Claims
- 1. A method for selectively addressing particular memory elements having hysteresis and forming an array of memory elements and for guarding the condition of memory elements other than those particular elements being selectively addressed, wherein the selectively addressed elements from said array are excited to one of a relatively positive or negative condition, each of said elements of the array comprising the intersection of a respective x and a respective y-line, some of said x-lines driven with a particular normalized selection signal having an amplitude of either 0 or 2/3, and some of said y-lines driven with a particular normalized selection signal having an amplitude of either 0, 1/3 or 1, said method including the steps of:
- at least one selectively addressed element of the array being turned off by exciting said element to the negative condition by driving the respective x-line thereof with a normalized selection signal having amplitude 2/3 and driving the respective y-line thereof with a normalized selection signal having amplitude 1, and
- at least one other selectively addressed element of the array being turned on by exciting said element to the positive condition by driving the respective x-line thereof with a normalized selection signal having amplitude 0 and driving the respective y-line thereof with a normalized selection signal having amplitude 1.
- 2. The method recited in claim 1, including selecting the elements comprising said array from a ferroelectric material.
- 3. The method recited in claim 1, including selecting the elements comprising said array from a ferromagnetic material.
- 4. The method recited in claim 1 including the further step of driving said x-line at an interval of time before driving said y-line for exciting the particular element of said array to the negative condition.
- 5. The method recited in claim 4, including the further step of terminating said x-line selection signal at an interval of time later than the terminating of said y-line selection signal.
- 6. The method recited in claim 1, including the further step of initially polarizing the particular element of said array to the negative remanant state.
- 7. The method recited in claim 1, wherein the condition of each of the elements of said array other than the particular elements being selectively addressed is guarded by the steps of:
- driving said x-line with a normalized selection signal having amplitude 2/3; and
- driving said y-line with a normalized selection signal having amplitude 1/3.
- 8. The method recited in claim 7, including the further step of driving said x-line at an interval of time after the driving of said y-line for guarding the condition of said elements.
- 9. The method recited in claim 8, including the further step of terminating said x-line selection signal at an interval of time before the terminating of said y-line selection signal.
- 10. The method recited in claim 1, wherein the condition of each of the elements of said array other than the particular elements being selectively addressed is guarded by the steps of:
- driving said x-line with a selection signal having amplitude 0; and
- driving said y-line with a normalized selection signal having amplitude 1/3.
- 11. The method recited in claim 1, said array forming an information display memory.
CROSS REFERENCES TO RELATED APPLICATIONS
This patent application is a continuation of Ser. No. 678,501 filed Apr. 19, 1976, and now abandoned.
Government Interests
The invention described herein was made in the performance of work under NASA Contract No. NASl-12228 and is subject to the provisions of section 305 of the National Aeronautics and Space Act of 1958 (72 Stat. 435; 42 U.S.C. 2457).
US Referenced Citations (3)
Continuations (1)
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Number |
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678501 |
Apr 1976 |
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