The scaling of CMOS technology leads to a greater difficulty in the integration of both floating gate memory and logic together for high performance and low power system-on-chip (SoC). The floating gate memory provides multi-time programmable memory (MTP) and embedded Flash memory. Embedded Flash memory is typically 2 or 3 nodes behind leading edge CMOS technology, because of the complexity of integrating additional processing (which also increases the costs). As a result, one-time programmable (OTP) memory is being used increasingly for embedded non-volatile memory (NVM) applications.
Two types of OTP memory are available on CMOS technology at or below 65 nm: electrical fuse (eFuse) and anti-fuse. An eFuse memory element is programmed by forcing a high current density through a conductive link in order to completely rupture it or make its resistance significantly higher such that the link is no longer conductive (the link is high resistance or open circuit). Anti-fuse is the opposite of an eFuse. The circuit is originally open (high resistance) and is programmed by applying electrical stress that creates a low resistance conductive path.
Neither eFuse or anti-fuse memory require additional process steps in a standard CMOS process; however as eFuse requires high current, it is programmed during production of the device and is not suited to programming during the operation of the chip on which it resides. The memory footprint of eFuse memory is also large and does not scale well with technology. Anti-fuse memory is low power such that a memory cell can be programmed at any stage and the memory footprint is smaller and scales with technology.
The use of charge trapping in MOS transistors, and in particular using hot carrier injection for programming, has been developed. However, programming typically requires high power and has low programming efficiency.
The embodiments described below are not limited to implementations which solve any or all of the disadvantages of known non-volatile memory.
This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
A one-time programmable (OTP) charge-trapping non-volatile memory (NVM) device is described. In an embodiment, an OTP transistor is formed using a thick gate oxide typically used in producing an I/O MOS transistor and source/drain extensions which are highly doped, shallow and include pocket implants and which are typically used in producing a CORE thin-oxide MOS transistor. In an optimization, the OTP transistor may be formed with two narrow active areas instead of one wider active area. This provides increased performance compared to a device with a wider active area and reduced variability compared to a device with one narrow active area. In another embodiment, a dual gate oxide CMOS technology provides three types of transistor; a thin oxide device, a thick oxide device, and a thick oxide device using the implant type of the thin oxide device for providing an OTP charge-trapping NVM device.
Many of the attendant features will be more readily appreciated as the same becomes better understood by reference to the following detailed description considered in connection with the accompanying drawings. The preferred features may be combined as appropriate, as would be apparent to a skilled person, and may be combined with any of the aspects of the invention.
Embodiments of the invention will be described, by way of example, with reference to the following drawings, in which:
Like reference numerals are used to designate like parts in the accompanying drawings. It will be appreciated that the schematic diagrams showing cross-sections (e.g.
Embodiments of the present invention are described below by way of example only. These examples represent the best ways of putting the invention into practice that are currently known to the Applicant although they are not the only ways in which this could be achieved. The description sets forth the functions of the example and the sequence of steps for constructing and operating the example. However, the same or equivalent functions and sequences may be accomplished by different examples.
It will be understood that the phrase ‘CMOS technology’ is used herein to refer to a defined set of processes and options for the design and manufacture of CMOS devices. The phrase is not intended to be restrictive and should be read to also include BiCMOS and other process variants to which the following disclosure also applies.
The use of the word implant or implant condition is used in this disclosure to refer to any method by which dopants are introduced into CMOS devices, for example, but not limited to, ion implantation. The methods and techniques described herein are independent of the methods used to introduce dopants.
Where references are made to mask properties, the term ‘open’ or ‘opening’ is used to indicate that during wafer processing, the mask causes the creation of a related feature (i.e. oxide or implant) at that location. This term is used for convenience and is not intended to indicate that the physical mask has an actual opening, but is rather indicative of the function of the area of the mask.
CMOS technologies generally provide two types of MOSFET, a thin-oxide (core) MOSFET and a thick-oxide (I/O) MOSFET. The core devices are optimized to provide high switching speed and high integration density, while the I/O devices are designed to provide a robust interface to external components at voltages higher than can be tolerated in the core devices.
Process options for multiple threshold voltages in core devices are generally provided, but each option requires additional masking steps to adjust the channel doping. Furthermore, beyond the 65 nm process node, pocket implants are generally used to define transistor type, rather than well and channel implants. Different device types therefore have very similar long-channel threshold voltages and so low-threshold short-channel devices are not useful to increase the available voltage headroom in long-channel devices for analogue circuits.
Additional types of transistor can be provided by the use of additional processing steps. However, such an approach is expensive and development often lags behind leading-edge CMOS technologies.
It has now been shown that a transistor having an improved performance can be fabricated by combining certain features from thin and thick oxide transistors in a dual oxide CMOS technology.
The conventional CMOS technology provides two types of transistor, however, by using different combinations of process steps (gate oxides and doping schemes) three or four types of transistor can be provided. Where the term conventional CMOS technology is used herein it is used to describe a technology providing base devices from which features may be combined according to the current disclosure. This description has been given in the context of a technology providing two transistor types for different supply voltages, but the conventional CMOS technology to which the methods described herein may be applied may provide more than two transistor types. Similarly, the methods described herein apply to all modifications and variants of the basic CMOS processes.
The provision of the AVT transistor 12 by the modified CMOS technology does not require any additional processing or development beyond the core 10 and I/O 11 devices provided by the conventional CMOS technology. The AVT transistor can therefore be provided without additional cost or manufacturing cycle time.
The AVT transistor may be provided by an extension of the Process Design Kit (PDK) in relation to the CMOS technology. The provision of new rules, design options and models allow the use of the new AVT transistor within designs using the modified CMOS technology. As explained previously, the provision of the new transistor type does not require additional processing steps and so the wafer manufacturing process remains conventional, although new mask layouts are created by the new rules which lead to the definition of new, previously unavailable, combinations of devices in the ICs formed according to the modified CMOS technology.
For the core device 20 the NLDD_CORE implant mask 21 (LDD/pocket for thin gate oxide devices) is open but the NLDD_IO implant mask 22 (LDD/pocket mask for thick gate oxide devices) is closed. In contrast the NLDD_IO implant mask 22 is open for the I/O device 23, but the NLDD implant mask 21 is closed. The thick oxide mask 24 is open only for the thick-oxide I/O device 23. For the avoidance of doubt, for devices where the thick oxide mask is closed, a thin oxide is assumed to be present.
For the conventional devices, the NLDD_CORE mask 21 can therefore be written logically as [N+ AND ACTIVE-AREA NOT THICK-OXIDE], and the NLDD_IO mask 22 can be written logically as [N+ AND ACTIVE-AREA AND THICK-OXIDE].
The AVT device 25 utilizes a new combination of features for the NLDD_IO mask 22, and introduces the combination [N+ AND ACTIVE-AREA AND AVT_LDD], where AVT_LDD is a marker layer marking AVT devices.
The AVT device of the current disclosure is thus obtained by new features of the PDK utilized in the design of integrated circuits and in the mask manufacture process. The modified CMOS technology provides new combinations of mask openings to provide the AVT device without adding process steps. An AVT device is thus characterized by utilizing a combination of features from the core and I/O devices provided by the conventional CMOS technology.
ICs utilizing the modified CMOS technology incorporating the AVT device may be characterized by presence of devices sharing features with more than one other type of device in the chip, in particular sharing an oxide layer with one type of device, and implants with another type of device. More particularly, the AVT device shares an oxide layer with a thin-oxide core transistor and implants with a thick-oxide I/O transistor. In a further embodiment a transistor may share an oxide layer with a thick-oxide I/O transistor and implants with a thin-oxide core transistor, as described in more detail below with reference to
Data is presented below demonstrating the expected performance of AVT devices. Unless otherwise stated
At channel lengths significantly larger than the minimum length, the LVT, SVT and HVT devices all have very similar threshold voltages due to the use of pocket implants to generate the variants as opposed to channel implants. The pocket implants also lead to the reverse-short channel effect seen in the graph.
The AVT device provides a lower threshold voltage and retains the VT roll-off of the I/O device. The better gate control provided by the use of a thin-oxide gives a smaller difference in VT between L=10 μm and 0.23 μm compared to the I/O device.
As described above, in a further embodiment, a transistor may share an oxide layer with a thick oxide I/O transistor and implants with a thin-oxide core transistor in a dual oxide CMOS technology.
The thick oxide layer 902 in the OTP MOS device 900 may, for example, be 30-70 Å thick and in a particular example, the thick oxide layer 902 may be 52 Å thick. The source/drain extensions 904 are highly-doped, shallow and with pockets (as shown in
The use of thick gate oxide increases charge retention performance, due to lower tunneling probability compared with thinner oxide. However, when shallow and high dose source/drain extensions are implanted into the thick gate oxide, a high percentage of the implant species passes through the oxide and a part of it becomes lodged within the oxide. This creates additional charge traps along the edges of the gate and therefore introduces a process-induced trap area 1006 at the longitudinal gate edges. This process-induced trap area 1006 is focused on the key zones where the voltage threshold shift occurs because it is above the most doped channel areas. As a result, memory read margin of the OTP NVM device 900 is further enhanced because the process-induced trap area 1006 increases voltage threshold shift (as shown in
V
gs
@I
ds=10−7.W/L[A] with Vds=50mV
It can be seen from these results that the shortest and narrowest device (W=108 nm and L=162 nm) has the highest threshold value.
For the core device 20 the NLDD_CORE implant mask 1301 (LDD/pocket for thin gate oxide devices) is open but the NLDD_IO implant mask 1302 (LDD/pocket mask for thick gate oxide devices) is closed. In contrast the NLDD_IO implant mask 1302 is open for the I/O device 23, but the NLDD implant mask 1301 is closed. The thick oxide mask 1303 is open for the thick oxide I/O device 23 and not for the core device 20. The OTP device 1300 utilizes a new combination, with the thick oxide mask 1303 and NLDD_CORE implant mask 1301 open and the NLDD_IO implant mask 1302 closed. For the avoidance of doubt, for devices where the thick oxide mask is closed, a thin oxide is assumed to be present.
In a variation of the examples described above and where the CMOS process provides both SVT and HVT implants, an integrated circuit may be formed which comprises thin oxide transistors formed using SVT implants, thin oxide transistors formed using HVT implants and OTP transistors with thick oxide and using HVT implants. In a further variation, an OTP transistor may be formed with a thick oxide and an SRAM implant instead of using HVT implants. In such an instance, the SRAM mask may be modified instead of the HVT mask for formation of a particular OTP transistor. Consequently, where SRAM, SVT and HVT implants are all available, an integrated circuit may be formed which comprises thin oxide transistors formed using SVT implants, thin oxide transistors formed using HVT implants and OTP transistors with thick oxide and using SRAM implants.
In some examples, the highly-doped, shallow source/drain extensions with pockets may be formed in multiple steps to achieve transistors with different threshold voltages. In such an example, the implants resulting in the highest threshold voltage may be combined to form the OTP device.
The OTP device described herein is thus obtained by new features of the PDK utilized in the design of integrated circuits and in the mask layout process, e.g. the data preparation (Boolean algorithms) applied to the design data before mask manufacture commences. The modified CMOS technology provides new combinations of mask openings to provide the OTP device without adding process steps. An OTP device is thus characterized by utilizing a combination of features from the core and I/O devices provided by the conventional CMOS technology.
The new OTP NVM device described above exploits the combination of thick gate oxide and aggressive source/drain extensions for Fowler-Nordheim tunneling as a programming method. This results in low power requirements for programming so that bit-cell may be programmed during the operation of the chip (if required). In addition, the new charge trapping sites improve the data retention performance compared to other OTP transistors and can be used to provide reliable OTP devices. Data retention tests show that the threshold voltage shift remains greater than 500 mV after 10 years at 125° C. The device can be integrated on existing dual gate oxide CMOS technology without any additional masks or process steps.
The example designs and results shown in
The applicant hereby discloses in isolation each individual feature described herein and any combination of two or more such features, to the extent that such features or combinations are capable of being carried out based on the present specification as a whole in the light of the common general knowledge of a person skilled in the art, irrespective of whether such features or combinations of features solve any problems disclosed herein, and without limitation to the scope of the claims. The applicant indicates that aspects of the present invention may consist of any such individual feature or combination of features. In view of the foregoing description it will be evident to a person skilled in the art that various modifications may be made within the scope of the invention.
Any range or device value given herein may be extended or altered without losing the effect sought, as will be apparent to the skilled person.
It will be understood that the benefits and advantages described above may relate to one embodiment or may relate to several embodiments. The embodiments are not limited to those that solve any or all of the stated problems or those that have any or all of the stated benefits and advantages.
Any reference to ‘an’ item refers to one or more of those items. The term ‘comprising’ is used herein to mean including the method blocks or elements identified, but that such blocks or elements do not comprise an exclusive list and a method or apparatus may contain additional blocks or elements.
The steps of the methods described herein may be carried out in any suitable order, or simultaneously where appropriate. Additionally, individual blocks may be deleted from any of the methods without departing from the spirit and scope of the subject matter described herein. Aspects of any of the examples described above may be combined with aspects of any of the other examples described to form further examples without losing the effect sought.
It will be understood that the above description of a preferred embodiment is given by way of example only and that various modifications may be made by those skilled in the art. Although various embodiments have been described above with a certain degree of particularity, or with reference to one or more individual embodiments, those skilled in the art could make numerous alterations to the disclosed embodiments without departing from the spirit or scope of this invention.
Number | Date | Country | Kind |
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0909686.8 | Jun 2009 | GB | national |
98121178 | Jun 2009 | TW | national |
This application is a continuation in part of U.S. application Ser. No. 12/783,215, filed on May 19, 2010. That application claimed the benefit of GB Application No. 0909686.8, filed on Jun. 5, 2009, and TW Application No. 98121178, filed on Jun. 24, 2009. The disclosures of all these related applications are incorporated herein by reference in their entirety.
Number | Date | Country | |
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Parent | 12783215 | May 2010 | US |
Child | 13045754 | US |