Patent Application
20230185034
Embodiments described herein generally relate to photonic integrated circuits (PICs) for use in electronic devices such as computer systems.
Optical interconnects offer very high bandwidths compared to electrical interconnects, and PICs can be used to convert electrical signals to optical signals in systems offering optical interconnects. Open cavities in the substrate can be used to enable more direct PIC to electrical IC connection. However, open cavities can cause issues with heat generation and mechanical stresses, among other problems. It is desired to have an open cavity PIC that can address these concerns, and other technical challenges.
The following description and the drawings sufficiently illustrate specific embodiments to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Portions and features of some embodiments may be included in, or substituted for, those of other embodiments. Embodiments set forth in the claims encompass all available equivalents of those claims.
Optical interconnects offer very high bandwidths compared to electrical interconnects. Photonic ICs (PIC) are used to convert electrical signals to optical signals. Optical coupling is provided between a PIC and external packages to transfer optical signals out of the package. It is desirable to provide the PIC within an open cavity to enable direct electrical IC to PIC connection. Furthermore, it may be desirable to provide a relatively thin PIC (e.g., less than 50 microns (μm) thick) so that substrate routing layers are not consumed in cavity generation. However, providing such a thin PIC can make it more difficult to disperse or dissipate the heat that can be generated by any lasers that may be embedded in the open cavity PIC. In addition, with the open cavity PIC being embedded in the package substrate, a large coefficient of thermal expansion (CTE) difference may exist between the substrate and the open cavity PIC, and this difference can result in a large mechanical stress on the open cavity PIC. This mechanical stress can provide stress to any embedded laser as well, affecting laser performance and reliability.
Some current systems may address the above issues by placing a laser to one side of the open cavity PIC. However, this uses up valuable package real estate. In addition, because the laser in these solutions is mounted on the package substrate, the laser may still be subjected to stresses caused by the high CTE differential between the laser and substrate.
Systems and apparatuses according to various embodiments address these and other concerns by integrating a laser on the top of the open cavity PIC using, for example, a three-dimensional (3D) integration process. The heat generated by the laser can be conducted to an integrated heat spreader through a pedestal and thermal interface material (TIM), or through a thermo-electric cooler (TEC) and TIM.
In
In
The electronic device 300 can include an integrated circuit 320 coupled to the second surface of the PIC 308 for electrical communication external to the electronic device 300. The electronic device 300 can include a heat spreader 322 above the second laser circuitry surface 314. A pedestal 324 can couple the heat spreader 322 to the second laser circuitry surface 314. In embodiments, the pedestal 324 can be coupled to the second laser circuitry surface 314 through a thermal interface material (TIM) 326, which can include, for example a grease that is impregnated with thermal conductor particles (carbon, nanotubes, metals, etc.). In examples such as an example depicted in
Example embodiments as described with reference to
Open cavity PICs, and particularly thin (less than 50 μm) PICs, can be subject to warpage when attached or coupled to packages within electronic devices. Overhang of the PIC over the substrate edge, as shown above in
To address these and other concerns, packages in accordance with some embodiments can provide structures to prevent warpage of a PIC where optical fiber or a lens is attached.
The photonic circuit package 500 can include a substrate 502 having a substrate front surface 504 defining a cavity 506 that extends into the substrate front surface 504. The substrate 502 can further include a leading edge 508. The cavity 506 can have a cavity length 510. The photonic circuit package 500 can further include a PIC 512 attached to the substrate 502 within the cavity 506 at a first surface 514 of the PIC 512 and having a PIC length 516 greater than the cavity length 510 such that the PIC 512 extends beyond the leading edge 508 of the substrate 502. The PIC 512 can be about 30-200 μm thick.
The photonic circuit package 500 can include a die structure 518 that will not include circuitry but be comprised at least mostly of a structural material such as silicon (Si). The die structure 518 can be attached to a second surface 520 of the PIC 512 opposite the first surface 514 of the PIC 512. In some embodiments, the die structure 518 can extend past the leading edge 508.
In some example embodiments, an optical epoxy 522 can be attached to the PIC 512 at least at a portion of the PIC 512 that extends beyond the leading edge 508 of the substrate 502. The photonic circuit package 500 can comprise a lens 524 coupled to the optical epoxy 522 to provide optical communication from the PIC 512. The die structure 518 can provide further support for attachment of the lens 524, the optical epoxy 522, and a fiber attach unit 526. The die structure 518 can thermally connect the PIC 512 to a heat spreader 528 for cooling the PIC 512. The die structure 518 can further help stop capillary underfill (CUF) 530 from spreading to the optical attach side.
Alternative embodiments of the photonic circuit package are shown in
The method can continue with operation 704 with positioning a PIC 108 within the cavity 106 at a first surface 110 of the PIC 108. The method can continue with operation 706 by providing laser circuitry 112 communicably coupled to a second surface 114 of the PIC 108 opposite the first surface 110.
The method can further comprise providing a grating coupler 200 within the second surface 114 of the PIC 108 and providing at least one of a GC 202 at a surface of the laser circuitry 112 facing the PIC 108 and a mirror apparatus 204 at the surface of the laser circuitry facing the PIC 108 for communication with the GC 200 within the second surface 114 of the PIC 108.
In one embodiment, processor 810 has one or more processor cores 812 and 812N, where 612N represents the Nth processor core inside processor 810 where N is a positive integer. In one embodiment, system 800 includes multiple processors including 810 and 805, where processor 805 has logic similar or identical to the logic of processor 810. In some embodiments, processing core 812 includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions and the like. In some embodiments, processor 810 has a cache memory 816 to cache instructions and/or data for system 800. Cache memory 816 may be organized into a hierarchal structure including one or more levels of cache memory.
In some embodiments, processor 810 includes a memory controller 814, which is operable to perform functions that enable the processor 810 to access and communicate with memory 830 that includes a volatile memory 832 and/or a non-volatile memory 834. In some embodiments, processor 810 is coupled with memory 830 and chipset 820. Processor 810 may also be coupled to a wireless antenna 878 to communicate with any device configured to transmit and/or receive wireless signals. In one embodiment, an interface for wireless antenna 878 operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.
In some embodiments, volatile memory 832 includes, but is not limited to, Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM), and/or any other type of random access memory device. Non-volatile memory 834 includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.
Memory 830 stores information and instructions to be executed by processor 810. In one embodiment, memory 830 may also store temporary variables or other intermediate information while processor 810 is executing instructions. In the illustrated embodiment, chipset 820 connects with processor 810 via Point-to-Point (PtP or P-P) interfaces 817 and 822. Chipset 620 enables processor 810 to connect to other elements in system 800. In some embodiments of the example system, interfaces 817 and 822 operate in accordance with a PtP communication protocol such as the Intel® QuickPath Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used.
In some embodiments, chipset 820 is operable to communicate with processor 810, 805N, display device 840, and other devices, including a bus bridge 872, a smart TV 876, I/O devices 874, nonvolatile memory 860, a storage medium (such as one or more mass storage devices) 862, a keyboard/mouse 864, a network interface 866, and various forms of consumer electronics 877 (such as a PDA, smart phone, tablet etc.), etc. In one embodiment, chipset 820 couples with these devices through an interface 824. Chipset 820 may also be coupled to a wireless antenna 878 to communicate with any device configured to transmit and/or receive wireless signals. In one example, any combination of components in a chipset may be separated by a continuous flexible shield as described in the present disclosure.
Chipset 820 connects to display device 840 via interface 826. Display 840 may be, for example, a liquid crystal display (LCD), a light emitting diode (LED) array, an organic light emitting diode (OLED) array, or any other form of visual display device. In some embodiments of the example system, processor 810 and chipset 820 are merged into a single SOC. In addition, chipset 820 connects to one or more buses 850 and 855 that interconnect various system elements, such as I/O devices 874, nonvolatile memory 860, storage medium 862, a keyboard/mouse 864, and network interface 866. Buses 850 and 855 may be interconnected together via a bus bridge 872.
In one embodiment, mass storage device 862 includes, but is not limited to, a solid state drive, a hard disk drive, a universal serial bus flash memory drive, or any other form of computer data storage medium. In one embodiment, network interface 866 is implemented by any type of well-known network interface standard including, but not limited to, an Ethernet interface, a universal serial bus (USB) interface, a Peripheral Component Interconnect (PCI) Express interface, a wireless interface and/or any other suitable type of interface. In one embodiment, the wireless interface operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.
While the modules shown in
To better illustrate the method and apparatuses disclosed herein, a non-limiting list of embodiments is provided here:
Example 1 includes a laser package, comprising: a substrate having a substrate front surface and defining a cavity that extends into the substrate front surface; a photonic integrated circuit (PIC) attached to the substrate within the cavity at a first surface of the PIC; and laser circuitry communicably coupled to a second surface of the PIC opposite the first surface.
Example 2 includes the laser package of example 1, wherein the second surface of the PIC includes a grating coupler (GC).
Example 3 includes the laser package of any one of examples 1-2, wherein the laser circuitry includes a GC at a surface of the laser circuitry facing the PIC, and wherein the laser circuitry and the PIC communicate using GC-to-GC communication.
Example 4 includes the laser package of any one of examples 1-3, wherein the laser circuitry includes a mirror apparatus at a surface of the laser circuitry facing the PIC, and wherein the laser circuitry and the PIC communicate using mirror-to-GC communication.
Example 5 includes the laser package of any one of examples 1-4, further comprising a prism configured to provide communication between the laser circuitry and the GC on the second surface of the PIC.
Example 6 includes the laser package of any of examples 1-5, wherein the second surface of the PIC includes a lens, the laser circuitry includes a lens at a surface of the laser circuitry facing the PIC, and wherein the laser circuitry and the PIC communicate using lens-to-lens communication.
Example 7 includes the laser package of any of examples 1-6, wherein the PIC is less than 100 micrometers thick.
Example 8 includes the laser package of any of examples 1-7, wherein the PIC is less than 50 micrometers thick.
Example 9 includes the laser package of any of examples 1-8, wherein the PIC overhangs past an outer edge of the substrate for an overhang portion.
Example 10 includes the laser package of any of examples 1-9, wherein at least a portion of the laser circuitry extends over at least a portion of the overhang portion.
Example 11 includes an electronic device comprising a substrate having a substrate front surface and defining a cavity that extends into the substrate front surface; a photonic integrated circuit (PIC) attached to the substrate within the cavity at a first surface of the PIC; laser circuitry, having a first laser circuitry surface and a second laser circuitry surface, communicably coupled at a first surface to a second surface of the PIC opposite the first surface; an integrated circuit coupled to the second surface of the PIC for electrical communication external to the electronic device, and a heat spreader above the second laser circuitry surface.
Example 12 includes an electronic device of example 11, and optionally further comprising a pedestal to couple the heat spreader to the second laser circuitry surface.
Example 13 includes an electronic device of any of examples 11-12, and optionally wherein the pedestal is coupled to the second laser circuitry surface through a thermal interface material.
Example 14 includes an electronic device of any of examples 11-13, and optionally further comprising a thermal interface material and a thermo-electric cooler to couple the heat spreader to the second laser circuitry surface.
Example 15 includes an electronic device of any of examples 11-14, optionally wherein the second surface of the PIC includes a grating coupler (GC), the laser circuitry includes a GC at a surface of the laser circuitry facing the PIC, and the laser circuitry and the PIC communicate using GC-to-GC communication.
Example 16 includes an electronic device of any of examples 11-15, optionally wherein the second surface of the PIC includes a grating coupler (GC), the laser circuitry includes a mirror apparatus at a surface of the laser circuitry facing the PIC, and the laser circuitry and the PIC communicate using mirror-to-GC communication.
Example 17 is a method for assembling a laser package, the method comprising: providing a substrate, the substrate having a substrate front surface and defining a cavity that extends into the substrate front surface; positioning a photonic integrated circuit (PIC) within the cavity at a first surface of the PIC; and providing laser circuitry communicably coupled to a second surface of the PIC opposite the first surface.
Example 18 includes the method of example 17, and optionally further comprising providing a grating coupler (GC) within the second surface of the PIC; and providing at least one of a GC at a surface of the laser circuitry facing the PIC and a mirror apparatus at the surface of the laser circuitry facing the PIC for communication with the GC within the second surface of the PIC.
Example 19 includes a photonic circuit package comprising a substrate having a substrate front surface defining a cavity that extends into the substrate front surface, the substrate further including a leading edge and the cavity having a cavity length; a photonic integrated circuit (PIC) attached to the substrate within the cavity at a first surface of the PIC and having a PIC length greater than the cavity length such that the PIC extends beyond the leading edge of the substrate; and a die structure comprised of a structural material, the die structure attached to a second surface of the PIC opposite the first surface of the PIC.
Example 20 includes the photonic circuit package of example 19, and optionally wherein the die structure extends past the leading edge.
Example 21 includes the photonic circuit package of any of examples 19-20 wherein an optical epoxy is attached to the PIC at least at a portion of the PIC that extends beyond the leading edge of the substrate.
Example 22 includes the photonic circuit package of any of examples 19-21, and optionally further comprising a fiber attach mechanism coupled to the optical epoxy, and an optical fiber within the fiber attach mechanism to provide optical communication from the PIC.
Example 23 includes the photonic circuit package of any of examples 19-22, optionally further comprising a lens coupled to the optical epoxy to provide optical communication from the PIC.
Throughout this specification, plural instances may implement components, operations, or structures described as a single instance. Although individual operations of one or more methods are illustrated and described as separate operations, one or more of the individual operations may be performed concurrently, and nothing requires that the operations be performed in the order illustrated. Structures and functionality presented as separate components in example configurations may be implemented as a combined structure or component. Similarly, structures and functionality presented as a single component may be implemented as separate components. These and other variations, modifications, additions, and improvements fall within the scope of the subject matter herein.
Although an overview of the inventive subject matter has been described with reference to specific example embodiments, various modifications and changes may be made to these embodiments without departing from the broader scope of embodiments of the present disclosure. Such embodiments of the inventive subject matter may be referred to herein, individually, or collectively, by the term “invention” merely for convenience and without intending to voluntarily limit the scope of this application to any single disclosure or inventive concept if more than one is, in fact, disclosed.
The embodiments illustrated herein are described in sufficient detail to enable those skilled in the art to practice the teachings disclosed. Other embodiments may be used and derived therefrom, such that structural and logical substitutions and changes may be made without departing from the scope of this disclosure. The Detailed Description, therefore, is not to be taken in a limiting sense, and the scope of various embodiments is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled.
As used herein, the term “or” may be construed in either an inclusive or exclusive sense. Moreover, plural instances may be provided for resources, operations, or structures described herein as a single instance. Additionally, boundaries between various resources, operations, modules, engines, and data stores are somewhat arbitrary, and particular operations are illustrated in a context of specific illustrative configurations. Other allocations of functionality are envisioned and may fall within a scope of various embodiments of the present disclosure. In general, structures and functionality presented as separate resources in the example configurations may be implemented as a combined structure or resource. Similarly, structures and functionality presented as a single resource may be implemented as separate resources. These and other variations, modifications, additions, and improvements fall within a scope of embodiments of the present disclosure as represented by the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
The foregoing description, for the purpose of explanation, has been described with reference to specific example embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the possible example embodiments to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The example embodiments were chosen and described in order to best explain the principles involved and their practical applications, to thereby enable others skilled in the art to best utilize the various example embodiments with various modifications as are suited to the particular use contemplated.
It will also be understood that, although the terms “first,” “second,” and so forth may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first contact could be termed a second contact, and, similarly, a second contact could be termed a first contact, without departing from the scope of the present example embodiments. The first contact and the second contact are both contacts, but they are not the same contact.
The terminology used in the description of the example embodiments herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used in the description of the example embodiments and the appended examples, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
As used herein, the term “if” may be construed to mean “when” or “upon” or “in response to determining” or “in response to detecting,” depending on the context. Similarly, the phrase “if it is determined” or “if [a stated condition or event] is detected” may be construed to mean “upon determining” or “in response to determining” or “upon detecting [the stated condition or event]” or “in response to detecting [the stated condition or event],” depending on the context.
