Electrical signaling and processing is one technique for signal transmission and processing. Optical signaling and processing have been used in increasingly more applications in recent years, particularly due to the use of optical fiber-related applications for signal transmission.
Optical signaling and processing are typically combined with electrical signaling and processing to provide full-fledged applications. For example, optical fibers may be used for long-range signal transmission, and electrical signals may be used for short-range signal transmission as well as processing and controlling. Accordingly, devices integrating long-range optical components and short-range electrical components are formed for the conversion between optical signals and electrical signals, as well as the processing of optical signals and electrical signals. Packages thus may include both optical (photonic) dies including optical devices and electronic dies including electronic devices.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
Embodiments will now be discussed with respect to certain embodiments in which a multi-tier connector is utilized to provide multiple inputs into an optical device. The embodiments presented, however, are intended to be illustrative and are not intended to limit the ideas presented to the precise embodiments described. Rather, the ideas presented may be incorporated into a wide variety of embodiments, and all such embodiments may be included within the overall scope of the disclosure.
With reference now to
The first insulator layer 103 may be a dielectric layer that separates the first substrate 101 from the overlying first active layer 201 and can additionally, in some embodiments, serve as a portion of cladding material that surrounds the subsequently manufactured first optical components 203 (discussed further below). In an embodiment the first insulator layer 103 may be silicon oxide, silicon nitride, germanium oxide, germanium nitride, combinations of these, or the like, formed using a method such as implantation (e.g., to form a buried oxide (BOX) layer) or else may be deposited onto the first substrate 101 using a deposition method such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, combinations of these, or the like. However, any suitable material and method of manufacture may be used.
The material 105 for the first active layer 201 is initially (prior to patterning) a conformal layer of material that will be used to begin manufacturing the first active layer 201 of the first optical components 203. In an embodiment the material 105 for the first active layer 201 may be a translucent material that can be used as a core material for the desired first optical components 203, such as a semiconductor material such as silicon, germanium, silicon germanium, combinations of these, or the like, while in other embodiments the material 105 for the first active layer 201 may be a dielectric material such as silicon nitride or the like, although in other embodiments the material 105 for the first active layer 201 may be III-V materials, lithium niobate materials, or polymers. In embodiments in which the material 105 of the first active layer 201 is deposited, the material 105 for the first active layer 201 may be deposited using a method such as epitaxial growth, chemical vapor deposition, atomic layer deposition, physical vapor deposition, combinations of these, or the like. In other embodiments in which the first insulator layer 103 is formed using an implantation method, the material 105 of the first active layer 201 may initially be part of the first substrate 101 prior to the implantation process to form the first insulation layer 103. However, any suitable materials and methods of manufacture may be utilized to form the material 105 of the first active layer 201.
To begin forming the first active layer 201 of first optical components 203 from the initial material, the material 105 for the first active layer 201 may be patterned into the desired shapes for the first active layer 201 of first optical components 203. In an embodiment the material 105 for the first active layer 201 may be patterned using, e.g., one or more photolithographic masking and etching processes. However, any suitable method of patterning the material 105 for the first active layer 201 may be utilized. For some of the first optical components 203, such as waveguides or edge couplers, the patterning process may be all or at least most of the manufacturing that is used to form these first optical components 203 components.
Additionally, during the manufacture of the first metallization layers 501, one or more second optical components 503 may be formed as part of the first metallization layers 501. In some embodiments the second optical components 503 of the first metallization layers 501 may include such components as couplers (e.g., edge couplers, grating couplers, etc.) for connection to outside signals, optical waveguides (e.g., ridge waveguides, rib waveguides, buried channel waveguides, diffused waveguides, etc.), optical modulators (e.g., Mach-Zehnder silicon-photonic switches, microelectromechanical switches, micro-ring resonators, etc.), amplifiers, multiplexors, demultiplexors, optical-to-electrical converters (e.g., P-N junctions), electrical-to-optical converters, lasers, combinations of these, or the like. However, any suitable optical components may be used for the one or more second optical components 503.
In an embodiment the one or more second optical components 503 may be formed by initially depositing a material for the one or more second optical components 503. In an embodiment the material for the one or more second optical components 503 may be a dielectric material such as silicon nitride, silicon oxide, combinations of these, or the like, or a semiconductor material such as silicon, deposited using a deposition method such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, combinations of these, or the like. However, any suitable material and any suitable method of deposition may be utilized.
Once the material for the one or more second optical components 503 has been deposited or otherwise formed, the material may be patterned into the desired shapes for the one or more second optical components 503. In an embodiment the material of the one or more second optical components 503 may be patterned using, e.g., one or more photolithographic masking and etching processes. However, any suitable method of patterning the material for the one or more second optical components 503 may be utilized.
For some of the one or more second optical components 503, such as waveguides or edge couplers, the patterning process may be all or at least most manufacturing that is used to form these components. Additionally, for those components that utilize further manufacturing processes, such as Mach-Zehnder silicon-photonic switches that utilize resistive heating elements, additional processing may be performed either before or after the patterning of the material for the one or more second optical components 503. For example, implantation processes, additional deposition and patterning processes for different materials, combinations of all of these processes, or the like, and can be utilized to help further the manufacturing of the various desired one or more second optical components 503. All such manufacturing processes and all suitable one or more second optical components 503 may be manufactured, and all such combinations are fully intended to be included within the scope of the embodiments.
Once the one or more second optical components 503 of the first metallization layers 501 have been manufactured, a first bonding layer 505 is formed over the first metallization layers 501. In an embodiment, the first bonding layer 505 may be used for a dielectric-to-dielectric and metal-to-metal bond. In accordance with some embodiments, the first bonding layer 505 is formed of a first dielectric material 509 such as silicon oxide, silicon nitride, or the like. The first dielectric material 509 may be deposited using any suitable method, such as CVD, high-density plasma chemical vapor deposition (HDPCVD), PVD, atomic layer deposition (ALD), or the like. However, any suitable materials and deposition processes may be utilized.
Once the first dielectric material 509 has been formed, first openings in the first dielectric material 509 are formed to expose conductive portions of the underlying layers in preparation to form first bond pads 507 within the first bonding layer 505. Once the first openings have been formed within the first dielectric material 509, the first openings may be filled with a seed layer and a plate metal to form the first bond pads 507 within the first dielectric material 509. The seed layer may be blanket deposited over top surfaces of the first dielectric material 509 and the exposed conductive portions of the underlying layers and sidewalls of the openings and the second openings. The seed layer may comprise a copper layer. The seed layer may be deposited using processes such as sputtering, evaporation, or plasma-enhanced chemical vapor deposition (PECVD), or the like, depending upon the desired materials. The plate metal may be deposited over the seed layer through a plating process such as electrical or electro-less plating. The plate metal may comprise copper, a copper alloy, or the like. The plate metal may be a fill material. A barrier layer (not separately illustrated) may be blanket deposited over top surfaces of the first dielectric material 509 and sidewalls of the openings and the second openings before the seed layer. The barrier layer may comprise titanium, titanium nitride, tantalum, tantalum nitride, or the like.
Following the filling of the first openings, a planarization process, such as a CMP, is performed to remove excess portions of the seed layer and the plate metal, forming the first bond pads 507 within the first bonding layer 505. In some embodiments a bond pad via (not separately illustrated) may also be utilized to connect the first bond pads 507 with underlying conductive portions and, through the underlying conductive portions, connect the first bond pads 507 with the first metallization layers 501.
Additionally, the first bonding layer 505 may also include one or more third optical components 511 incorporated within the first bonding layer 505. In such an embodiment, prior to the deposition of the first dielectric material 509, the one or more third optical components 511 may be manufactured using similar methods and similar materials as the one or more second optical components 503 (described above), such as by being waveguides and other structures formed at least in part through a deposition and patterning process. However, any suitable structures, materials and any suitable methods of manufacture may be utilized.
In an embodiment the first semiconductor device 601 may be configured to work with the optical interposer 100 for a desired functionality. In some embodiments the first semiconductor device 601 may be a high bandwidth memory (HBM) module, an xPU, a logic die, a 3DIC die, a CPU, a GPU, a SoC die, a MEMS die, combinations of these, or the like. Any suitable device with any suitable functionality, may be used, and all such devices are fully intended to be included within the scope of the embodiments.
In an embodiment the first semiconductor device 601 and the first bonding layer 505 may be bonded using a dielectric-to-dielectric and metal-to-metal bonding process. In a particular embodiment which utilizes a dielectric-to-dielectric and metal-to-metal bonding process, the process may be initiated by activating the surfaces of the second bonding layer 609 and the surfaces of the first bonding layer 505. Activating the top surfaces of the first bonding layer 505 and the second bonding layer 609 may comprise a dry treatment, a wet treatment, a plasma treatment, exposure to an inert gas plasma, exposure to H2, exposure to N2, exposure to O2, combinations thereof, or the like, as examples. In embodiments where a wet treatment is used, an RCA cleaning may be used, for example. In another embodiment, the activation process may comprise other types of treatments. The activation process assists in the bonding of the first bonding layer 505 and the second bonding layer 609.
After the activation process the optical interposer 100 and the first semiconductor device 601 may be cleaned using, e.g., a chemical rinse, and then the first semiconductor device 601 is aligned and placed into physical contact with the optical interposer 100. The optical interposer 100 and the first semiconductor device 601 are then subjected to thermal treatment and contact pressure to bond the optical interposer 100 and the laser die 600. For example, the optical interposer 100 and the first semiconductor device 601 may be subjected to a pressure of about 200 kPa or less, and a temperature between about 25° C. and about 250° C. to fuse the optical interposer 100 and the first semiconductor device 601. The optical interposer 100 and the first semiconductor device 601 may then be subjected to a temperature at or above the eutectic point for material of the first bond pads 507 and the third bond pads 611, e.g., between about 150° C. and about 650° C., to fuse the metal. In this manner, the optical interposer 100 and the first semiconductor device 601 forms a dielectric-to-dielectric and metal-to-metal bonded device. In some embodiments, the bonded dies are subsequently baked, annealed, pressed, or otherwise treated to strengthen or finalize the bond.
Additionally, while specific processes have been described to initiate and strengthen the bonds, these descriptions are intended to be illustrative and are not intended to be limiting upon the embodiments. Rather, any suitable combination of baking, annealing, pressing, or combination of processes may be utilized. All such processes are fully intended to be included within the scope of the embodiments.
Once the first gap-fill material 613 has been deposited, the first gap-fill material 613 may be planarized in order to expose the first semiconductor device 601. In an embodiment the planarization process may be a chemical mechanical planarization process, a grinding process, or the like. However, any suitable planarization process may be utilized.
Once the first substrate 101 and the first insulator layer 103 have been removed, a second active layer 801 of fourth optical components 803 may be formed on a back side of the first active layer 201. In an embodiment the second active layer 801 of fourth optical components 803 may be formed using similar materials and similar processes as the second optical components 503 of the first metallization layers 501 (described above with respect to
Once the through device via openings have been formed within the optical interposer 100, the through device via openings may be lined with a liner. The liner may be, e.g., an oxide formed from tetraethylorthosilicate (TEOS) or silicon nitride, although any suitable dielectric material may alternatively be used. The liner may be formed using a plasma enhanced chemical vapor deposition (PECVD) process, although other suitable processes, such as physical vapor deposition or a thermal process, may also be used.
Once the liner has been formed along the sidewalls and bottom of the through device via openings, a barrier layer (also not independently illustrated) may be formed and the remainder of the through device via openings may be filled with first conductive material. The first conductive material may comprise copper, although other suitable materials such as aluminum, alloys, doped polysilicon, combinations thereof, and the like, may be utilized. The first conductive material may be formed by electroplating copper onto a seed layer (not shown), filling and overfilling the through device via openings. Once the through device via openings have been filled, excess liner, barrier layer, seed layer, and first conductive material outside of the through device via openings may be removed through a planarization process such as chemical mechanical polishing (CMP), although any suitable removal process may be used.
Optionally, in some embodiments once the first through device vias 901 have been formed, second metallization layers (not separately illustrated in
The third bonding layer 903 is formed in order to provide electrical connections between the optical interposer 100 and subsequently attached devices. In an embodiment the third bonding layer 903 may be similar to the first bonding layer 505, such as having third bond pads 909 (similar to the first bond pads 507) and even fifth optical components 911 (similar to the third optical components 511). However, any suitable devices may be utilized.
Optionally, first active devices (not separately illustrated) may be added to the semiconductor substrate 1003. The first active devices comprise a wide variety of active devices and passive devices such as capacitors, resistors, inductors and the like that may be used to generate the desired structural and functional requirements of the design for the semiconductor substrate 1003. The first active devices may be formed using any suitable methods either within or else on the semiconductor substrate 1003.
The third metallization layers are formed over the semiconductor substrate 1003 and the first active devices and are designed to connect the various devices to form functional circuitry. In an embodiment the third metallization layers are formed of alternating layers of dielectric (e.g., low-k dielectric materials, extremely low-k dielectric material, ultra low-k dielectric materials, combinations of these, or the like) and conductive material and may be formed through any suitable process (such as deposition, damascene, dual damascene, etc.). However, any suitable materials and processes may be utilized.
Additionally, if desired, the third metallization layers may further comprise interposer optical components that can interact with the fifth optical components 911 of the first optical package 900. In an embodiment the interposer optical components can be formed using similar methods and materials as the third optical components 511 described above with respect to
Additionally, at any desired point in the manufacturing process, the third TDVs 1007 may be formed within the semiconductor substrate 1003 and, if desired, one or more layers of the third metallization layers, in order to provide electrical connectivity from a front side of the semiconductor substrate 1003 to a back side of the semiconductor substrate 1003. In an embodiment the third TDVs 1007 may be formed by initially forming through device via (TDV) openings into the semiconductor substrate 1003 and, if desired, any of the overlying third metallization layers (e.g., after the desired third metallization layer has been formed but prior to formation of the next overlying third metallization layer). The TDV openings may be formed by applying and developing a suitable photoresist, and removing portions of the underlying materials that are exposed to a desired depth. The TDV openings may be formed so as to extend into the semiconductor substrate 1003 to a depth greater than the eventual desired height of the semiconductor substrate 1003.
Once the TDV openings have been formed within the semiconductor substrate 1003 and/or any third metallization layers, the TDV openings may be lined with a liner. The liner may be, e.g., an oxide formed from tetraethylorthosilicate (TEOS) or silicon nitride, although any suitable dielectric material may be used. The liner may be formed using a plasma enhanced chemical vapor deposition (PECVD) process, although other suitable processes, such as physical vapor deposition or a thermal process, may be used.
Once the liner has been formed along the sidewalls and bottom of the TDV openings, a barrier layer may be formed and the remainder of the TDV openings may be filled with first conductive material. The first conductive material may comprise copper, although other suitable materials such as aluminum, alloys, doped polysilicon, combinations thereof, and the like, may be utilized. The first conductive material may be formed by electroplating copper onto a seed layer, filling and overfilling the TDV openings. Once the TDV openings have been filled, excess liner, barrier layer, seed layer, and first conductive material outside of the TDV openings may be removed through a planarization process such as chemical mechanical polishing (CMP), although any suitable removal process may be used.
Once the TDV openings have been filled, the semiconductor substrate 1003 may be thinned until the third TDVs 1007 have been exposed. In an embodiment the semiconductor substrate 1003 may be thinned using, e.g., a chemical mechanical polishing process, a grinding process, or the like. Further, once exposed, the third TDVs 1007 may be recessed using, e.g., one or more etching processes, such as a wet etch process in order to recess the semiconductor substrate 1003 so that the third TDVs 1007 extend out of the semiconductor substrate 1003.
In an embodiment the second external connectors 1009 may be placed on the semiconductor substrate 1003 in electrical connection with the third TDVs 1007 and may be, e.g., a ball grid array (BGA) which comprises a eutectic material such as solder, although any suitable materials may be used. Optionally, an underbump metallization or additional metallization layers (not separately illustrated in
Once the interposer substrate 1001 has been formed, the first optical package 900 may be attached to the interposer substrate 1001. In an embodiment the first optical package 900 may be attached to the interposer substrate 1001 by aligning the first external connectors 913 with conductive portions of the interposer substrate 1001. Once aligned and in physical contact, the first external connectors 913 are reflowed by raising the temperature of the first external connectors 913 past a eutectic point of the first external connectors 913, thereby shifting the material of the first external connectors 913 to a liquid phase. Once reflowed, the temperature is reduced in order to shift the material of the first external connectors 913 back to a solid phase, thereby bonding the first optical package 900 to the interposer substrate 1001.
Of course, while the second semiconductor device 1011 is a HBM module in one embodiment, the embodiments are not restricted to the second semiconductor device 1011 being an HBM module. Rather, the second semiconductor device 1011 may be any suitable semiconductor device, such as a processor die or other type of functional die. In particular embodiments the second semiconductor device 1011 may be an xPU, a logic die, a 3DIC die, a CPU, a GPU, a SoC die, a MEMS die, combinations of these, or the like. Any suitable device with any suitable functionality, may be used, and all such devices are fully intended to be included within the scope of the embodiments.
The third semiconductor device 1013 may be another EIC that is intended to work with both the first optical package 900 and the second semiconductor device 1011. In some embodiments the third semiconductor device 1013 may have a different functionality from the second semiconductor device 1011, such as by being an xPU, a GPU, an ASIC device, or may have a same functionality as the second semiconductor device 1011, such as by being another high bandwidth memory device.
In an embodiment both the second semiconductor device 1011 and the third semiconductor device 1013 may be bonded to the interposer substrate 1001 using, e.g., third external connections 1015. The third external connections 1015 may be conductive bumps (e.g., ball grid arrays, microbumps, etc.) or conductive pillars utilizing materials such as solder and copper. In an embodiment in which the third external connections 1015 are contact bumps, the third external connections 1015 may comprise a material such as tin, or other suitable materials, such as silver, lead-free tin, or copper. In an embodiment in which the third external connections 1015 are tin solder bumps, the third external connections 1015 may be formed by initially forming a layer of tin through such commonly used methods such as evaporation, electroplating, printing, solder transfer, ball placement, etc. Once a layer of tin has been formed on the structure, a reflow may be performed in order to shape the material into the desired bump shape.
Additionally, once the third external connections 1015 have been placed, the second semiconductor device 1011 and the third semiconductor device 1013 are aligned with the interposer substrate 1001. Once aligned and in physical contact, the third external connections 1015 are reflowed by raising the temperature of the third external connections 1015 past a eutectic point of the third external connections 1015, thereby shifting the material of the third external connections 1015 to a liquid phase. Once reflowed, the temperature is reduced in order to shift the material of the third external connections 1015 back to a solid phase, thereby bonding the second semiconductor device 1011 and the third semiconductor device 1013 to the interposer substrate 1001.
Optionally, an underfill material (not separately illustrated) may be placed. The underfill material may reduce stress and protect the joints resulting from the reflowing of the third external connections 1015 and the first external connectors 913. The underfill material may be formed by a capillary flow process after the first optical package 900, the second semiconductor device 1011 and the third semiconductor device 1013 are attached.
Once the second semiconductor device 1011, the third semiconductor device 1013 and the first optical package 900 have been bonded to the interposer substrate 1001, the interposer substrate 1001 may be bonded to a second substrate 1021 with, e.g., the second external connectors 1009. In an embodiment the second substrate 1021 may be a package substrate, which may be a printed circuit board (PCB) or the like. The second substrate 1021 may include one or more dielectric layers and electrically conductive features, such as conductive lines and vias. In some embodiments, the second substrate 1021 may include through-vias, active devices, passive devices, and the like. The second substrate 1021 may further include conductive pads formed at the upper and lower surfaces of the second substrate 1021.
The second external connectors 1009 may be aligned with corresponding conductive connections on the second substrate 1021. Once aligned the second external connectors 1009 may then be reflowed in order to bond the second substrate 1021 to the interposer substrate 1001. However, any suitable bonding process may be used to connect the interposer substrate 1001 to the second substrate 1021.
Additionally, the second substrate 1021 may be prepared for further connections by placing fourth external connections (not separately illustrated) on an opposite side of the second substrate 1021 from the first optical package 900. In an embodiment the fourth external connections may be formed using similar processes and materials as the second external connectors 1009. However, any suitable materials and processes may be utilized.
The first lens 1103 is formed within the first tier substrate 1101. In an embodiment the first lens 1103 may be formed by shaping the material of the support substrate (e.g., silicon) using masking and etching processes. However, any suitable process may be utilized.
Additionally, if desired, a first anti-reflective coating (ARC) 1113 may be formed on the first lens 1103. In an embodiment the first ARC 1113 may be one or more layers of materials which help to prevent undesired reflections as light is focused through the first lens 1103. In a particular embodiment the one or more layers of materials may be materials such as silicon oxide, silicon nitride, combinations of these, or the like, formed using processes such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, oxidation, nitridation, combinations of these, or the like.
In a particular embodiment the first ARC 1113 may be formed using a first layer of silicon oxide and a first layer of silicon nitride formed over the first layer of silicon oxide. A second layer of silicon oxide and a second layer of silicon nitride are deposited over the first layer of silicon oxide and the first layer of silicon nitride, forming an alternating stack of silicon oxide and silicon nitride. Once all of the desired layers have been deposited, the layers may be patterned using, e.g., a photolithographic masking and etching process. However, any suitable combinations of materials and processes may be utilized.
Additionally, if the recess formed by the first lens 1103 is not otherwise filled, a fill material may be deposited in order to fill the recess formed by the first lens 1103. In an embodiment the fill material may be a cladding material such as silicon oxide deposited using a method such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, combinations of these, or the like. Once the recess has been filled, the fill material may be planarized using a process such as chemical mechanical polishing in order to remove portions of the fill material outside of the recess.
Once the first lens 1103 has been formed, a first tier active layer 1105 with sixth optical components 1107 is formed over the first tier substrate 1101. In an embodiment the first tier active layer 1105 with sixth optical components 1107 may be formed using similar materials and similar processes as the second active layer 801 of the fourth optical components 803 described above with respect to
In a particular embodiment the sixth optical components 1107 comprise at least one integrated multiple coupler (IMC) (e.g., an edge coupler), such as a multiple waveguide edge coupler that is situated to receive optical signals (described further below with respect to
Once the first tier active layer 1105 with sixth optical components 1107 has been formed, the first mirror 1109 may be formed to extend into the first tier active layer 1105 and have a first orientation. In an embodiment the first mirror 1109 may be formed by initially patterning the first tier active layer 1105 to form a recess. In an embodiment the recess may be formed using one or more photolithographic masking and etching processes, such as one or more wet etching processes or dry etching processes. However, any suitable process may be utilized.
Once the recess has been formed, the first mirror 1109 may be formed along sidewalls of the recess. In an embodiment the first mirror 1109 may be a single layer of a reflective material such as aluminum copper, copper, gold, aluminum, titanium nitride, combinations of these, or the like, or else may be a multi-layer structure such as a Braggs reflector comprising alternating layers of different materials, such as alternating layers of silicon dioxide and amorphous silicon. The individual materials of the first mirror 1109 may be deposited using any suitable methods, such as chemical vapor deposition, physical vapor deposition, plating, combinations of these, or the like, and the individual layers may be then be further patterned using, e.g., a photolithographic masking and etching process (for example, to remove horizontal portions of the deposited materials). However, any suitable materials and methods may be utilized in order to form the first mirror 1109 along the sidewalls of the recess.
Additionally, if the formation of the first mirror 1109 does not fully fill the recess, the recess may be filled and planarized. In an embodiment the recess may be filled and/or overfilled with a material similar to the cladding material of the first tier active layer 1105 deposited using a method such as chemical vapor deposition, followed by a planarization process such as a chemical mechanical polishing process. However, any suitable material and any suitable process may be utilized.
Once the first mirror 1109 has been formed, the first tier active layer 1105 may be bonded to a first carrier substrate 1111. In an embodiment the first carrier substrate 1111 may comprise a material such as glass, silicon, silicon germanium, combinations of these, or the like, and the first carrier substrate 1111 may be bonded to the first tier active layer 1105 using, for example, a dielectric-to-dielectric bonding process. However, any suitable materials and any suitable bonding process may be utilized.
A second tier active layer 1203 with seventh optical components 1205 may be formed over the second lens 1201. In an embodiment the second tier active layer 1203 and the seventh optical components 1205 may be formed using similar materials and methods as the first tier active layer 1105 with sixth optical components 1107 described above with respect to
Additionally, if desired, at this point in the manufacturing process the second tier active layer 1203, after being bonded, may be thinned. In a particular embodiment the second tier active layer 1203 may be thinned using a planarization process, such as a chemical mechanical polishing process. However, any suitable planarization process, such as a grinding process or one or more etching processes, may be utilized.
The third lens 1603 and the fourth lens 1605 may be formed on opposite sides of the third tier substrate 1601. In an embodiment the third lens 1603 and the fourth lens 1605 may be formed using methods as the first lens 1103, such as using one or more photolithographic masking and etching process to shape the surfaces of the third tier substrate 1601 and, if desired, a third ARC 1613 and a fourth ARC 1615 may be formed using similar processes and materials as the first ARC 1113. However, any suitable methods may be utilized.
After the third lens 1603 and the fourth lens 1605 have been formed, a third tier active layer 1607 with eighth optical components 1609 may be formed. In an embodiment the third tier active layer 1607 with eighth optical components 1609 may be formed using similar processes and similar materials as the first tier active layer 1105 with sixth optical components 1107 (described above with respect to
Once the third mirror 1611 has been formed, the first tier active layer 1105 may be bonded to the third tier substrate 1601 to form a multi-tier connection unit 1600. In an embodiment the first tier active layer 1105 may be bonded to the third tier substrate 1601 using, e.g., a dielectric-to-dielectric bonding process. However, any suitable bonding process may be utilized.
Additionally, the multi-tier connection unit 1600 may be attached to the second substrate 1021 in order to provide secondary support and help avoid warpage of the second substrate 1021. In an embodiment the multi-tier connection unit 1600 may be attached to the second substrate 1021 using first spacers 1703, which may be a rubber material, a soft and supportive polymer material, combinations of these, or the like. However, any suitable material may be utilized.
In a particular embodiment the core material may have a thickness of about 10 μm. Additionally, the cladding material may have a thickness along one side of the core material of about 125 μm. However, any suitable dimensions may be utilized.
In an embodiment, the ferrule 1805 may be used to receive the plurality of optical fibers 1803 (from off of the figure), align the optical fibers 1803, and connect the optical fibers 1803 to the multi-row connector 1801. In an embodiment, the ferrule 1805 may be a mechanical transfer (MT) ferrule and the like made of a material that can be used to protect, support and align the individual optical fibers 1803. However, any suitable materials may be utilized. In an embodiment, the optical fibers 1803 may be inserted into openings located within the ferrule 1805. Once inserted a glue material, such as an epoxy, silicone, a photocurable elastic polymer, combinations of these, or the like, may be injected or otherwise placed into the openings within the ferrule 1805 in order to secure the optical fibers 1803 within the ferrule 1805. Additionally, a curing process such as a light cure, a heat cure, or the like, may be utilized to harden the glue material. In this embodiment, the ferrule 1805 helps secure the optical fibers 1803 such that the optical signals provided by the optical fibers 1803 may be transmitted to the multi-tier connection unit 1600.
The multi-row connector 1801 receives the optical fibers 1803 from the ferrule 1805 and separates them into more than one row. In the particular embodiment illustrated in
In an embodiment each of the individual rows of optical fibers 1803, once the multi-row connector 1801 is attached to the multi-tier connection unit 1600, are aligned with a corresponding tier within the multi-row connector 1801. In the particular embodiment in which two rows are utilized, the first row 1811 is aligned so that optical signals from the first row enter the eighth optical components 1609 of the third tier active layer 1607. Additionally, the second row 1813 is aligned so that optical signals from the second row enter the sixth optical components 1107 of the first tier active layer 1105. In a particular embodiment the first row 1811 may be separated from the second row 1813 by a first pitch P1 of between about 250 μm and about 500 μm. However, any suitable distance may be utilized.
Once the multi-row connector 1801 is ready, the multi-row connector 1801 is connected to the multi-tier connection unit 1600 and the second substrate 1021. In an embodiment the multi-row connector 1801 may be attached to the multi-tier connection unit 1600 using, e.g., a second optical glue 1807 and a sidewall anti-reflective coating 1806. In some embodiments, the second optical glue 1807 and the sidewall anti-reflective coating 1806 may be formed using similar materials and methods as the optical glue 1701 and the first ARC 1113, described above with respect to
Additionally, the multi-row connector 1801 may be attached to the second substrate 1021 in order to provide secondary support and help avoid warpage of the second substrate 1021. In an embodiment the multi-row connector 1801 may be attached to the second substrate 1021 using second spacers 1809, which may be a rubber material, a soft and supportive polymer material, combinations of these, or the like. However, any suitable material may be utilized.
Additionally, the optical signals from the first row 1811 enters the eighth optical components 1609 in the third tier active layer 1607, are reflected by the third mirror 1611, pass between separate elements of the first mirror 1109, and are reflected by the second mirror 1207 before entering the seventh optical components 1205 of the second tier active layer 1203. From the seventh optical components 1205, the optical signals can be routed into the first optical package 900 through, e.g., edge couplers located within the seventh optical components 1205 and the second active layer 801 of the fourth optical components 803.
By utilizing the multi-row connector 1801, more optical fibers 1803 can be connected to the first optical package 900. In particular the third tier active layer 1607 may be used to ensure compatibility with the multi-row connector 1801, the first tier active layer 1105 is used to provide height to align with the various rows of the multi-row connector 1801 without the need for cutting substrates, and the second tier active layer 1203 is utilized to help ensure that the seventh optical components 1205 are precisely aligned with the couplers of the first optical package 900.
Additionally, by increasing the number of optical fibers 1803, this allows for a higher bandwidth both into and out of the first optical package 900. As such, coupling losses from the optical fibers 1803 to the first optical package 900 can be decreased and a more efficient device can be formed.
Additionally, the sixth optical components 1107 may also be removed and not manufactured during the formation of the first optical package 900, although the dielectric and/or cladding material may still be manufactured in order to assist in bonding. As such, the first mirror 1109 may be formed within the first tier substrate 1101 using, e.g., similar processes as described above with respect to
Additionally in this embodiment the first mirror 1109 may not be located directly below the third mirror 1611, and the location of the first mirror 1109 may be offset from the location of the third mirror 1611. As such, the third lens 1603 and the first lens 1103 may further be offset from the location of the first mirror 1109 so as to be available for the transmission of optical signals from the third mirror 1611.
Looking at the second tier active layer 1203, in this embodiment the second lens 1201 and the second mirror 1207 may remain as discussed above in order to be able to reflect optical signals received from the first mirror 1109. In this embodiment, however, the second tier active layer 1203 may additionally include a fifth lens 2001 and a fourth mirror 2003. In an embodiment the fifth lens 2001 and the fourth mirror 2003 are used to receive reflected optical signals from the third mirror 1611 and reflect the optical signals into the seventh optical components 1205 of the second tier active layer 1203, and the fifth lens 2001 and the fourth mirror 2003 may be formed using similar methods and materials as the first lens 1103 and the first mirror 1109, described above with respect to
Returning to
Additionally, the optical signals from the first row 1811 enters the third tier substrate 1601 and is reflected by the third mirror 1611. From the reflection from the third mirror 1611, the optical signal is reflected by the fourth mirror 2003 into the seventh optical components 1205 of the second tier active layer 1203. From the seventh optical components 1205, the optical signals are then routed into the first optical package 900.
Additionally in this embodiment, while the multi-tier connection unit 1600 may be optically connected to the first optical package 900 as described above (e.g. directly from the multi-tier connection unit 1600 to the first optical package 900), in other embodiments the multi-tier connection unit 1600 may be indirectly connected to the first optical package 900 through, e.g., the interposer optical components 2201 (described above with respect
After the first tier substrate 1101 has been thinned, a first bonding layer 2401 is deposited on the first tier substrate 1101. In an embodiment the first bonding layer 2401 may be a bonding material such as silicon oxide, silicon nitride, combinations of these, or the like, deposited using a method such as chemical mechanical polishing processes. However, any suitable method and material may be utilized.
Once the gap fill material 613 has been deposited, a second bonding layer 2501 is deposited over the first semiconductor device 601 and the first gap-fill material 613. In an embodiment the second bonding layer 2501 may be similar to the first bonding layer 2401, such as by being silicon oxide deposited by chemical vapor deposition. However, any suitable methods and materials may be utilized.
Once the first bonding layer 2401 and the second bonding layer 2501 have been formed, the first bonding layer 2401 is bonded to the second bonding layer 2501. In an embodiment the first bonding layer 2401 and the second bonding layer 2501 may be bonded using a dielectric-to-dielectric bonding process. However, any suitable bonding process may be utilized.
Once the first substrate 101 has been removed, the second active layer 801 of the fourth optical components 803 are manufactured along a backside of the first active layer 107. In an embodiment, the second active layer 801 of the fourth optical components 803 may be manufactured as described above with respect to
In this embodiment, however, in addition to forming the fourth optical components 803 within the second active layer 801, a fifth mirror 2701 is additionally formed within the second active layer 801. In an embodiment the fifth mirror 2701 may be formed in a similar manner and using similar materials as the first mirror 1109 described above with respect to
In this embodiment the multi-row connector 1801 may be used to space the first row 1811 from the second row 1813 in order to align first row 1811 and the second row 1813 with the desired portions of the second optical package 2700. In a particular embodiment the first row 1811 and the second row 1813 may have a second pitch P2 of between about 127 μm and about 250 μm. However, any suitable pitch may be utilized.
In operation, optical signals from the second row 1813 are directed directly into the second active layer 801 with the fourth optical components 803. However, the optical signals from the overlying first row 1811 are directed into the sixth optical components 1107 of the first tier active layer 1105, reflected off of the first mirror 1109 through the first gap-fill material 613 and to the fifth mirror 2701. The fifth mirror 2701 receives the optical signals and reflects them into the fourth optical components 803 of the second active layer 801.
By utilizing the first tier active layer 1105 over the second active layer 801, more optical fibers 1803 can be connected. By increasing the number of optical fibers 1803, this allows for a higher bandwidth both into and out of the second active layer 801. As such, coupling losses from the optical fibers 1803 to the second active layer 801 can be decreased and a more efficient device can be formed.
In an embodiment, a method of manufacturing an optical device includes: receiving a multi-tier connection unit, the multi-tier connection unit including: a first tier comprising a first mirror with a first orientation; a second tier comprising a second mirror with a second orientation the same as the first orientation; and a third tier comprising a third mirror, the third mirror having a third orientation different from the first orientation; and attaching the multi-tier connection unit to a first optical package. In an embodiment the third tier further comprises fan-in waveguides. In an embodiment the second mirror comprises multiple, separated portions. In an embodiment the first mirror is a single unit. In an embodiment the multi-tier connection unit has a constant width. In an embodiment the first mirror is located with a semiconductor substrate. In an embodiment the first tier further comprises waveguides aligned with the first mirror.
In another embodiment, a method of manufacturing an optical device includes: attaching an electrical integrated circuit to an optical interposer; and bonding a first tier active layer over the electrical integrated circuit and the optical interposer, the first tier active layer including: first optical components; and a first mirror aligned with the first optical components. In an embodiment after the bonding the first mirror is aligned with a second mirror located on an opposite side of the electrical integrated circuit from the first mirror, the second mirror being located in a first active layer of second optical components. In an embodiment the method further includes attaching a multi-tier connection unit to the optical interposer. In an embodiment the multi-tier connection unit includes: a first optical fiber aligned with the first mirror; and a second optical fiber aligned with the second optical components. In an embodiment a first center of the first optical fiber is located directly over a second center of the second optical fiber. In an embodiment the first optical fiber is in a staggered configuration with the second optical fiber. In an embodiment a pitch between the first optical fiber and the second optical fiber is about 108 μm.
In yet another embodiment an optical device includes: a multi-tier connection unit, the multi-tier connection unit including: a first tier comprising a first mirror; a second tier comprising a second mirror, a first lens, and a second lens; and a third tier comprising a third mirror and a third lens; and a first optical package attached to the multi-tier connection. In an embodiment the first lens and the second lens are adjacent to the second mirror. In an embodiment the first lens and the second lens are offset from the second mirror. In an embodiment the third tier comprises a fourth mirror aligned with the first lens and the second lens. In an embodiment the optical device further includes a multiple row connector attached to the multi-tier connection unit, wherein a first row of optical fibers is aligned with the first mirror and wherein a second row of optical fibers is aligned with the second mirror. In an embodiment the first tier further comprises first optical components adjacent to the first mirror.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
This application claims the benefit of U.S. Provisional Application No. 63/535,402, filed on Aug. 30, 2023, entitled “Fan-In Si FAU Assembly for Multi-Row Fibers, and Edge Coupling with High Beachfront Density,” and U.S. Provisional Application No. 63/608,012, filed on Dec. 8, 2023, entitled “Optical Device and Method of Manufacture,” which applications are hereby incorporated herein by reference.
Number | Date | Country | |
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63608012 | Dec 2023 | US | |
63535402 | Aug 2023 | US |