Patent Application
20230097053
The present disclosure generally relates to optical demultiplexers.
In optical communication systems, multiplexing techniques (such as polarization-division multiplexing (PDM)) can increase communication capacity and/or photon efficiency by multiplexing different signals over different channels (e.g., different polarization modes on the same carrier frequency) for simultaneous transmission through a single fiber. However, a challenge of using PDM is that the polarization modes tend to undergo random and unpredictable rotations and losses as they propagate through an optical communication system, for example due to stress in the glass fiber (bending and twisting), ambient temperature changes, or other non-idealities in the communication system. This results in the different signals in the polarization modes becoming mixed among each other when they are received. In such scenarios, the signals must be unmixed at the receiver through multiple-input-multiple-output (MIMO) demultiplexing.
Implementations of the present disclosure are generally directed to optical demultiplexers, such as optical polarization demultiplexers.
One general aspect includes a 2×2 optical multi-input-multi-output (MIMO) demultiplexer, including: a pair of MIMO inputs configured to input light into a first pair of optical transmission paths; a first optical phase shifter configured to apply a first relative phase shift between the first pair of optical transmission paths; a first 2×2 optical coupler configured to combine the first pair of optical transmission paths and output a second pair of optical transmission paths; a second optical phase shifter configured to apply a second relative phase shift between the second pair of optical transmission paths; a second 2×2 optical coupler configured to combine the second pair of optical transmission paths and output a third pair of optical transmission paths; a third optical phase shifter configured to apply a third relative phase shift between the third pair of optical transmission paths; a third 2×2 optical coupler configured to combine the third pair of optical transmission paths and output a fourth pair of optical transmission paths; and a pair of MIMO outputs configured to output the fourth pair of optical transmission paths. Other embodiments of this aspect include corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the methods.
Implementations may include one or more of the following features. The 2×2 optical MIMO demultiplexer where the first optical phase shifter is configured to apply a value of the first relative phase shift that is binary. The 2×2 optical MIMO demultiplexer where the value of the first relative phase shift is binary among c+π/2 and c×π/2, where c is a real number. The 2×2 optical MIMO demultiplexer where the second optical phase shifter is configured to apply a value of the second relative phase shift within a finite range that includes −nπ and +nπ, where n is an integer. The 2×2 optical MIMO demultiplexer where the second optical phase shifter is configured for analog operation within a range (−nπ, +nπ). The 2×2 optical MIMO demultiplexer where the third optical phase shifter is configured to apply a value of the third relative phase shift within a finite range that depends on the value of the first relative phase shift. The 2×2 optical MIMO demultiplexer where the third optical phase shifter is configured to operate between 0 and +nπ, based on the value of the first relative phase shift being c−π/2, and is configured to operate between −nπ and 0, based on the value of the first relative phase shift being c+π/2, where n is an integer. The 2×2 optical MIMO demultiplexer where the third optical phase shifter is configured for analog operation within a range (0, +nπ) or within a range (−nπ, 0). The 2×2 optical MIMO demultiplexer further including: at least one processor and at least one memory storing instructions that, based on being executed by the at least one processor, perform operations to control the values of the first relative phase shift, the second relative phase shift, and the third relative phase shift. The 2×2 optical MIMO demultiplexer further including a first optical attenuator configured to apply a first relative attenuation between the first pair of optical transmission paths. The 2×2 optical MIMO demultiplexer further including a second optical attenuator configured to apply a second relative attenuation between the third pair of optical transmission paths. The 2×2 optical MIMO demultiplexer where each of the first optical phase shifter, the second optical phase shifter, and the third optical phase shifter have a phase shifting range that is less than or equal to 2n. Implementations of the described techniques may include hardware, a method or process, or computer software on a computer-accessible medium.
Another general aspect includes an optical multi-input-multi-output (MIMO) receiver, including: an input port configured to receive input light; means for performing adaptive 2×2 optical MIMO polarization demultiplexing on the input light using 3-stage optical phase-shifting to output a first optical signal and a second optical signal; and at least one photodetector configured to detect the first optical signal and the second optical signal. Other embodiments of this aspect include corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the methods.
Implementations may include one or more of the following features. The optical MIMO receiver where each stage of the 3-stage optical phase-shifting has a range less than or equal to 2n. Implementations of the described techniques may include hardware, a method or process, or computer software on a computer-accessible medium.
Another general aspect includes a method of performing 2×2 optical multi-input-multi-output (MIMO) demultiplexing, the method including: receiving light through a pair of MIMO inputs into a first pair of optical transmission paths; controlling a first optical phase shifter to apply a first relative phase shift between the first pair of optical transmission paths; combining the first pair of optical transmission paths with a first 2×2 optical coupler to output a second pair of optical transmission paths; controlling a second optical phase shifter to apply a second relative phase shift between the second pair of optical transmission paths; combining the second pair of optical transmission paths with a second 2×2 optical coupler to output a third pair of optical transmission paths; controlling a third optical phase shifter to apply a third relative phase shift between the third pair of optical transmission paths; combining the third pair of optical transmission paths with a third 2×2 optical coupler to output a fourth pair of optical transmission paths; and outputting the fourth pair of optical transmission paths through a pair of MIMO outputs. Other embodiments of this aspect include corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the methods.
Implementations may include one or more of the following features. The method where controlling the first optical phase shifter includes applying a value of the first relative phase shift that is binary. The method where the value of the first phase shift is binary among c+π/2 and c−π/2, where c is a real number. The method where controlling the second optical phase shifter includes applying a value of the second relative phase shift within a finite range that includes −nπ and +nπ, where n is an integer. The method where controlling the second optical phase shifter is performed by analog operation within a range (−nπ, +nπ). The method where controlling the third optical phase shifter includes applying a value of the third relative phase shift within a finite range that depends on the value of the first relative phase shift. The method where controlling the third optical phase shifter further includes: controlling the third optical phase shifter to operate between 0 and +nπ, based on the value of the first relative phase shift being c−π/2, and to operate between −nπ and 0, based on the value of the first relative phase shift being c+π/2, where n is an integer. The method where controlling the third optical phase shifter is performed by analog operation within a range (0, +nπ) or within a range (−nπ, 0), depending on the value of the first relative phase shift. The method, further including detecting a first reference signal on a first polarization channel in a first MIMO output of the pair of MIMO outputs, detecting a second reference signal on a second polarization channel in a second MIMO output of the pair of MIMO outputs, determining an amount of error measured from the first reference signal and the second reference signal; and controlling at least one of the first optical phase shifter, the second optical phase shifter, or the third optical phase shifter based on the amount of error measured from the first reference signal and the second reference signal. The method where the 2×2 optical MIMO demultiplexing is performed in an endless manner without resetting any of the first optical phase shifter, the second optical phase shifter, or the third optical phase shifter during operation. Implementations of the described techniques may include hardware, a method or process, or computer software on a computer-accessible medium.
Another general aspect includes an optical multi-input-multi-output (MIMO) receiver configured to perform optical MIMO polarization demultiplexing. The optical MIMO receiver includes an input port configured to receive input light; a polarization beam splitter and rotator (PBSR) configured to split the input light into a pair of optical transmission paths; an optical phase shifter configured to apply a relative phase shift between the pair of optical transmission paths; a 2×2 optical coupler configured to combine the pair of optical transmission paths; and a controller configured to control the optical phase shifter using a binary control with two states of operation for the relative phase shift that is applied between the pair of optical transmission paths. Other embodiments of this aspect include corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the methods.
Another general aspect includes an optical multi-input-multi-output (MIMO) receiver configured to perform optical MIMO polarization demultiplexing. The optical MIMO receiver includes an input port configured to receive input light; a polarization beam splitter and rotator (PBSR) configured to split the input light into a pair of optical transmission paths; an optical attenuator configured to apply a relative attenuation between the pair of optical transmission paths; a 2×2 optical coupler configured to combine the pair of optical transmission paths; and a controller configured to control the relative attenuation that is applied by the optical attenuator. Other embodiments of this aspect include corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the methods.
Implementations may include one or more of the following features. The optical MIMO receiver where the optical attenuator is a differential optical attenuator that is configured to apply (i) a first attenuation to one of the pair of optical transmission paths, and (ii) a second attenuation to another of the pair of optical transmission paths, where the first attenuation and the second attenuation are equal in magnitude in decibels and opposite in sign. The optical MIMO receiver, further including a second optical attenuator configured to apply a second relative attenuation between a second pair of optical transmission paths, where the second pair of optical transmission paths includes light that has been attenuated by the optical attenuator, and where the controller is further configured to control the second relative attenuation that is applied by the second optical attenuator. Implementations of the described techniques may include hardware, a method or process, or computer software on a computer-accessible medium.
In some implementations, the techniques described herein for optical MIMO polarization demultiplexing can be applied to general 2×2 optical MIMO demultiplexing. For example, in some implementations, the techniques described herein can be implemented separately from or without the PBSR.
The details of one or more implementations of the subject matter of this disclosure are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims.
Systems and techniques are disclosed herein that provide novel multi-stage optical MIMO demultiplexers (e.g., optical MIMO polarization demultiplexers) which can achieve significantly improved efficiency and speed with lower rates of data loss. This is accomplished by novel implementations which enable an “endless” property of adaptive demultiplexing without requiring any resets of interruptions of data reception. In some implementations, this is achieved by an adaptive three-stage phase-shifting demultiplexer structure in which the first stage phase-shifter is controlled to apply a binary value, and the second and third stages of phase-shifting are controlled to operate over finite ranges (e.g., continuous ranges) of phase shifting values. The control of the three stages of phase-shifting are coordinated to adapt to random and unpredictable rotations and losses in received polarization, without requiring any resets of the phase-shifting that would interrupt signal reception, a property referred to as an “endless” operation of the demultiplexer.
In general, multi-polarization detection is challenging, because polarization states tend to drift as an optical waveform travels through a communication system (e.g., due to randomly changing birefringence in fiber transmission lines). Over a long-distance system, these random drifts of polarization can accumulate progressively without limit. In an optical communication system which uses polarization division multiplexing (PDM) to transmit different signals over the two polarization modes of light, the random and unknown polarization drifting creates challenges for a receiver to accurately detect the proper orientation of the two polarization modes, resulting in the different signals becoming mixed at the receiver (sometimes referred to as “cross-talk”). Hence, even though a signal is transmitted in one polarization mode, the signal may actually be received in both polarization modes at the receiver. In addition to polarization drift, other non-idealities in an optical communication system may degrade performance, such as polarization dependent loss (PDL), which amplifies or attenuates different polarization modes differently.
To compensate for polarization drift and other non-idealities, a multi-polarization receiver must do constant, adaptive MIMO demultiplexing to separate and unmix the signals that are transmitted in the two polarization modes. Such MIMO multiplexing may be performed either in the optical domain using optical phase shifters or in the electronic domain by digital signal processing (DSP). Optical MIMO demultiplexing provides various advantages over DSP-based MIMO demultiplexing. For example, optical demultiplexing can reduce power consumption, complexity, and sensitivity to the symbol rate. By contrast, DSP-based demultiplexing typically requires higher power consumption, and can become prohibitively complex for high symbol-rate or large mode-number systems.
Furthermore, optical polarization demultiplexing can be used in conjunction with intensity modulation and direct detection (IMDD) transmission formats (in which information is transmitted only in the magnitude squared of the optical electric field), such as pulse amplitude modulation (PAM). This is because optical demultiplexing can be performed using optical elements that separate the two polarization modes of light, before photodetection is performed on the light. By contrast, DSP-based polarization demultiplexing cannot be used in conjunction with IMDD because the nonlinearity of optical direct detection in IMDD results in a loss of information, which cannot be recovered by DSP techniques alone. Instead, DSP-based demultiplexing typically requires coherent reception. In such systems, the two polarization modes of light are first separated by coherent detection, and then the full field of each polarization is detected, allowing the DSP to perform processing on the signals received in the two polarization modes. An example of this distinction is described with reference to
This dual-polarized (DP) optical waveform travels through a fiber link (116 and 166). As the DP waveform travels through the fiber, various unknown and varying birefringence and twists in the fiber can cause changes in the polarizations of the two waveforms. If the fiber link (116 and 166) does not have significant polarization-dependent loss (PDL), then the two polarizations remain orthogonal. For example, x (X) may evolve from a linear horizontal polarization to a right-hand circular polarization, which means that y (Y) evolves from a linear vertical polarization to a left-hand circular polarization. However, in the presence of PDL, the orthogonality of the polarizations in the DP optical waveform will degrade, which will complicate the demultiplexing of x (X) and y (Y).
At the receiver (118 and 168), the DP waveform enters a PBSR (120 and 162) which splits the DP waveform into two waveforms, h and v, which have orthogonal polarizations. Due to the non-idealities in the optical communication system, the outputs of the PBSR, h and v, are each a linear and orthogonal combination of x and y (more precisely, the received signals will be noisy versions of x and y due to additive noise in the system, but we will assume a noiseless scenario for the purposes of this discussion). In particular, h is a linear combination of x and y, and similarly v is a linear combination of x and y. For example, h=(x−y)/sqrt(2) and v=(x+y)/sqrt(2). The purpose of MIMO demultiplexing is to extract the original signals x and y from the received h and v. This can be done via DSP-based demultiplexing (as in
In the coherent case of
By contrast, in the example of IMDD reception in
For two orthogonal states of polarization, a PDM optical communication system can be represented as a 2×2 Multi-Input-Multi-Output (MIMO) channel. Thus, the optical transmission can be modeled as a 2×2 matrix, F. The matrix F is a transfer function describing polarization effects and chromatic dispersion of the communication from transmitter to receiver. For example, the matrix F can model the effects of the fiber that connects a transmitter and receiver, as well as the effects of the optical components in the transmitter and receiver themselves. For purposes of this disclosure, the matrix F will be referred to as a “channel matrix F” with the understanding that the “channel” can represent various effects of the optical communication system, such as the fiber transmission line and components of the transmitter and/or receiver.
To estimate the original signals x and y from the received signals h and v, an optical demultiplexer D is applied at the receiver, to generate estimates x′ and y′:
Then, as long as x′=ax and y′=bx (where “a” and “b” are complex constants), then the receiver will have successfully demultiplexed the polarizations.
Consider the simpler case of a lossless system (where the optical channel matrix F is unitary), which is approximately the case in most short fiber-optic links. In such scenarios, fiber loss is negligible, especially fiber polarization-dependent loss (PDL). The channel matrix F can then be characterized by four real numbers. Since the receiver only needs to achieve x′=ax and y′=bx for successful demultiplexing, the demultiplexing matrix D can be characterized by two real numbers. Thus, for a lossless scenario, the four real numbers of the channel matrix F can be expressed as only two, independently-controlled real parameters which should be compensated by the demultiplexing matrix D.
Thus, for a unitary system (lossless scenario), the optical demultiplexer (i.e., the matrix D above) requires a theoretical minimum of at least two phase control signals to reverse the effects of the channel matrix F and demultiplex. An example of a 2-stage demultiplexer is describe with reference to
With this structure, the demultiplexer 200 can be represented as a matrix D (using the Mueller notation for polarization).
However, as mentioned above, a major issue with the configuration of demultiplexer 200 in
To address this problem, a demultiplexer can implement more than two stages of phase shifters. However, a greater number of phase shifting stages (for the lossless scenario using a unitary demultiplexer) increases the algorithmic and control complexity and reduces the speed of controlling the numerous phase shifting variables. Furthermore, it can be difficult to guarantee that the phase-shifting control does not get “trapped” in a particular state during its operation (and being unable to exit the trapped state without a phase shifter exceeding its limits), for an arbitrary input. In addition, higher-complexity control systems may face increased risk of converging to a local state which is not a desirable (e.g., suboptimal) multiplexing operation. Because of this complexity and uncertainty, designing dual-polarized IMDD systems can be challenging.
Furthermore, if polarization dependent loss (PDL) is present, then this can compound the challenges. PDL refers to two orthogonal polarizations being attenuated differently, resulting in a non-unitary channel matrix F. Although PDL is sometimes negligible in fibers, PDL can be significant in discrete devices such as amplifiers and wavelength division multiplexers. Designing non-unitary optical demultiplexers is challenging. In general, a non-unitary demultiplexer can be characterized by four real numbers, with the theoretical minimum control set consisting of two optical phase shifters and two optical attenuators.
Implementations are disclosed herein that achieve an “endless” property of optical MIMO polarization demultiplexing using just three stages of finite-range phase shifting, for the lossless scenario of no PDL, an example of which is described with reference to
The demultiplexer 300 includes three stages (302, 304, and 306) of phase shifting. Each stage is controlled by a phase shift control signal. For example, the first stage 302 is controlled by a first control signal 308, the second stage 304 is controlled by a second control signal 310, and the third stage 306 is controlled by a third control signal 312. Each control signal controls the amount of phase shift that is implemented in the respective phase shifting stage.
In the example of
Although the example of
The phase shifters can be thermo-optic (thermo-optic phase shifter, TOPS), electro-optic (electro-optic phase shifter, EOPS), or other types. The TOPS generally have the slowest response time but can be sped up by covering with metal and/or shortening the distance to the heat sink. The power consumption of the TOPS can be reduced by having the optical transmission path pass through the heated region multiple times. The EOPS can operate on, for example, current injection, carrier depletion, or the Pockels effect. Each phase shifter could consist of multiple sections, such as a section with a phase shifter type that has a fast response time but more power consumption and a section with a phase shifter type that has a slow response time but reduced power consumption.
The 2×2 couplers can be, for example, implemented by directional couplers, multi-mode interference couplers, or adiabatic couplers.
As mentioned above, the three stages (302, 304, 306) of demultiplexer 300 are controlled within specific ranges or values of operations in a coordinated manner, so as to ensure that the demultiplexer 300 can achieve an “endless” property of demultiplexing without requiring a reset of any of the phase shifters. In particular, in the example of
During operation of the demultiplexer 300, light that has traveled through a fiber first enters the splitter, such as PBSR 346, which splits the input light into the two optical transmission paths 314 and 316. The PBSR splits the input light into two polarizations and rotates one of the polarizations so that both outputs of the PBSR are in the same polarization. Thus, although path 314 contains light that was in one polarization when it entered the PBSR and path 316 contains light that was in the orthogonal polarization when it entered the PBSR, once in paths 314 and 316, the light in both paths 314 and 316 are in the same polarization. Although the example of
The split input light enters the two optical transmission paths 314 and 316 of the first stage 302, and undergo relative phase shifts through phase shifting elements 318 and 320, such that light in one optical transmission path is phase-shifted by an amount φ1 relative to light in the other optical transmission path. The amount of this relative phase shift φ1 is controlled by the control signal 308. The phase-shifted light in the two optical transmission paths then enter a 2×2 coupler 322 which combines the relative phase-shifted light. This process repeats through the second stage 304 and the third stage 306, undergoing different phase shifts controlled by control signals φ2 (310) and φ3 (312).
A controller 344 controls the amount of relative phase shift in the three stages 302, 304, and 306 via the control signals 308, 310, and 312. In scenarios of closed-loop feedback, this control can be based on feedback information 348 which can be, for example, a measurement of an error in the received signal. The specific algorithms that are used by the controller 344 for controlling and coordinating the control signals 308, 310, and 312 will be described with reference to
As discussed above, demultiplexer 300 compensates for random birefringence changes which rotate the polarizations of light, caused by distortions introduced by the optical communication system. In addition to compensating for phase shifts, a demultiplexer can also be designed to compensate for other non-idealities, such as polarization dependent loss (PDL). While PDL may be negligible in most short fiber-optic links, as the length of the fiber increases, PDL can have a more substantial impact on proper reception of the optical signals.
In scenarios of polarization dependent loss (PDL), the amount of loss experienced in each of the two polarization modes of light may be different, e.g., the loss in the transverse magnetic (TM) mode may be greater/smaller than the loss in transverse electric (TE) mode. This results in a channel matrix F which is non-unitary. In this case, demultiplexing with phase shift controls alone may be insufficient to fully separate the signals which have been mixed in the two polarization modes of light. Instead, a combination of optical phase shifters and optical attenuators are implemented in the demultiplexer, as described with reference to
Demultiplexer 400 includes three stages (402, 404, and 406) of relative phase shift control and/or optical attenuation control. Each stage is controlled by one or more control signals. For example, the first stage 402 is controlled by a first attenuation control signal 408 and a first phase shift control signal 410. The second stage 404 is controlled by a second phase shift control signal 412. The third stage 406 is controlled by a second attenuation control signal 414 and a third phase shift control signal 416. Each control signal controls the amount of phase shift or optical attenuation that is implemented in the respective stage.
In the example of
Although the example of
Similarly, the relative phase difference between the two optical transmission paths is referred to simply as “φ,” regardless of whether the relative phase shift is implemented by a differential phase shifter (i.e., each phase shifting element in the differential pair designed to shift by +/−φ/2, as shown in the example of
As mentioned above, the three stages of demultiplexer 400 are controlled within specific ranges or values of operations in a coordinated way, so as to ensure that the demultiplexer 400 can achieve an “endless” property of demultiplexing without requiring a reset of any of the phase shifters. For the phase shift control, in the example of
During operation of the demultiplexer 400, light that has traveled through a fiber first enters the splitter, such as PBSR 458, which splits the input light into the two optical transmission paths 418 and 420. Although the example of
The relatively-attenuated light in the two optical transmission paths then undergo relative phase shifts through phase shifting elements 426 and 428 (forming a differential phase shifter), such that the phase of light in one optical transmission path is shifted relative to the phase of light in the other optical transmission path. The amount of this relative phase shift φ1 is controlled by the control signal 410. The phase-shifted light in the two optical transmission paths then enter a 2×2 coupler 430 which combine the relative phase-shifted light. This process continues through the second stage 404 and the third stage 406, so that the two polarizations of light undergo relative phase shifts and/or relative attenuations controlled by phase control signals 412 and 416 and the attenuation control signal 414.
A controller 456 controls the amount of relative attenuation and relative phase shift the different stages 402, 404, and 406 via the control signals 408, 410, 412, 414, and 416. By controlling both the relative attenuation and the relative phase shift between the two polarizations of light, demultiplexer 400 is able to compensate for both random phase shifts as well as PDL (non-unitary channel matrix F). In scenarios of closed-loop feedback, this control can be based on feedback information 460 which can be, for example, a measurement of an error in the received signal. The specific algorithms that are used by the controller 456 for controlling and coordinating the control signals 408, 410, 412, 414, and 416 will be described with reference to
In general, the control (e.g., by controller 344 in
To measure of the amount of crosstalk, in some implementations, the communication system may utilize reference signals (e.g., pilot tones or pilot signals) which are transmitted in addition to the signals carrying information. The reference signals have waveform properties which are known to both the transmitter and receiver, and allow the receiver to estimate and compensate for the random effects of the communication channel.
In the example of
Thus, in transmitters 500 and 520 of
Examples of receiver structures for detecting pilot tones and measuring error in received pilot tones are discussed with reference to
Although
In example of
To estimate the impact of this cross-mixing, the receiver can detect the power of each pilot tone (A and B) in each of the two polarization modes (H and V). For example, in
The controller 610 then calculates an error signal based on these received pilot tone components, to estimate the amount of cross-talk between the two polarization modes that have been induced by non-idealities in the communication system. For example, in some implementations, the error can be calculated as:
However, other measures of error can be used to estimate the amount of cross-talk between the pilot tones (A and B) in the two polarization modes (H and V). In general, the measure of error should increase with increasing values of PHB and/or PVA. The measure of error provides an estimate of how well the controller 606 is adapting the control signals (e.g., 608, 610, and 612) to adjust the relative phase shift and/or relative attenuation between the two polarization modes H and V, to compensate for random polarization drifts and PDL. Thus, the controller 606 can use this error measurement in a feedback control loop to dynamically adjust the control signals (e.g., 608, 610, and 612) to further reduce the error. Details of example feedback algorithms are described with reference to
The pilot tones A and B can be detected from the received waveform at various points in the receiving process, examples of which are described with reference to
In both examples of
Next, examples of using error measurements in feedback control of relative phase shifts and/or relative attenuation are discussed with reference to
In step 802, light is received through a pair of MIMO inputs into a first pair of optical transmission paths (314, 316). In step 804, a first optical phase shifter (e.g., the differential phase shifter formed by 318 and 320) is controlled to apply a first relative phase shift between the first pair of optical transmission paths (314, 316). In some implementations, the first optical phase shifter can be controlled in a binary manner, for example with values (c+π/2) and (c−π/2), where “c” is a real number reflecting an offset. This control can be based on feedback information (e.g., using pilot tones).
In step 806, the first pair of optical transmission paths (314, 316) is combined with a first 2×2 optical coupler (322) to output a second pair of optical transmission paths (324, 326).
In step 808, a second optical phase shifter (e.g., the differential phase shifter formed by 328 and 330) is controlled to apply a second relative phase shift between the second pair of optical transmission paths (324, 326). In some implementations, the second optical phase shifter can be controlled within a finite range of values that includes −nπ and +nπ, where “n” is an integer. For example, this can be by analog operation within a range (−nπ, +nπ). This control can be based on feedback information (e.g., using pilot tones).
In step 810, the second pair of optical transmission paths (324, 326) is combined with a second 2×2 optical coupler (332) to output a third pair of optical transmission paths (334, 336).
In step 812, a third optical phase shifter (e.g., the differential phase shifter formed by 338 and 340) is controlled to apply a third relative phase shift between the third pair of optical transmission paths (334, 336). In some implementations, the third optical phase shifter can be controlled within a finite range that depends on the value of the first relative phase shift. For example, as described above, the third optical phase shifter can be controlled to operate between 0 and +nπ if the first relative phase shift is equal to (c−π/2), and to operate between −nπ and 0 if the first relative phase shift is equal to (c+π/2), where “n” is an integer. This can be done by analog operation within the ranges (0, +nπ) and (−nπ, 0). This control can be based on feedback information (e.g., using pilot tones).
In step 814, the third pair of optical transmission paths (334, 336) is combined with a third 2×2 optical coupler (342) to output a fourth pair of optical transmission paths (350, 352). In step 816, the fourth pair of optical transmission paths (350, 352) is then output through a pair of MIMO outputs.
Although the example method 800 in
The method 900 is an iterative process that adapts the relative phase shift control signals 308, 310, and 312 to gradually reduce the measured feedback error (e.g., feedback 348 in
In step 902, at the beginning of the iterations, the demultiplexer initializes the relative phase shift values of the three control signals 308, 310, and 312. For example, in some implementations, the first control signal φ1 (308) is a binary (digital) value, initially set to either −π/2 or +π/2. The second control signal φ2 (310) is a continuous (analog) or discrete (digital) value, initially set to a value somewhere between −π and +π. The third control signal φ3 (312) is also a continuous (analog) or discrete (digital) value, and is either set to a value somewhere between 0 and +π if the first control signal φ1 (308) was set to −π/2, and otherwise the third control signal φ3 (312) is set to a value somewhere between −π and 0 if the first control signal φ1 (308) was set to +π/2. This relationship between the third control signal φ3 (312) and the first control signal φ1 (308) is maintained throughout the control process of method 900.
In step 904, the third control signal φ3 (312) is adjusted (within its current range) to reduce the measured error in the feedback (e.g., feedback 348 of
In step 906, the second control signal φ2 (310) is adjusted to reduce the measured error. The adjustment of the second control signal φ2 (310) can be performed by an optimization or pseudo-optimization algorithm (e.g., a gradient descent algorithm) that seeks to minimize or reduce the measured error. For example, the adjustment of the second control signal φ2 (310) can be performed by searching within a local neighborhood of the current value of second control signal φ2 (310) to find a new value that reduces the measured error. As a specific example, a description will be given in which the second control signal φ2 (310) is adjusted in steps of +/−Δφ2 to find a value that reduces measured error. The step size Δφ2 can be dynamically adjusted in each iteration. For example, in some implementations, the step size Δφ2 can be configured to increase as the value sin2(φ3) (of the third control signal 312) becomes smaller. In the search process of step 906, the second control signal φ2 (310) is first increased by Δφ2 and the resulting error in feedback 348 is measured. Then, the second control signal φ2 (310) is decreased by 2Δφ2 (i.e., decreased by Δφ2 from the original value) and the resulting error in feedback 348 is again measured. The value of the second control signal φ2 (310) that resulted in the lower error is denoted as φ2′ (for purposes of this description).
In step 908, the demultiplexer determines whether the value φ2′<−π (i.e., outside the lower limit). If so, then in step 910, the new adjusted value of the second control signal φ2 (310) is set to −2π−φ2′. Furthermore, in step 912, the first control signal φ1 (308) and the third control signal φ3 (312) are flipped in values. Namely, if the value of the first control signal (308) is φ1=−π/2 (meaning that the third control signal 312 is within a range 0 and +π), then then a value of n is simultaneously added to the first control signal φ1 (308) and subtracted from the third control signal φ3 (312). Alternatively, if the value of the first control signal (308) is φ1=+π/2 (meaning that the third control signal 312 is within a range −π and 0), then a value of n is simultaneously subtracted from the first control signal φ1 (308) and added to the third control signal φ3 (312). The control loop should pause during this simultaneous addition and subtraction. In some implementations, the simultaneous addition and subtraction of n may be performed sequentially (e.g., adjusting the first control signal φ1 (308) and then adjusting the third control signal φ3 (312), or vice versa). Nonetheless, the procedure of adjusting the first control signal φ1 (308) and the third control signal φ3 (312) described above should be performed quickly to avoid long pauses and control lag in the control system.
If it is determined in step 908 that φ2′ is not outside the lower limit, then in step 914, the demultiplexer checks whether φ2′>+π (i.e., outside the upper limit). If so, then in step 916, the new adjusted value of the second control signal φ2 (310) is set to +2n−φ2′. Furthermore, in step 912 (as described above), the values of the first control signal φ1 (308) and the third control signal φ3 (312) are flipped.
If it is determined in step 914 that φ2′ is not outside the upper limit (meaning that φ2′ is within the range of −π to +π), then in step 918, the new adjusted value of the second control signal φ2 (310) is set to φ2′. In this case, the first control signal φ1 (308) and the third control signal φ3 (312) are not flipped. Then, the next iteration of adjusting the control signals is performed, returning back to step 904.
The control process of method 900 can achieve an “endless” operation of demultiplexing without requiring a reset or interruption of data reception. This property is enabled by the fact that when the second control signal φ2 (310) reaches either of end points (+π or −π), then the second stage of phase shifting (304 in
Although the example method 900 in
Furthermore, the specific ranges of values described in step 902 can be modified. For example, the possible values of the first control signal φ1 (308) can have a fixed offset, so as to be a shifted binary value of (−π/2+c) or (+π/2+c). The possible values of the second control signal φ2 (310) could be shifted by integer multiples of 2π, as long as the end points of the range enable the pass-through property discussed above. The possible values of the third control signal φ3 (312) could also be shifted by integer multiples of 2π.
Although the example method 1000 illustrates control of both relative attenuation control signals a1 (408) and a2 (414), in some scenarios only one of the signals is implemented. For example, in some implementations, only the first control signal a1 is implemented. This may be appropriate, for example, in scenarios where the PDL levels are moderate (e.g., in scenarios where the only source of PDL is in the receiver, rather than in the fiber transmission line itself). Furthermore, if the PDL values are not expected to change significantly over time, then the control value a1 can be set once at the beginning of operation (e.g., in a factory), and left unchanged.
Alternatively, as shown in method 1000, both optical attenuation control signals a1 and a2 are can be adjusted (e.g., continuously), for example by using variable optical attenuators (VOAs). This may be appropriate, for example, in scenarios where PDL levels are more significant (e.g., in scenarios where PDL occurs in both the receiver and in the fiber transmission line).
In general, the relative attenuation signals a1 (408) and a2 (414) can be controlled using an optimization or pseudo-optimization process, designed to reduce or minimize the measured error in the feedback (e.g., feedback 460 in
In step 1002, at the beginning of the iterations, the demultiplexer initializes the two VOA control signals a1 (408) and a2 (414) to initial values, for example to zero values.
In step 1004, the first VOA control signal a1 (408) is adjusted (within its allowed range, such as −3 to +3) to reduce the measured error in the feedback. The adjustment of the first VOA control signal a1 (408) can be performed by an optimization or pseudo-optimization algorithm (e.g., a gradient descent algorithm) that seeks to minimize or reduce the measured error. For example, the adjustment of the first VOA control signal a1 (408) can be performed by searching within a local neighborhood of the current value of first VOA control signal a1 (408) to find a new value that reduces the measured error. As a specific example, a description will be given in which the first VOA control signal a1 (408) is adjusted in steps of +/−Δa1 to find a value that reduces measured error. The step size Δa1 can be dynamically adjusted in each iteration. The first VOA control signal a1 (408) is first increased by Δa1 and the resulting error in feedback 460 is measured. Then, the first VOA control signal a1 (408) is decreased by 2Δa1 (i.e., decreased by Δa1 from the original value) and the resulting error in feedback 460 is again measured. The value of the first VOA control signal a1 (408) that resulted in the lower error is assigned as the new, adjusted value of the first VOA control signal a1 (408).
In step 1006, the second VOA control signal a2 (414) is adjusted (within its allowed range, such as −3 to +3) to reduce the measured error. The adjustment of the second VOA control signal a2 (414) can be performed by an optimization or pseudo-optimization algorithm (e.g., a gradient descent algorithm) that seeks to minimize or reduce the measured error. For example, the adjustment of the second VOA control signal a2 (414) can be performed by searching within a local neighborhood of the current value of second control signal a2 (414) to find a new value that reduces the measured error. As a specific example, a description will be given in which the second VOA control signal a2 (414) is adjusted in steps of +/−Δa2 to find a value that reduces measured error. The step size Δa2 can be dynamically adjusted in each iteration. For example, in some implementations, the step size Δa2 can be configured to increase as the value sin2(a1) (of the first VOA control signal 408) becomes smaller (and vice versa). In the search process of step 1006, the second VOA control signal a2 (414) is first increased by Δa2 and the resulting error in feedback 460 is measured. Then, the second VOA control signal a2 (414) is decreased by 2Δ2 (i.e., decreased by Δa2 from the original value) and the resulting error in feedback 460 is again measured. The value of the second VOA control signal a2 (414) that resulted in the lower error is assigned as the new, adjusted value of the second VOA control signal a2 (414). Then, the next iteration of adjusting the control signals is performed, returning back to step 1004.
Although the example method 1000 in
In some implementations, the techniques described herein for optical MIMO polarization demultiplexing can be applied to general 2×2 optical MIMO demultiplexing. For example, in some implementations, the techniques described herein can be implemented separately from or without the PBSR.
Graph 1102 shows an example of an evolution of the three control signals φ1 (308), φ2 (310), and φ3 (312) over time, as they are adjusted by the control algorithm. Graph 1100 shows an example of the resulting amount of crosstalk, namely the error “e” discussed above.
The computing system 1200 is intended to represent various systems that include digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The components shown here, their connections and relationships, and their functions, are meant to be examples only, and are not meant to be limiting.
The computing system 1200 includes a processor 1202, a memory 1204, a storage device 1206, a high-speed interface 1208 connecting to the memory 1204 and multiple high-speed expansion ports 1210, and a low-speed interface 1212 connecting to a low-speed expansion port 1214 and the storage device 1206. Each of the processor 1202, the memory 1204, the storage device 1206, the high-speed interface 1208, the high-speed expansion ports 1210, and the low-speed interface 1212, are interconnected using various busses, and may be mounted on a common motherboard or in other manners as appropriate. The processor 1202 can process instructions for execution within the computing system 1200, including instructions stored in the memory 1204 or on the storage device 1206 to display graphical information for a GUI on an external input/output device, such as a display 1216 coupled to the high-speed interface 1208. In other implementations, multiple processors and/or multiple buses may be used, as appropriate, along with multiple memories and types of memory. In addition, multiple computing devices may be connected, with each device providing portions of the operations (e.g., as a server bank, a group of blade servers, or a multi-processor system). In some implementations, the processor 1202 is a single-threaded processor. In some implementations, the processor 1202 is a multi-threaded processor. In some implementations, the processor 1202 is a quantum computer.
The memory 1204 stores information within the computing system 1200. In some implementations, the memory 1204 is a volatile memory unit or units. In some implementations, the memory 1204 is a non-volatile memory unit or units. The memory 1204 may also be another form of computer-readable medium, such as a magnetic or optical disk.
The storage device 1206 is capable of providing mass storage for the computing system 1200. In some implementations, the storage device 1206 may be or include a computer-readable medium, such as a floppy disk device, a hard disk device, an optical disk device, or a tape device, a flash memory or other similar solid-state memory device, or an array of devices, including devices in a storage area network or other configurations. Instructions can be stored in an information carrier. The instructions, when executed by one or more processing devices (for example, processor 1202), perform one or more methods, such as those described above. The instructions can also be stored by one or more storage devices such as computer- or machine-readable mediums (for example, the memory 1204, the storage device 1206, or memory on the processor 1202). The high-speed interface 1208 manages bandwidth-intensive operations for the computing system 1200, while the low-speed interface 1212 manages lower bandwidth-intensive operations. Such allocation of functions is an example only. In some implementations, the high-speed interface 1208 is coupled to the memory 1204, the display 1216 (e.g., through a graphics processor or accelerator), and to the high-speed expansion ports 1210, which may accept various expansion cards (not shown). In the implementation, the low-speed interface 1212 is coupled to the storage device 1206 and the low-speed expansion port 1214. The low-speed expansion port 1214, which may include various communication ports (e.g., USB, Bluetooth, Ethernet, wireless Ethernet) may be coupled to one or more input/output devices, such as a keyboard, a pointing device, a scanner, or a networking device such as a switch or router, e.g., through a network adapter.
The computing system 1200 may be implemented in a number of different forms, as shown in the figure. For example, it may be implemented as a standard server 1220, or multiple times in a group of such servers. In addition, it may be implemented in a personal computer such as a laptop computer 1222. It may also be implemented as part of a rack server system 1224.
The term “system” as used in this disclosure may encompass all apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers. A processing system can include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.
A computer program (also known as a program, software, software application, script, executable logic, or code) can be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and it can be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub programs, or portions of code). A computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a communication network.
Computer readable media suitable for storing computer program instructions and data include all forms of non-volatile or volatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, e.g., internal hard disks or removable disks or magnetic tapes; magneto optical disks; and CD-ROM and DVD-ROM disks. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry. Sometimes a server is a general-purpose computer, and sometimes it is a custom-tailored special purpose electronic device, and sometimes it is a combination of these things.
Implementations can include a back end component, e.g., a data server, or a middleware component, e.g., an application server, or a front end component, e.g., a client computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the subject matter described is this specification, or any combination of one or more such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication, e.g., a communication network. Examples of communication networks include a local area network (“LAN”) and a wide area network (“WAN”), e.g., the Internet.
The features described can be implemented in digital electronic circuitry, or in computer hardware, firmware, software, or in combinations of them. The apparatus can be implemented in a computer program product tangibly embodied in an information carrier, e.g., in a machine-readable storage device, for execution by a programmable processor; and method steps can be performed by a programmable processor executing a program of instructions to perform functions of the described implementations by operating on input data and generating output. The described features can be implemented advantageously in one or more computer programs that are executable on a programmable system including at least one programmable processor coupled to receive data and instructions from, and to transmit data and instructions to, a data storage system, at least one input device, and at least one output device. A computer program is a set of instructions that can be used, directly or indirectly, in a computer to perform a certain activity or bring about a certain result. A computer program can be written in any form of programming language, including compiled or interpreted languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.
While this disclosure contains many specific implementation details, these should not be construed as limitations on the scope of any invention or of what may be claimed, but rather as descriptions of features that may be specific to particular implementations of particular inventions. Certain features that are described in this disclosure in the context of separate implementations can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.
Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results.
