Patent Application
20240419084
This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2023-0076412, filed on Jun. 14, 2023, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference.
The present disclosure relates to a method of fabricating a semiconductor device, and in particular, to a method of fabricating a semiconductor device using an optical proximity correction (OPC) method.
Due to their small-sized, multifunctional, and/or low-cost characteristics, semiconductor devices are being esteemed as important elements in the electronics industry.
The semiconductor devices are classified into a memory device for storing data, a logic device for processing data, and a hybrid device including both memory and logic elements. As the electronics industry is highly developed, there is an increasing demand for semiconductor devices with improved characteristics. For example, there is an increasing demand for semiconductor devices with high reliability, high performance, and/or multiple functions. To satisfy these technical requirements, complexity and/or integration density of semiconductor devices are being increased.
An embodiment of the inventive concept may provide an OPC method that can preserve the consistency of an OPC process.
An embodiment of the inventive concept may provide a method of fabricating a highly integrated and highly reliable semiconductor device.
According to an embodiment of the inventive concept, a method of fabricating a semiconductor device may include performing an optical proximity correction (OPC) on a design pattern of a layout and forming a photoresist pattern on a substrate using a photomask manufacture based the corrected layout. The performing of the OPC may include analyzing a cell hierarchy to choose a representative cell in the layout, dividing the design pattern in the representative cell into a plurality of segments including first segments, choosing a first unique segment, which represents the first segments, from the plurality of segments, generating a first correction bias of the first unique segment, applying the first correction bias to all of the first segments to generate a correction pattern, and applying a correction result of the representative cell to other cells that are included in the layout and are of a same type as the representative cell.
According to an embodiment of the inventive concept, a method of fabricating a semiconductor device may include performing an optical proximity correction (OPC) on a layout of a memory device and forming a photoresist pattern on a substrate using a photomask manufacture based on the corrected layout. The performing of the OPC may include choosing a representative cell from a plurality of cells in the layout, dividing a design pattern in the representative cell into a plurality of segments, choosing a unique segment from the plurality of segments, and generating a correction bias of the unique segment.
According to an embodiment of the inventive concept, a method of fabricating a semiconductor device may include performing an optical proximity correction (OPC) on a design pattern of a layout, manufacturing a photomask based on the corrected layout, forming an etch-target layer and a photoresist layer on a substrate, performing a photolithography process using the photomask on the photoresist layer to form photoresist patterns, and patterning the etch-target layer using the photoresist patterns. The performing of the OPC may include analyzing a cell hierarchy to choose a representative cell in the layout, dividing the design pattern in the representative cell into a plurality of segments including first and second segments, choosing a first unique segment, which represents the first segments, from the segments, choosing a second unique segment, which represents the second segments, from the segments, generating a first correction bias of the first unique segment, generating a second correction bias of the second unique segment, applying the first correction bias to all of the first segments, and applying the second correction bias to all of the second segments.
Hereinafter, embodiments are described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and redundant descriptions thereof are omitted. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. It is noted that aspects described with respect to one embodiment may be incorporated in different embodiments although not specifically described relative thereto. That is, all embodiments and/or features of any embodiments can be combined in any way and/or combination.
The CPU 10 may be configured to run a variety of software programs, such as application programs, operating systems, and device drivers. For example, the CPU 10 may be configured to run an operating system (not shown) loaded on the working memory 30. Furthermore, the CPU 10 may be configured to run various application programs on the operating system. For example, the CPU 10 may be configured to run a layout design tool 32 and/or an optical proximity correction (OPC) tool 34 loaded on the working memory 30.
The operating system or application programs may be loaded on the working memory 30. For example, when the computer system starts a booting operation, an OS image (not shown) stored in the auxiliary storage 70 may be loaded on the working memory 30 according to a booting sequence. In the computer system, overall input/output operations may be managed by the operating system. Some application programs, which may be selected by a user or be provided for basic services, may be loaded on the working memory 30. According to an embodiment of the inventive concept, the layout design tool 32 and/or OPC tool 34 may be loaded on the working memory 30, from the auxiliary storage 70.
The layout design tool 32 may provide a function for changing biasing data for specific layout patterns; for example, the layout design tool 32 may be configured to allow the specific layout patterns to have shapes and positions different from those defined by a design rule. The layout design tool 32 may be configured to perform a design rule check (DRC) under the changed condition of the bias data. The OPC tool 34 may be configured to perform an OPC process on layout data, which is obtained by the layout design tool 32. The working memory 30 may be one of volatile memory devices (e.g., static random access memory (SRAM) or dynamic random access memory (DRAM) devices) or nonvolatile memory devices (e.g., PRAM, MRAM, ReRAM, FRAM, NOR FLASH memory devices).
The input-output device 50 may be configured to control user input and output operations of user interface devices. For example, the input-output device 50 may include a keyboard or a monitor, allowing a designer to input relevant information. By using the input-output device 50, the designer may receive information on several regions or data paths, to which adjusted operating characteristics will be applied, of a semiconductor device. The input-output device 50 may be configured to display a progress status or a process result of the OPC tool 34.
The auxiliary storage 70 may serve as a storage medium for the computer system. The auxiliary storage 70 may be configured to store application programs, an OS image, and various data. The auxiliary storage 70 may be provided in the form of one of memory cards (e.g., MMC, eMMC, SD, MicroSD, and so forth) or a hard disk drive (HDD). The auxiliary storage 70 may include a NAND FLASH memory device with a large memory capacity. In other embodiments, the auxiliary storage 70 may include one or more next-generation nonvolatile memory devices (e.g., PRAM, MRAM, ReRAM, or FRAM) or NOR FLASH memory devices.
A system interconnector 90 may serve as a system bus for realizing a network in the computer system. The CPU 10, the working memory 30, the input-output device 50, and the auxiliary storage 70 may be electrically connected to each other through the system interconnector 90, and thus, data may be exchanged therebetween. However, the system interconnector 90 may not be limited to the afore-described configuration; for example, it may further include an additional element for increasing efficiency in data communication.
Referring to
A layout design process may be performed to realize a logically complete form of the semiconductor integrated circuit on a silicon wafer (S20). For example, the layout design process may be performed, based on the schematic circuit prepared in the high-level design process or the corresponding netlist. The layout design process may include a routing operation of placing and connecting various standard cells that are provided from a cell library, based on a predetermined design rule.
The cell library may contain, but is not limited to, information on operation, speed, and power consumption of cells. In an embodiment, a cell library for representing a layout of a circuit at a gate level may be defined in or by the layout design tool. Here, the layout may be prepared to define or describe shapes, positions, or dimensions of patterns constituting transistors and metal interconnection lines, which will be formed on a silicon wafer. For example, to form an inverter circuit on a silicon wafer, it may be necessary to prepare or draw a layout for patterns (e.g., PMOS, NMOS, N-WELL, gate electrodes, and metal interconnection lines thereon). For this, at least one of the inverters defined in the cell library may be selected.
Furthermore, a routing operation of connecting the selected cells to each other may be performed. In detail, the routing operation may be performed on the selected and placed standard cells to connect them to upper interconnection lines. The afore-described steps may be automatically or manually performed by the layout design tool. Furthermore, an operation of placing and routing the standard cells may be automatically performed by an additional Place & Routing tool.
After the routing operation, a verification operation may be performed on the layout to check whether there is a portion violating the given design rule. In an embodiment, the verification operation may include evaluating verification items, such as a design rule check (DRC), an electrical rule check (ERC), and a layout vs schematic (LVS). The evaluating of the DRC item may be performed to evaluate whether the layout meets the given design rule. The evaluating of the ERC item may be performed to evaluate whether there is an issue of electrical disconnection in the layout. The evaluating of the LVS item may be performed to evaluate whether the layout is prepared to coincide with the gate-level netlist.
An optical proximity correction (OPC) operation may be performed (S30). The OPC operation may be performed to correct optical proximity effects, which may occur when a photolithography process is performed on a silicon wafer using a photomask manufactured based on the layout. The optical proximity effect may be an unintended optical effect (such as refraction or diffraction), which may occur in the exposing process using the photomask manufactured based on the layout. In the OPC operation, the layout may be modified to reduce a difference in shape between designed patterns and actually-formed patterns, which may be caused by the optical proximity effects. As a result of the OPC operation, the shapes and positions of patterns in the designed layout may be changed or biased. The OPC operation will be described in more detail with reference to
A photomask may be manufactured, based on the layout modified by the OPC operation (S40). In general, the photomask may be manufactured by patterning a chromium layer provided on a glass substrate using the layout pattern data.
The photomask manufactured may be used to manufacture a semiconductor device (S50). In the actual fabricating process, the exposing and etching operations may be repeatedly performed, and thus, patterns defined in the layout design process may be sequentially formed on a semiconductor substrate.
The light source 1200 may be configured to emit light. The light emitted from the light source 1200 may be incident into the photomask 1400. To control a focal length, a lens may be provided between the light source 1200 and the photomask 1400. The light source 1200 may be configured to emit an ultraviolet light; for example, the light source 1200 may be a KrF light source (at 234 nm), an ArF light source (at 193 nm), or an extreme ultraviolet (EUV) light source. In an embodiment, the light source 1200 may be the EUV light source. The light source 1200 may include a single point light source P1, but embodiments of the inventive concept may not be limited thereto. In an embodiment, the light source 1200 may be configured to have a plurality of point light sources.
The photomask 1400 may include image patterns, which are used to transcribe or print the designed layout onto the substrate SUB. The image patterns may be formed, based on layout patterns, which are prepared through layout design and OPC operations described above. The image patterns may be defined by transparent and opaque regions formed on the photomask 1400. The transparent region may be formed by etching the metal layer (e.g., the chromium layer) that is provided on the photomask 1400. The transparent region may be configured to allow light, which is incident from the light source 1200, to propagate toward the substrate SUB. By contrast, the opaque region may be configured to inhibit or prevent the light from propagating toward the substrate SUB.
The light passing through the transparent region of the photomask 1400 may be incident into a photoresist layer, which is formed on the substrate SUB, through the reduction projection apparatus 1600, and as a result, photoresist patterns may be formed on the substrate SUB. The photoresist patterns may have shapes corresponding to the image patterns of the photomask 1400. That is, by using the reduction projection apparatus 1600, it may be possible to form the photoresist patterns, whose shapes are defined by the image patterns of the photomask 1400, on the substrate SUB.
The substrate stage 1800 may be configured to support the substrate SUB. The substrate SUB may include, for example, a silicon wafer. The reduction projection apparatus 1600 may include an aperture. The aperture may be used to control a depth of focus, when the ultraviolet light emitted from the light source 1200 is incident onto the substrate SUB. As an example, the aperture may include a dipole or quadruple aperture. The reduction projection apparatus 1600 may further include a lens for controlling a focal length.
As an integration density of a semiconductor device increases, a distance between the image patterns of the photomask 1400 may be reduced, thereby causing a proximity issue such as undesired interference and diffraction. As a result of the proximity issue, the photoresist patterns formed on the substrate SUB may have distorted shapes (i.e., different from those of the image patterns of the photomask 1400). The distortion of the photoresist patterns may lead to malfunction of an electronic device or circuit to be formed on the substrate SUB.
A resolution enhancement technology may be used to reduce or prevent the distortion of the photoresist patterns. An OPC technology, which is used in the OPC operation S30 of
A layout of a semiconductor device may include a plurality of layers. In an embodiment, the OPC operation may be performed to correct a layout for each of the layers. In other words, the OPC operation may be independently performed on each of the plurality of layers. A semiconductor device may be manufactured by forming the plurality of layers on a substrate through a semiconductor process. As an example, a semiconductor device may include a plurality of stacked metal layers constituting a specific circuit.
A designed layout LO may include first to fourth circuit patterns R1, R2, R3, and R4. To reduce complexity in the drawings and to provide better understanding of the inventive concept, an example of a shape of the designed layout LO is illustrated in
As described above, owing to the optical distortion issue caused by interference and diffraction, photoresist patterns on the substrate SUB may have shapes different from those in the designed layout LO. For example, even when the image patterns of the photomask 1400 are formed to have shapes depicted by the solid lines of
An OPC operation may be performed to reduce or prevent the distortion of the patterns. For example, to reduce a difference between the actual pattern (depicted by the dotted line of
In the present specification, the term “division” may not mean a physical division and may, in some examples, mean identifying one region or portion from another region or portion. Furthermore, although a plurality of segments are illustrated in
In the OPC operation, each of the divided segments SEG may be a unit object to which the biasing can be applied. Each of the divided segments SEG may be independently biased. For example, one of the segments SEG may be biased in one of a first direction (e.g., a positive or outward direction) and a second direction (e.g., a negative or inward direction), independent of the other ones of the segments SEG. Each of the divided segments SEG may be biased to reduce a difference in shape or size between the actual and target patterns. The biasing of the divided segments SEG may be performed by the OPC tool 34 of
The dotted line of
As an example, referring to
An actual pattern printed on the substrate SUB may have a shape depicted by the dotted line. The actual pattern may have substantially the same shape and size as those of the target pattern depicted by the solid line. That is, by using the afore-described OPC operation, it may be possible to reduce a difference between the actual and target patterns.
Referring to
According to an embodiment of the inventive concept, the layout LO may contain information on a cell hierarchy. For example, the layout LO may be a layout of a memory device. In general, the layout LO may contain information on the cell hierarchy for the memory device, in which unit memory cells are repeatedly arranged. According to the cell hierarchy, the layout LO may include a plurality of cells CEL as illustrated in
A representative cell may be chosen from the layout LO by analyzing the cell hierarchy (S31). In detail, the layout LO of
Hereinafter, the optical proximity correction process will be described with reference to an example, in which the first cell CEL1 placed at the top left of
In detail, the layout of the first cell CEL1 may be divided into a plurality of patches PA by using the OPC tool 34 of
The portion ‘M’ of the first cell CEL1 may include a plurality of design patterns LIP1 to LIP6. As an example, the design patterns LIP1 to LIP6 may correspond to the circuit patterns R1 to R4 previously described with reference to
A data preparation operation may be executed on the representative cell CEL1 including the first to sixth design patterns LIP1 to LIP6. The data preparation step may include performing an optical proximity correction (OPC) step on a designed layout (
Referring to
The contour may be divided into a plurality of segments SEG, based on the division points PD. In an embodiment, the design pattern LIP1 to LIP6 may be divided into the segments SEG in the same manner as described with reference to
The division points PD on the first, second, fifth, and sixth design patterns LIP1, LIP2, LIP5, and LIP6 may be created with a specific distance. Thus, segments SEG with the same length may be created in the first, second, fifth, and sixth design patterns LIP1, LIP2, LIP5, and LIP6. By contrast, segments SEG with different lengths may be created in the third and fourth design patterns LIP3 and LIP4. This may be because additional division point PD_F are created at points of the contour that intersect the patch boundary BND.
Referring to
A hash value may be generated based on a pattern image in the query region QR (S332). The pattern image may include a shape of the target segment TSG, a shape of a neighboring segment SEG, and a distance between the target segment TSG and the neighboring segment SEG. In other words, the hash value of the target segment TSG may reflect information on the shape of the target segment TSG, the shape of the neighboring segment SEG, and the distance between the target segment TSG and the neighboring segment SEG. The hash value of the target segment TSG may be generated as a unique 64-bit value. The hash value of the target segment TSG may be a hash ID of the target segment TSG.
The hash value for each of the segments SEG may be generated by choosing each of the segments SEG as a target segment based on the afore-described method.
Referring to
As an example, the fifth unique segment USG5 may be adjacent to the patch boundary BND. Owing to the patch boundary BND, the fifth unique segment USG5 may have a length different from the first unique segment USG1, and thus, the fifth unique segment USG5 may have a hash value different from the first unique segment USG1.
For example, the seventh unique segment USG7 may include a segment of a short length, like the fifth unique segment USG5 in the query region, and thus, the seventh unique segment USG7 may have a hash value different from the second unique segment USG2.
Referring to
The first bias BI1 may be commonly applied to first segments SEG1, which have the same hash value (i.e., the first hash value (#1))) as the first unique segment USG1. In this case, the first segments SEG1 may be biased or shifted in a first direction DI by the first bias BI1.
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
A correction bias may be applied to all of the segments SEG through the afore-described processes. In embodiments of the inventive concept, the correction bias may not be independently calculated for and applied to each of the segments SEG. If each of the segments SEG is independently corrected, the execution time for the OPC step may be excessively increased. According to an embodiment of the inventive concept, a correction bias may be obtained for the unique segment USG, and then, the obtained correction bias may be applied to all of the segments SEG that have the same hash value. Thus, the execution time for the OPC step may be significantly reduced.
The corrected segments SEG may constitute a correction pattern COP. For example, first to sixth correction patterns COP1 to COP6 may be generated by applying an OPC operation to the first to sixth design patterns LIP1 to LIP6. The OPC operation on the first cell CEL1, which serves as the representative cell, may be completed through the operations previously described with reference to
Referring to
The OPC operation on the second cells CEL2 in the layout LO may be performed in the same manner as the afore-described OPC step on the first cells CEL1. The OPC operation on the third cells CEL3 in the layout LO may be performed in the same manner as the afore-described OPC step on the first cells CEL1.
If the correction patterns COP are respectively generated for design patterns LIP in the layout LO, the mask rule check (MRC) step may be executed on the generated correction patterns COP (S38 of
In a subsequent developing process, all regions of the photoresist layer PRL other than the photoresist patterns PRP may be removed, and the photoresist patterns PRP may be left. An etch target layer TGL on the substrate SUB may be patterned using the left photoresist patterns PRP as an etch mask. Thus, desired target patterns may be formed on the substrate SUB. By forming target patterns in each layer using this method, it may be possible to manufacture a semiconductor device (S50 of
In the OPC operation described with reference to
Furthermore, even in the OPC step on the representative cell, a unique segment may be chosen, based on hash values of the segments. A correction bias may be generated for the unique segment. The correction bias may be applied to the remaining ones of the segments that have the same hash value as the unique segment. Thus, it may be possible to maintain the consistency of the OPC operation, increase the accuracy of the OPC operation, and reduce the execution time for the OPC operation.
Referring to
The active patterns ACT may be realized using a photolithography process. A photomask, which is used in the photolithography process for realizing the active patterns ACT, may be manufactured through the OPC method described with reference to
In an embodiment, the patterning process to form the active patterns ACT may include an EUV lithography process. The EUV lithography process may include performing an exposing process of irradiating the EUV light onto a photoresist layer and performing a developing process of developing the photoresist layer. As an example, the photoresist layer may be an organic photoresist layer containing an organic polymer (e.g., polyhydroxystyrene). The organic photoresist layer may further include a photosensitive compound which can be reacted with the EUV light. The organic photoresist layer may further contain a material having high EUV absorptivity (e.g., organometallic materials, iodine-containing materials, or fluorine-containing materials). As another example, the photoresist layer may be an inorganic photoresist layer containing an inorganic material (e.g., tin oxide).
The photoresist layer may be formed to have a relatively small thickness. Photoresist patterns may be formed by developing the photoresist layer, which is exposed to the EUV light. When viewed in a plan view, the photoresist patterns may be formed to have a line shape extending in a specific direction, an island shape, a zigzag shape, a honeycomb shape, or a circular shape, but embodiments of the inventive concept are not limited to these examples.
Mask patterns may be formed by patterning at least one layer, which is disposed below the photoresist patterns, using the photoresist patterns as an etch mask. Desired patterns may be formed on a wafer by patterning a target layer using the mask patterns as an etch mask.
For example, the minimum pitch between the active patterns ACT, which are realized by the EUV lithography process according to the present embodiment, may be less than or equal to 45 nm. In other words, by using the EUV lithography process, it may be possible to form the active patterns ACT precisely and finely with just one photomask.
First and second trenches TRI and TR2 may be defined between the active patterns ACT. The first trench TR1 may be defined between a pair of active patterns ACT, which are adjacent to each other in the second direction D2. The second trench TR2 may be defined between a pair of active patterns ACT, which are adjacent to each other in the third direction D3.
In some embodiments, a device isolation layer ST may be formed to at least partially fill the first and second trenches TRI and TR2. In some embodiments, the device isolation layer ST may be formed to completely fill the first and second trenches TRI and TR2 and to at least partially cover the active patterns ACT. A planarization process may be performed on the device isolation layer ST to expose the top surfaces of the active patterns ACT.
Referring to
The formation of the third trenches TR3 may include forming a hard mask pattern with openings and etching the exposed portions of the active patterns ACT and the device isolation layer ST using the hard mask pattern as an etch mask. The third trench TR3 may be formed to be shallower than the first trench TR1.
Referring to
TR3. In detail, the gate insulating layer GI may be formed to conformally at least partially cover the third trench TR3. The gate insulating layer GI may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and/or a high-k dielectric layer.
The gate electrode GE may be formed on the gate insulating layer GI by forming a conductive layer to at least partially fill the third trench TR3. The conductive layer may be formed of or include one or more conductive metal nitrides and/or metallic materials.
The gate insulating layer GI and the gate electrode GE may be recessed to form an empty region and then, the gate capping layer GP may be formed in the empty region or on the recessed gate electrode GE. The gate capping layer GP may be formed to have a top surface that is coplanar with the top surface of the active pattern ACT.
An ion implantation process may be performed on the active patterns ACT to form a first source/drain region SD1 and a pair of second source/drain regions SD2 in an upper portion of the active pattern ACT. The pair of second source/drain regions SD2 may be spaced apart from each other in the third direction D3, with the first source/drain region SD1 interposed therebetween. In an embodiment, the first and second source/drain regions SD1 and SD2 may be doped with the same impurities.
A channel region CH may be defined in a portion of the active pattern ACT located below the gate electrode GE in the D4 direction. When viewed in a plan view, the channel region CH may be interposed between the first source/drain region SD1 and the second source/drain region SD2. The gate electrode GE may be provided on the top surface and opposite side surfaces of the channel region CH (e.g., see
Referring to
Referring to
The barrier layer BAL may be formed to be interposed between the first conductive layer CL1 and the second conductive layer CL2. The barrier layer BAL may be formed of or include one or more conductive metal nitrides. The second conductive layer CL2 may be formed of or include one or more metallic materials. The barrier layer BAL may prevent or suppress a metallic material in the second conductive layer CL2 from being diffused into the first conductive layer CL1.
Referring to
In detail, mask patterns MP may be formed on the second conductive layer CL2. The mask patterns MP may be formed in a line shape extending in the first direction D1. As an example, the mask patterns MP may be formed of or include silicon nitride and/or silicon oxynitride.
A bit line BL, a barrier pattern BP, and a conductive pattern CP may be formed by sequentially patterning the second conductive layer CL2, the barrier layer BAL, and the first conductive layer CL1 using the mask patterns MP as a mask. The mask pattern MP, the bit line BL, the barrier pattern BP, and the conductive pattern CP may be vertically, i.e., D4 direction, overlapped with each other. The mask pattern MP, the bit line BL, the barrier pattern BP, and the conductive pattern CP may constitute the line structure LST. When viewed in a plan view, the bit lines BL may be extended to cross the gate electrodes GE.
The conductive pattern CP may include contact portions CNP at least partially filling the first contact holes CNH1, respectively. The conductive pattern CP may be connected to the first source/drain region SD1 through the contact portion CNP. In other words, the bit line BL may be electrically connected to the first source/drain region SD1 through the conductive pattern CP.
A pair of spacers SP may be formed on opposite side surfaces of each of the line structures LST. The formation of the spacers SP may include conformally forming a spacer layer on the entire top surface of the substrate SUB and anisotropically etching the spacer layer.
An etching process using the spacers SP and the mask patterns MP as a mask may be performed on the entire top surface of the substrate 100 to form second contact holes CNH2 exposing the second source/drain regions SD2, respectively. In detail, the second contact hole CNH2 may be formed to penetrate the insulating layer IL and may be extended to a level lower in the D4 direction than the top surface of the substrate SUB. When the second contact hole CNH2 is formed, an upper portion of the second source/drain region SD2 may be partially recessed. When the second contact hole CNH2 is formed, an upper portion of the device isolation layer ST around the second source/drain region SD2 may be partially recessed.
Referring to
Contacts CNT may be respectively formed in the second contact holes CNH2 by at least partially filling the second contact holes CNH2 with a conductive material. The contacts CNT may be connected to the second source/drain regions SD2. In detail, the conductive material may be formed on the entire top surface of the substrate SUB and then may be recessed until a top surface of the conductive material is lower in the D4 direction than top surfaces of the insulating fences IFS. In this case, the conductive material may be cut by the insulating fences IFS, and as a result, the contacts CNT may be formed in the second contact holes CNH2, respectively. The contacts CNT and the insulating fences IFS may be alternately arranged in the first direction D1.
The conductive material at least partially filling the second contact holes CNH2 may be formed of or include one or more doped semiconductor materials. In an embodiment, the second contact holes CNH2 may be at least partially filled with a doped semiconductor material, and then, impurities in the semiconductor material may be diffused into the second source/drain regions SD2.
Referring to
The patterning of the metal layer may be performed using the photolithography process previously described with reference to
Since the photomask manufactured through the afore-described OPC method is used to form the landing pads LP, the landing pads LP may be precisely formed, even when the landing pads LP have fine sizes and fine pitches. Thus, it may be possible to form the landing pads LP on the contacts CNT, respectively, without a process defect issue.
An insulating pattern INP may be formed by at least partially filling a space between the landing pads LP with an insulating material. First electrodes LEL may be formed on the landing pads LP, respectively. The afore-described photolithography process may be used as a part of a patterning process to form the first electrodes LEL.
A dielectric layer HDL may be conformally formed on the first electrodes LEL. A second electrode TEL may be formed on the dielectric layer HDL. The first electrode LEL, the dielectric layer HDL, and the second electrode TEL may constitute a data storing element DS (e.g., a capacitor). Although not shown, metal layers (e.g., M1, M2, M3, M4, and so forth) may be further formed on the second electrode TEL.
In an OPC method according to an embodiment of the inventive concept, a representative cell, on which an OPC process will be executed, may be chosen using information on cell hierarchy, and the OPC process may be selectively executed on a unique segment, which is selected in the representative cell. In this case, it may be possible to maintain the consistency of the OPC process and reduce the execution time of the OPC process.
While example embodiments of the inventive concept have been particularly shown and described, it will be understood by one of ordinary skill in the art that variations in form and detail may be made therein without departing from the spirit and scope of the attached claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0076412 | Jun 2023 | KR | national |
