Patent Application
20130232456
1. Field of the Invention
Generally, the present disclosure relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to various optical proximity correction (OPC) methods as it relates to the design of masks or reticles to be used in multiple patterning processes, such as double patterning processes, and the use of such masks or reticles in various photolithography systems to manufacture integrated circuit products.
2. Description of the Related Art
Photolithography is one of the basic processes used in manufacturing integrated circuit products. At a very high level, photolithography involves (1) forming a layer of light or radiation-sensitive material, such as photoresist, above a layer of material or a substrate, (2) selectively exposing the radiation-sensitive material to a light generated by a light source (such as a DUV or EUV source) to transfer a pattern defined by a mask or reticle (inter-changeable terms) to the radiation-sensitive material, and (3) developing the exposed layer of radiation-sensitive material to define a patterned mask layer. Various process operations, such as etching or ion implantation processes, may then be performed on the underlying layer of material or substrate through the patterned mask layer.
The design and manufacture of reticles used in such photolithography processes is a very complex and expensive undertaking as such masks must be very precise and must enable the repeated and accurate formation of a desired pattern in the underlying layer of material (for an etching process). It is well known that, for a variety of reasons, photolithography systems do not print exactly what is depicted in a theoretical target pattern, e.g., the lengths of line-type features may be shorter than anticipated, corners may be rounded instead of square, etc. There are several factors that cause such printing differences, such as interference between light beams transmitted through adjacent patterns, resist processes, the reflection of light from adjacent or underlying materials or structures, unacceptable variations in topography, etc. Such errors will generally be referred to herein as optical proximity errors. One technique used in designing and developing masks for use in semiconductor manufacturing to overcome or at least reduce such optical proximity errors involves the use of software-based optical proximity correction (OPC) techniques in an effort to make sure that a mask, when used, generates the desired pattern on the target material or structure in a reliable and repeatable manner. In recent years, the accuracy of pattern transfer in photolithography processes has become even more important and more difficult due to, among other things, the ongoing shrinkage of various features on integrated circuit devices.
There are several OPC correction methods that have been employed within the industry. These methods are roughly classified into rules-based approaches and simulation-based approaches. Both of these techniques are software-based approaches that are time-consuming and expensive to perform. In general, rules-based approaches involve modifying the mask or reticle to account for errors that are anticipated in the photolithography process. For example, using a rules-based approach may involve making a mask wherein the geometry of a feature on the mask is modified (e.g., a line may be lengthened to account for a reduced length when actually printed), a corner stressing pattern may be placed in corners of the pattern to reduce corner rounding, one or more assist features (that are smaller than the resolution limit of the photolithography) may be formed on a mask, etc. Simulation-based approaches used for OPC involve modeling the exposure processes and attempting to predict, based upon such models, how accurately a target pattern will be formed using a particular photolithography process. Such simulation-based approaches typically require a great deal of processing time and very lengthy calculations.
The photolithographic masks or reticles referred to above comprise geometric patterns corresponding to the circuit components that are part of an integrated circuit product. The patterns used to create such masks or reticles are generated utilizing computer-aided design (CAD) programs, wherein this process is sometimes referred to as electronic design automation. Most CAD programs follow a set of predetermined design rules in order to create functional masks. These rules are set by processing and design limitations. For example, design rules define the space tolerance between circuit devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the circuit devices or lines do not interact with one another in an undesirable way. The design rule limitations are typically referred to as “critical dimensions” (CD). A critical dimension of a circuit can be defined as the smallest width of a line or hole or the smallest space between two lines or two holes. Thus, the CD determines the overall size and density of the designed circuit.
Of course, the ultimate goal in integrated circuit fabrication is to faithfully reproduce the original circuit design on the integrated circuit product. Historically, the feature sizes and pitches (spacing between features) employed in integrated circuit products were such that a desired pattern could be formed using a single patterned photoresist masking layer. However, in recent years, device dimensions and pitches have been reduced to the point where existing photolithography tools, e.g., 193 nm wavelength photolithography tools, cannot form single patterned mask layer with all of the features of the overall target pattern. Accordingly, device designers have resorted to techniques that involve performing multiple exposures to define a single target pattern in a layer of material. One such technique is generally referred to as double patterning. In general, double patterning is an exposure method that involves splitting (i.e., dividing or separating) a dense overall target circuit pattern into two separate, less-dense patterns. The simplified, less-dense patterns are then printed separately on a wafer utilizing two separate masks (where one of the masks is utilized to image one of the less-dense patterns, and the other mask is utilized to image the other less-dense pattern). Further, in some cases, the second pattern is printed in between the lines of the first pattern such that the imaged wafer has, for example, a feature pitch which is half that found on either of the two less-dense masks. This technique effectively lowers the complexity of the photolithography process, improving the achievable resolution and enabling the printing of far smaller features than would otherwise be possible using existing photolithography tools.
While OPC processes are performed on each of the two less-dense masks in such a double patterning process, to date the OPC treatments of the respective masks is often insufficient to obtain acceptable imaging performance. This is due in part to the stronger proximity effects that occur when imaging features having increasingly smaller CDs, such as, for example, in the 20 nm mode, and such problems are only expected to increase as device dimensions continue to be reduced.
The present disclosure is directed to various optical proximity correction (OPC) methods as it relates to the design of masks or reticles to be used in multiple patterning processes and to the use of such masks or reticles in various photolithography systems to manufacture integrated circuit products.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
Generally, the present disclosure is directed to various optical proximity correction methods as it relates to the design of masks or reticles to be used in multiple patterning processes and to the use of such masks or reticles in various photolithography systems to manufacture integrated circuit products. One illustrative method disclosed herein includes the steps of decomposing an initial overall target pattern into at least a first sub-target pattern and a second sub-target pattern, wherein each of the first and second sub-target patterns comprise at least one feature, and performing a first optical proximity correction process on the first sub-target pattern, wherein a position of at least one feature of the second sub-target pattern in the initial overall target pattern is considered when performing the first optical proximity correction process.
In another illustrative example, a method disclosed herein includes the steps of decomposing an initial overall target pattern into at least a first sub-target pattern and a second sub-target pattern, wherein each of the first and second sub-target patterns comprise a plurality of features, performing a first optical proximity correction process on the first sub-target pattern wherein a position of each of the plurality of features of the second sub-target pattern in the initial overall target pattern is considered when performing the first optical proximity correction process, and performing a second optical proximity correction process on the second sub-target pattern, wherein a position of each of the plurality of features of the first sub-target pattern in the initial overall target pattern is considered when performing the second optical proximity correction process.
The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
Various illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
The present subject matter will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
The present disclosure is directed to various OPC methods as it relates to the design of masks to be used in multiple patterning processes, such as double patterning processes, and to the use of such masks during the manufacture of integrated circuit products. As will be readily apparent to those skilled in the art upon a complete reading of the present application, the methods disclosed herein may be employed in the fabrication of a variety of devices, such as logic devices, memory devices, ASICs, etc., and they may be employed to manufacture semiconductor devices as device dimensions continue to shrink. With reference to the attached figures, various illustrative embodiments of the methods disclosed herein will now be described in more detail.
The positions of the features 12A, 12B that are in the second sub-target pattern 10B may be input into a computer system that is used in performing the OPC process on the first sub-target pattern 10A using a variety of known techniques. In one example, a mask-rule-constraint (MRC) method may be used to define various constraints between the features in the first sub-target pattern 10A and the features 12A, 12B from the second sub-target pattern 10B. That is, various dimensional constraints may be established between the feature 14 in the first sub-pattern 10A and the features 12A and/or 12B from the second sub-target pattern 10B. Such MRC constraint methodologies are well known to those skilled in the art. In another illustrative example, an inverse of the reference layer, i.e., an inverse of the second sub-target pattern 10B, may be input using a “wafer-enclosed-by” command found in many OPC programs to effectively result in an image for the first exposure that will not bridge with the inverted reference layer. Of course, other methods may be employed to input the desired features from the second sub-target pattern 10B into the OPC process that is performed on the first sub-target pattern 10A, e.g., the features from the second sub-target pattern 10B appear only on the printed image on the wafer and not on the first mask associated with the first sub-target pattern 10A. This discussion about illustrative techniques for inputting information from a second sub-target pattern into an OPC process performed on a first sub-target pattern apply equally to all such similar situations described below.
In
OPC process 60C being performed for the second sub-target pattern 16B.
The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.
