Patent Grant
7409505
An embodiment of the invention relates generally to a cache coherence protocol in a multi-processor system.
Computers read, store, and manipulate data in memory. Ideally, a computer would have a singular, indefinitely large and very fast memory, in which any particular data would be immediately available to the computer. In practice, this is not practical because memory that is very fast is also very expensive.
Thus, computers typically have a hierarchy (or levels) of memory, each level of which has greater capacity than the preceding level, but which is also slower with a less expensive per-unit cost. Keeping frequently-needed data in a small but fast level of memory and infrequently-needed data in a slow level of memory can substantially increase the performance of a computer.
Another way to increase performance is to use multiple processors executing simultaneously, each with their own cache (fast level of memory) but sharing data. The caching of shared data among multiple processors introduces a new problem: cache coherence, that is if multiple processors each have a cached copy of data from a shared memory location, all of those cached copies need to be the same.
To ensure cache coherence, multi-processors systems use a technique called a cache coherence protocol. In a conventional coherence protocol, a write from a first processor's memory to a second processors's memory would go through the following steps: first processor performs a write, which results in a miss in a cache local to the first processor. A request is sent to a node of a second processor, which consults a directory. A controller for the send processor reads the target line from either from memory or from a cache local to the second processor and sends the line to the first processor, where the line is saved in the first processor's cache, modified, and marked as dirty. Later, the second processor reads the memory location written by the first processor, misses in the second processor's local cache, and consults the second processor's directory, which forwards the request to the first processor, which reads the dirty line from the first processor's cache. The line is sent to the second processor where it is written into the second processor's cache, and optionally into the second processor's memory.
Thus, in this scenario, four network traversals are performed, and the entire line is copied first from the second processor to the first processor, and then from the first processor back to the second processor. This is very inefficient, especially if the first processor merely wanted to send the second processor a single word.
The coherence mechanism supports a distributed memory programming model (in which processors each maintain their own memory area, and communicate data between them) without the overhead required to support global caching of data values. Moreover, since a modest caching domain is implemented (allowing a line to be cached by a number of processors within a caching domain), a hierarchical programming model is supported, which uses distributed memory semantics on top of shared memory nodes with a small number of processors per node. Coherence is maintained globally, but caching is restricted to a local region of the machine (a “node” or “caching domain”). In an embodiment, a directory cache is held entirely in an on-chip cache and is multi-banked, allowing very high transaction throughput. Directory associativity allows the directory cache to map contents of all caches concurrently. References off node are converted to non-allocating references, allowing the same access mechanism (a regular load or store) to be used for both for intra-node and extra-node references. Stores (Puts) to remote caches automatically update the caches instead of invalidating the caches, allowing producer/consumer data sharing to occur through cache instead of through main memory.
The Dcache 120 functions in write-through mode, and is kept coherent with the Ecache 115 through selective invalidations performed by the Ecache 115. The Dcache 120 is a data cache. The Ecache 115 is a frontside cache shared by all the processors 110 and is used for scalar, vector, and instruction data. Each Ecache chip 115 may have system ports to the local memory and network. The Ecache 115 is responsible for enforcing ordering of vector and scalar memory references as dictated by local memory synchronization instructions.
The sixteen M chips on a node may contain memory controllers, network interfaces and cache coherence directories with their associated protocol engines. In an embodiment, the memory system is sliced across the 16 M chips, round robin by 32-byte cache lines; each M chip supports one slice.
In an embodiment, each M chip resides in one of sixteen independent address slices of the machine, and the interconnection network may provide connectivity only between corresponding M chips on different nodes. All activity (cache, memory, network) relating to a line of memory stays within the corresponding slice. Each M chip controls a separate sector of a slice. Slices expand (get more memory in each) as nodes are added so the number of sectors in each slice is equal to the number of nodes in system. In an embodiment, each M chip may contain two network ports.
Virtual addresses used for instruction fetches and data references are first translated into physical addresses before memory is accessed. Two forms of address translation are supported: source translation and remote translation. In source translation, a virtual address is fully translated by a translation look aside buffer (TLB) on the local P chip to a physical address on an arbitrary node. A TLB is a cache of page table entries, which is loaded on demand under software control. In an embodiment, each P chip may contain three separate TLBs, for translating instructions, scalar references, and vector references, respectively. The three TLBs are independent, and may contain different sets of page table entries. Each is eight-way set associative, and contains 256 total entries in an embodiment. The vector TLB is replicated four times for bandwidth purposes, but will contain identical data under normal operation.
The cache coherence protocol consists of a set of cache line states in the Dcache, Ecache and directory, a set of messages sent between entities, and a set of state transitions on message and program events.
The cache coherence protocol has the following attributes:
Each entry in a directory cache consists of a tag field indicating the memory line to which the entry refers, a state field indicating the global state of the line, and a sharing vector that points to Ecaches that have cached a copy of the line. The directories track caching on an Ecache, rather than a processor granularity.
Caching of each line of memory is restricted to those Ecaches on the local, node.
In the global Exclusive state, only one Ecache has a cached copy of a line, and thus the sharing vector for that line will contain exactly one set bit. In the global Shared state, multiple Ecaches may have cached a copy of a line, and thus multiple bits may be set in the sharing vector. At the time a Shared line is invalidated, the directory sends invalidations to all Ecaches indicated in the association directory entry's sharing vector.
Hardware in the P chip automatically forces all references to memory outside the node to be non-allocating. This feature is functionally invisible to software, effecting performance only. The entire machine is still cache coherent. Atomic memory operations are still supported across the entire machine, as are load/store references, which are not cached outside the local node.
Coherence States
Local States
Table 1 lists the possible states associated with a line in the Ecache. The PendingReq state indicates that a request has been sent to the directory for this line. Information about the processor request that caused the directory request is saved in a local buffer, and the line is unavailable for further requests until the directory request is satisfied. In the WaitForVData and WFVDInvalid state, a VWrite packet has been processed, but the matching VWriteData packet has not. The line is unavailable for other requests until the data is written.
In addition to this state, each line in the Ecache includes a mask indicating whether the line has been read by each of the four local processors. If all bits are zero in this mask, then the line is not cached in any of the local Dcaches. If any bits are set, then the associated Dcaches may contain a copy of the line.
Two other masks are maintained by the Ecache for transient lines. A sword mask is used for scalar stores that caused allocations. The data for the store is placed in the cache, and when the ReadExclResp arrives from memory, the mask is used to avoid overwriting this data.
Another mask is created when entering WaitForVData state or “PendingReq state on a vector store. This mask keeps track of words that are going to be written by the vector store. Subsequent vector or scalar stores that get placed into the Replay Queue merge their masks into this mask, so it keeps a running record of dwords that are scheduled to be written. Then, in WaitForVData state, a load to the line can be serviced if it does not overlap with any of the to-be-stored dwords. This allows loads of a partial cache line to proceed in the event that stores to the other half of the same cache line from a previous loop iteration have not completed. This mask is cleared when a VWriteData packet takes the line back to the Dirty state. At this time, any matching requests in the Replay Queue are replayed, allowing them to reset the mask, if appropriate.
Table 2 lists the possible states associated with a line in the Dcache. Since the Dcache is write through, lines are never “dirty.” The Ecache takes care of obtaining write permission and enforcing global write serialization. Thus, the Deache makes no distinction between shared and exclusive data.
The Dcache itself also makes no distinction between valid and pending lines. Lines are marked valid as soon as they are allocated. An associative match against earlier queued requests, however, informs a new request when a valid line has not yet returned from the memory system, in which case the new request is queued behind the earlier request that initiated the Dcache fill.
Global States
Table 3 lists the states associated with memory lines at the directory. The states in the second half of the table are transient, and are used for cache lines involved in outstanding transactions. Those are only needed for entries in the transient directory buffer.
Coherent Message Types
The cache coherence protocol uses a variety of message types, as described below.
Local (Intra-Processor) Messages
Table 4 and Table 5 list the coherence protocol messages used between the P and E chips. In the P-to-E direction, all requests are sent on the same virtual channel except vector write data, which has its own virtual channel. Both of these virtual channels are flow controlled, and may block on VN0. Only a single virtual channel is used for E-to-P packets, and it is not flow controlled.
All read packets include masks indicating which of the swords within a cache line are requested, and transaction IDs (TIDs), which are returned with responses to match them with the corresponding requests. Write packets similarly contain a mask indicating which of the swords within a cache line are to be written to memory. The coherence protocol does not distinguish packets based upon either mask or TID.
Global Messages
Table 6 lists messages sent by the Ecache to the directory. The VN column indicates on which virtual network the packet is sent. The VN2 packets are only sent to a local directory, not across the interconnection network.
Table 7 lists messages sent by the directory to an Ecache.
In Table 11 and Table 13, the notation “C=0” or “C=1” indicates the state of the WriteComplete bit in ReadExclResp and GetResp packets. Ecaches receiving these packets interpret a set WriteComplete bit as a piggybacked WriteComplete packet, and decrement the appropriate outstanding write counter.
Simplified Coherence Protocol
Table 8 shows a simplified version of the cache coherence protocol assuming no race conditions and ignoring intra-processor details. For each basic processor request, the table shows the expected new state of the corresponding line after the request has been satisfied, depending upon the current state of the line.
Processor Requests and Dcache State Transitions
The processor generates both scalar and vector memory requests. Vector requests arc sent directly to the Ecache. They include a hint field that specifies the desired Ecache allocation behavior. Table 9 shows the messages that are sent to the Ecache for different vector memory requests. Vector read responses from E to P are sent as ReadResp messages.
Scalar memory references do not include an allocation hint in the instruction, but acquire a hint from the Hint field of the TLB entry used to translate the virtual address. The hints include allocate exclusive (the typical case), allocate shared (useful for shared read-only data), and no allocate (useful for remote memory used for explicit communication or for data accessed with no temporal locality).
The Dcache itself contains only two states: valid and invalid. Scalar memory requests are initially checked both against the Dcache, and associatively against a queue of previous scalar requests which have not yet been serviced. All requests in this queue are serviced in order to the Deache and the Ecache. It is thus called the forced order queue (FOQ).
If a new request does not match the address of any request in the FOQ, then the request may immediately access the Dcache (on a read hit) or send a message to E (on a read miss or an allocating write miss).
If a request detects a possible match in the FOQ (only a subset of the address is matched), then the request is queued behind the earlier requests to maintain ordering. Write requests are always run through the FOQ, and cannot be dequeued until their write data is present and they are committed. Requests that initiate Dcache fills from the Ecache are additionally placed into the FOQ, pending the response from E.
Table 10 presents a high-level overview of the Dcache operation. It abstracts away the details of the implementation, and does not describe the handling of synch instructions, or the Dcache bypass mode used in the shadow of an Msync instruction. Where the action states that the request is queued, it simply means that the request is run through the FOQ before being sent to the Dcache and/or Ecache.
Ecache State Transitions
Table 11 shows the Ecache state transactions that occur when processing messages from the scalar processor, vector processor or network. The Ecache keeps necessary information to respond to scalar and vector requests once messages return from the directory.
New processor requests may require allocating a new Ecache line (this is indicated in Table 11 by transitioning from the Invalid state to the Pending Req state), which may require evicting an existing line. Table 12 lists the actions necessary to evict a line from the Ecache. Lines that are pending (PendingReq, WaitForVData or WFVDInvalid state) cannot be evicted until they become quiescent.
The action “stall request” means that the request queue could be stalled in place until the request can be serviced and the protocol would still work (that is, there would be no deadlock). For performance reasons, the implementation will use a replay queue, and requests that cannot be serviced will be shunted in to the replay queue, allowing requests behind the stalled request to be serviced. This introduces some subtle issues regarding request ordering.
Any processor request, including non-allocating requests, that misses in the Ecache but finds both ways currently pending will be placed in to the replay queue. This ensures that it will remain ordered with any other previous requests to the same line that may have been placed into the replay queue due to the inability to allocate a new line.
When a pending line becomes quiescent again, due to a VWriteData or directory response packet, the replay queue is immediately interrogated with an associative lookup, and all potentially matching requests (based on a partial address compare) are replayed, in order. This ensures that no new requests from the processor request queue can access a newly quiescent line and pass earlier requests to the same line that were placed in the replay queue.
The replay queue includes logic to optimize replaying of multiple, queued VWrite and VWriteData packets. Due to the decoupled nature of vector writes, a series of allocating vector writes to the same line will likely get placed into the replay queue with the VWrite packets all ahead of the VWriteData packets (rather than interleaved as VWrite, matching VWriteData, VWrite, matching VWriteData, etc.). Since only the matching VWriteData packet can be accepted after a VWrite request (as the line will now be in WaitForVData state), it would be inefficient to play all requests in order from the replay queue, since that would cause the entire queue to be circulated for each VWrite/VWriteData pair. Instead, after processing a VWrite packet, the replay engine switches to replaying just the VWriteData packets. After processing a VWriteData data packet, it switches back to replaying the other types of requests.
Non-allocating vector writes (VWriteNA packets and their corresponding VWriteData packets) do not participate in this switching algorithm, because a VWriteNA will not necessarily cause a transition to WaitForVData state. Thus, after processing a VWriteNA request, the replay logic continues playing “regular” requests, and VWriteData packets belonging to non-allocating vector stores are replayed along with the regular requests. There can be at most one VWriteNA and corresponding VWriteData packet in the replay queue, due to the non-allocating vector write ordering logic.
Directory State Transitions
Table 13 summarizes the directory actions taken as a result of message events.
For all state transitions that return data to the requesting Ecache, and some others, the state transition action requires that a request be made to the memory manager. The directory engine creates a packet header, and then passes it on the memory manager, which accesses memory and typically sends the packet out to the network when it is ready. In some cases, the action requires the memory manager to “check back.” This is done to provide ordering between the messages sent to the Ecaches by the memory manager and those sent by the directory engine.
When the memory manager must “check back,” the directory goes into a transient state (PendMem*) and handles no other VN0 requests for this line until it receives the response from the memory manager. At this time, the directory knows that this, and any previous packets processed by the memory manager for this line will be ordered before any subsequent packets sent by the directory. State transitions for processing memory manager responses are shown in Table 14.
Each transient buffer (TB) entry contains a buffer capable of holding one cache line. This buffer is always marked empty when a TB entry is allocated, and can be filled (and marked full) by a WriteBack or a Supply message. The line buffer may subsequently be used to provide data for a request that had been placed in the replay queue.
A transient buffer entry persists as long as there are still requests for that line in the replay queue. The TB line buffer may be used to satisfy multiple requests from the replay queue, and actually provides a form a read combining if multiple MSPs try to read a line that was previously present in another MSP's cache. Any request that causes the value of the data buffer to become stale, however, will mark the line buffer as empty.
Accesses to MMRs on the local E chips are handled through the directory controller and transient buffer, so as to avoid having to implement VN0 from M to E and NV1 from E to M. The last four lines of Table 12 summarizes the directory actions for handling these E chip MMR accesses. They are handled much the same was as requests coming in to lines in the Exclusive state. The requests are forwarded to the local E chip on VN1, and the responses come back on VN2, where they are sunk by the transient buffer. The responses to the original requestor are then sent back on VN1.
Certain requests made to the memory manager from the directory protocol engine can be marked to “check back” with the directory on their way out to the network. The associated memory line is always placed in one of the PendMem* states when such a request is outstanding. Table 14 lists the state transitions associated with processing the responses from the memory manager.
Directory Request Flow Control
The directory engines are not always capable of processing requests as fast as they arrive. When the directory bandwidth fails to keep up with the rate of incoming messages, the messages will collect in the input buffers, and may eventually cause back pressure on VN0 or VN2 in the interconnection network.
The VN0 network can also be stalled due to unavailability of resources that incoming VN0 requests may need. This is complicated by the fact that up to three requests may be in flight in the directory engine pipeline at one time, making it impossible to stop the pipeline abruptly in response to the state of the request currently being processed. The directory controller deals with this issue in a number of ways. These are briefly described here.
For resources that may fill up, but will eventually drain, the controller maintains a “high water mark” that is below the maximum capacity. When the resource fills to this level, new VN0 packets are held off. VN0 requests already in flight may fill up the remaining slots “above” the high water mark. When the resource frees to some “low water mark”, the VN0 input is re-enabled. An example of this technique is the transient request buffer. Another is the VN 1 response queue coming back from the memory manager.
A request may arrive that cannot be serviced because the corresponding cache line is in a transient state. In this case, the request is sent to a “replay queue”, and a pointer into the replay queue is attached to the corresponding transient request buffer entry. When the transient state is resolved, the request is replayed from the replay queue. If there already exist one or more entries for this line in the replay queue, the request is added to the end of a linked list of such requests.
When a request arrives for a line that is not currently cached, a new directory entry may have to be allocated. The directory is 8-way set associative, so there are eight candidate locations for placing any new entry. Due to its size and associativity, the directories are able to contain entries for all cache lines contained in the four local Ecaches in the quiescent state. Therefore, typically, there will be a free (unused) location available among the eight when creating a new entry. However, it is possible for the caches to temporarily oversubscribe the directory. This can occur when a directory evicts a line, and then re-requests a new line that maps to the same directory index, and the new request arrives at the directory before the eviction notification (Notify, Drop or Writeback packet).
When the directory needs to allocate a new entry, but does not have a free way to use, it must wait for the Notify/Drop/Writeback packet that must be in flight to arrive and free up a way. In this case, the directory controller places the current request in the replay queue and shuts off new incoming VN0 requests. It then creates a special transient buffer entry to point to the request in the replay queue, and allocates a special widget to monitor the associated directory index. When a way becomes available, the widget marks the transient buffer as being ready to service, and it is then handled using the normal replay queue logic. The two VN0 requests in flight at the time VN0 was shut off may possibly have the same problem, so up to three monitoring widgets are available. When all set oversubsciptions have been handled, the VN0 input is re-enabled.
The banks also have four buffers for vector store data. The bank arbiter keeps track of how many words are in each of these buffers. When the number of words in the data buffer satisfies the number of words in the request mask, the request may be removed from the vector store queue.
Since vector store requests are written into both queues, vector store requests can be removed from the load/store queue, can make appropriate M chip requests, and can cause state actions prior to vector store data arriving. This reduces vector store latency if the vector store request did not hit in the cache. If the response has not been returned form the M chip when the request is removed from the vector store queue, the vector store request will be placed in a replay queue and processed again later. Vector store requests cannot pass other store requests in the vector store queue even if the data for the later store request is present.
Advantages
In an embodiment, a cache coherence mechanism supports high bandwidth memory references. Using a highly-banked implementation with multiple coherence engines at each node and on-chip directory caches, the throughput of coherence transactions is greater than convention coherence mechanisms that store their directory information in DRAM. In an embodiment, the cache coherence mechanism provides efficient communication between processors, and data is transferred only once across the machine and is cached only where it is consumed.
In the previous detailed description of exemplary embodiments of the invention, reference was made to the accompanying drawings (where like numbers represent like elements), which form a part hereof, and in which was shown by way of illustration specific exemplary embodiments in which the invention may be practiced. These embodiments were described in sufficient detail to enable those skilled in the art to practice embodiments of the invention, but other embodiments may be utilized and logical, mechanical, electrical, and other changes may be made without departing from the scope of the present invention. The previous detailed description is, therefore, not to be taken in a limiting sense, and the scope of embodiments of the present invention is defined only by the appended claims.
Numerous specific details were set forth to provide a thorough understanding of embodiments of the invention. However, embodiments of the invention may be practiced without these specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail in order not to obscure embodiments of the invention.
This application is a Divisional under 37 C.F.R. 1.53(b) of U.S. patent application Ser. No. 10/368,090 filed Feb. 18, 2003 now U.S. Pat. No. 7,082,500, which is incorporated herein by reference.
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| Number | Date | Country | |
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| Parent | 10368090 | Feb 2003 | US |
| Child | 11456781 | US |
