BRIEF DESCRIPTION OF THE DRAWINGS
The invention itself, as well as a preferred mode of use, further objects, and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
FIG. 1 depicts a high level block diagram of an exemplary integrated circuit (IC) equipped with logic built-in self-test (LBIST) components, as utilized in an embodiment of the present invention;
FIG. 2 is a high level logical flowchart of an exemplary method of LBIST in accordance with one embodiment of the invention; and
FIGS. 3A-3B illustrate an example of a design of an IC, as well as a corresponding set of customized LBIST activation patterns in accordance with one embodiment of the invention.
DETAILED DESCRIPTION OF AN ILLUSTRATIVE EMBODIMENT
The present invention provides a method and system for mitigating the impact of voltage supply variations on logic built-in self-test (LBIST) results. This mitigation is provided by creating a set of optimized LBIST activation patterns, as further described below.
With reference now to FIG. 1, there is depicted a block diagram of an exemplary integrated circuit (IC) 100, with which the present invention may be utilized. IC 100 comprises logic 105, memory 110, input/output (I/O) interface 115, IC bus 120, and LBIST 125. Note that, as is generally the case for IC's, the specific attributes of logic 105 may vary in accordance with the desired functionality of IC 100. As shown in FIG. 1, logic 105, memory 110, I/O interface 115, and LBIST 125 may communicate internally within IC 100 via IC bus 120. In accordance with an embodiment of the invention, LBIST 125 may be utilized by the manufacturer of IC 100 to verify the functionality of logic 105 during the IC manufacturing process. Similarly, in another embodiment, LBIST 125 may be utilized by the manufacturer of IC 100 to verify the functionality of logic 105 at the conclusion of the IC manufacturing process. In yet another embodiment, LBIST 125 may be utilized by a user of IC 100 to verify the functionality of logic 105 during the use of IC 100 in the field.
FIG. 1 depicts I/O interface 115 being utilized to facilitate the communication of IC 100 with external electronic components (not shown). In an alternate embodiment of the invention, IC 100 may not include I/O interface 115. In such an embodiment, logic 105, memory 110, and/or LBIST 125 may communicate directly with external electronic components. Similarly, in another embodiment, IC 100 may not include IC bus 120. In such an embodiment, the internal components of IC 100, such as logic 105, memory 110, and LBIST 125, may be coupled directly to one another.
Within the descriptions of the figures, similar elements are provided similar names and reference numerals as those of the previous figure(s). Where a later figure utilizes the element in a different context or with different functionality, the element is provided a different leading numeral representative of the figure number (e.g., 1xx for FIG. 1 and 2xx for FIG. 2). The specific numerals assigned to the elements are provided solely to aid in the description and not meant to imply any limitations (structural or functional) on the invention.
With reference now to FIG. 2, there is depicted a high level logical flowchart of an exemplary method of LBIST in accordance with one embodiment of the invention. The LBIST process begins at block 200, for example, in response to a user of IC 100 invoking LBIST 125, which preferably performs the remainder of the illustrated steps in an automated manner. At block 205, a set of customized LBIST activation patterns is created. The set of customized LBIST activation patterns comprises a number of patterns equal to the number of functional clock cycles required for bits to propagate through the components within logic 105, specifically a plurality of non-scan latches and the device under test. As utilized herein, device under test refers to any circuit, electronic component, or the like within IC 100. An example of a set of optimized LBIST activation patterns is provided in FIGS. 3A-3B and will be discussed in detail below.
Returning to FIG. 2, at block 210 the first LBIST activation pattern, from among the plurality of customized LBIST activation patterns, propagates from a plurality of scan-able latches of IC 100 through a plurality of non-scan latches within IC 100, thereby reaching the device under test. At block 215, the LBIST activation pattern propagates through the device under test, which creates output data in response to the LBIST activation pattern. At block 220, the output data propagates from the device under test through a plurality of non-scan latches within IC 100, thereby reaching a plurality of scan-able latches within IC 100. At block 225, the output data is captured in a scan-able latch.
A determination is made at block 230 whether or not additional customized LBIST activation patterns exist that have not yet been propagated through logic 105. If additional LBIST activation patterns, from among the plurality of customized LBIST activation patterns created at block 205, exist, then the process returns to block 210 and propagates the next LBIST activation pattern through logic 105. If no additional LBIST activation patterns exist, then the process terminates at block 235. A user may then utilize the output data to determine whether IC 100 contains any delay faults and also to determine the location within IC 100 of any delay faults that may exist, as further described below.
With reference to FIG. 3A, there is illustrated an example of a IC design comprising scan-able latches, non-scan latches, and a device under test in accordance with one embodiment of the invention. As shown in FIG. 3A, IC 100 includes scan-able latch 300, non-scan latch 305, non-scan latch 310, device under test 315, non-scan latch 320, and scan-able latch 325. Although FIG. 3A depicts IC 100 as including three non-scan latches 305, 310, 320, IC 100 may instead contain zero non-scan latches. Similarly, in another embodiment, IC 100 may contain a different number than three of non-scan latches. In order for device under test 315 to be tested by an LBIST activation pattern, the LBIST activation pattern must propagate from scan-able latch 300 to scan-able latch 325 by propagating through three non-scan latches 305, 310, 320 and device under test 315.
Turning now to FIG. 3B, there is illustrated an example of optimizing LBIST activation patterns in accordance with one embodiment of the invention. FIG. 3B comprises original activation pattern 330, half-frequency activation pattern 335, and a plurality of customized patterns 340. The plurality of customized activation patterns 340 comprises four separate activation patterns as follows: P2=SAHAHAHAHS; P3=SHAAHAHAHS; P4=SHAHAAHAHS; and P5=SHAHAHAAHS. As shown in FIG. 3B, LBIST activation patterns may be defined by a plurality of different instruction bits including, but not limited to, the following: H=Hold Data; S=Scan Shift; and A=Perform Functionally. As depicted in FIG. 3A, IC 100 comprises three non-scan latches 305, 310, 320, and one device under test 315. Original activation pattern 330 must thus include four A bits, as depicted in FIG. 3B, in order to test the functionality of each entity on the path between scan-able latch 300 and scan-able latch 325.
Generally, the bits in an LBIST activation pattern may be arranged in a plurality of orders, with H bits being utilized to vary the timing of the performance prompts caused by the A bits in relation to a clock signal. For example, in FIG. 3B, half-frequency activation pattern 335 contains four A bits, each separated by a single H bit. Half-frequency activation pattern thus performs the same functional tests as original activation pattern 330, but at half the frequency of original activation pattern 330 as compared to the clock signal within IC 100. The performance of IC 100 can thus be verified at multiple operational frequencies, according to the combination of bits used within an LBIST activation pattern.
Both S and A bits cause some nodes within IC 100 to switch states. State changes cause current to flow, which in turn leads to variations in the supply voltage of devices within IC 100. These supply voltage variations cause circuit performance to speed up in when supply voltage is high and/or to slow down when supply voltage is low. Thus, if device under test 315 is susceptible to a speed fault and is tested during a clock cycle when the supply voltage at device under test 315 is high, then device under test 315 may erroneously appear to be faster than a properly manufactured device. Similarly, if device under test 315 is susceptible to a speed fault and is tested during a clock cycle when the supply voltage at device under test 315 is low, then device under test 315 may erroneously appear to be slower than a properly manufactured device. The speed faults described above may be undetectable by conventional LBIST methods. The present invention thus studies the performance of each component in the path between scan-able latch 300 and scan-able latch 325 independently, via the utilization of the plurality of customized activation patterns 340, each of which corresponds to a specific component in the path between scan-able latch 300 and scan-able latch 325.
According to the invention, as applied to IC 100 or FIG. 3A, activation pattern P2 tests the launch from scan-able latch 300 to non-scan latch 305. Activation pattern P3 tests the path from non-scan latch 305 to non-scan latch 310. Activation pattern P4 tests the path from non-scan latch 310 to non-scan latch 320, which includes device under test 315. Activation pattern P5 tests the path from non-scan latch 320 to scan-able latch 325. If device under test 315 does not contain a delay fault, then each of the plurality of customized activation patterns 340 produces the same output data as original activation pattern 330 (i.e. P1 Output=P2 Output=P3 Output=P4 Output=P5 Output).
Each of the plurality of customized activation patterns 340 has a different characteristic voltage versus frequency relationship, which represents the first failure for a nominally manufactured IC. This voltage versus frequency relationship may be characterized by the expression Vmin/Fmax. The occurrence of delay faults causes a deviation from this characteristic Vmin/Fmax. Furthermore, the Vmin/Fmax of each of the plurality of customized activation patterns 340 may serve as a measure of both the structure of the devices present within IC 100 and any variations in supply voltage that may occur during LBIST. Consequently, if device under test does contain a delay fault, the origin of the delay fault may be determined by comparing the Vmin/Fmax observed during LBIST to the characteristic Vmin/Fmax of device under test 315. The present invention thus utilizes the characteristic Vmin/Fmax of devices within IC 100 to mitigate the impact of voltage supply variations between test cycles, which may otherwise occur in present LBIST methods.
It is understood that the use herein of specific names are for example only and not meant to imply any limitations on the invention. The invention may thus be implemented with different nomenclature/terminology and associated functionality utilized to describe the above devices/utility, etc., without limitation.
While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
Patent Application
20080092006
