Power distribution; Power saving

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CPC
G01R31/318575

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GPHYSICS G01Measuring instruments G01RMEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES G01R31/00Arrangements for testing electric properties Arrangements for locating electric faults Arrangements for electrical testing characterised by what is being tested not provided for elsewhere

Current Industry

G01R31/318575Power distribution; Power saving

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Method of finding optimized analog measurement hardware settings as...
- Patent number 12,140,630
- Issue date Nov 12, 2024
- Rohde & Schwarz GmbH & Co. KG
- Darren Tipton
- G01 - MEASURING TESTING
Information Patent Grant
Test access port architecture to facilitate multiple testing modes
- Patent number 12,057,183
- Issue date Aug 6, 2024
- Micron Technology, Inc.
- Michael Richard Spica
- G11 - INFORMATION STORAGE
Information Patent Grant
Power consumption measurement assembly and method, and chip power c...
- Patent number 12,032,022
- Issue date Jul 9, 2024
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Xinwang Chen
- G01 - MEASURING TESTING
Information Patent Grant
Power-sensitive scan-chain testing
- Patent number 12,025,661
- Issue date Jul 2, 2024
- MARVELL ASIA PTE. LTD.
- Balaji Upputuri
- G01 - MEASURING TESTING
Information Patent Grant
Power profiling in an integrated circuit having a current sensing c...
- Patent number 11,808,804
- Issue date Nov 7, 2023
- NXP USA, INC.
- Antonio Mauricio Brochi
- G01 - MEASURING TESTING
Information Patent Grant
Wafer scale testing using a 2 signal JTAG interface
- Patent number 11,782,091
- Issue date Oct 10, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic test pattern generation circuitry in multi power domain s...
- Patent number 11,680,982
- Issue date Jun 20, 2023
- STMICROELECTRONICS INTERNATIONAL N.V.
- Venkata Narayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Wafer scale testing using a 2 signal JTAG interface
- Patent number 11,561,258
- Issue date Jan 24, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase controlled codec block scan of a partitioned circuit device
- Patent number 11,519,964
- Issue date Dec 6, 2022
- Texas Instruments Incorporated
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Grant
Isolation logic test circuit and associated test method
- Patent number 11,442,108
- Issue date Sep 13, 2022
- STMICROELECTRONICS INTERNATIONAL N.V.
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING
Information Patent Grant
Power-aware scan partitioning
- Patent number 11,386,253
- Issue date Jul 12, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd
- Ankita Patidar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test access port architecture to facilitate multiple testing modes
- Patent number 11,250,928
- Issue date Feb 15, 2022
- Micron Technology, Inc.
- Michael Richard Spica
- G01 - MEASURING TESTING
Information Patent Grant
Wafer scale testing using a 2 signal JTAG interface
- Patent number 11,243,253
- Issue date Feb 8, 2022
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Augmenting an integrated circuit (IC) design simulation model to im...
- Patent number 11,231,462
- Issue date Jan 25, 2022
- Synopsys, Inc.
- Adam D. Cron
- G01 - MEASURING TESTING
Information Patent Grant
Method for reducing power consumption in scannable flip-flops witho...
- Patent number 11,092,649
- Issue date Aug 17, 2021
- Samsung Electronics Co., Ltd.
- Matthew Berzins
- G01 - MEASURING TESTING
Information Patent Grant
Phase controlled codec block scan of a partitioned circuit device
- Patent number 11,073,557
- Issue date Jul 27, 2021
- Texas Instruments Incorporated
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Grant
Systems on chips, integrated circuits, and operating methods of the...
- Patent number 10,990,473
- Issue date Apr 27, 2021
- Samsung Electronics Co., Ltd.
- Suh-ho Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Built-in self-test in a data processing apparatus
- Patent number 10,908,214
- Issue date Feb 2, 2021
- ARM Limited
- Joseph Samuel Herd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Channel circuitry, tap linking module, scan tap, debug tap domains
- Patent number 10,901,033
- Issue date Jan 26, 2021
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power saving scannable latch output driver
- Patent number 10,890,623
- Issue date Jan 12, 2021
- International Business Machines Corporation
- William Huott
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Test access port architecture to facilitate multiple testing modes
- Patent number 10,867,689
- Issue date Dec 15, 2020
- Micron Technology, Inc.
- Michael Richard Spica
- G01 - MEASURING TESTING
Information Patent Grant
Dynamically power noise adaptive automatic test pattern generation
- Patent number 10,816,599
- Issue date Oct 27, 2020
- International Business Machines Corporation
- Steven M. Douskey
- G01 - MEASURING TESTING
Information Patent Grant
Low-power shift with clock staggering
- Patent number 10,775,435
- Issue date Sep 15, 2020
- Cadence Design Systems, Inc.
- Christos Papameletis
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for at-speed scan shift frequency test optimiz...
- Patent number 10,746,795
- Issue date Aug 18, 2020
- NXP USA, INC.
- Sergey Sofer
- G01 - MEASURING TESTING
Information Patent Grant
Regulator control during scan shift and capture cycles
- Patent number 10,712,390
- Issue date Jul 14, 2020
- Silicon Laboratories Inc.
- Vivek Sarda
- G01 - MEASURING TESTING
Information Patent Grant
Power-aware scan partitioning
- Patent number 10,685,157
- Issue date Jun 16, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd
- Ankita Patidar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
2D compression-based low power ATPG
- Patent number 10,551,435
- Issue date Feb 4, 2020
- Cadence Design Systems, Inc.
- Nitin Parimi
- G01 - MEASURING TESTING
Information Patent Grant
Wafer with dio bidirectional lead, n dies, domains, clock leads
- Patent number 10,551,438
- Issue date Feb 4, 2020
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for identifying a fault at a device output and system therefor
- Patent number 10,436,839
- Issue date Oct 8, 2019
- NXP B.V.
- Robert Meyer
- G01 - MEASURING TESTING
Information Patent Grant
Semiconductor integrated circuit and semiconductor integrated circu...
- Patent number 10,401,430
- Issue date Sep 3, 2019
- Kabushiki Kaisha Toshiba
- Tomoyuki Maekawa
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHOD OF FINDING OPTIMIZED ANALOG MEASUREMENT HARDWARE SETTINGS AS...
- Publication number 20230184832
- Publication date Jun 15, 2023
- ROHDE & SCHWARZ GMBH & CO. KG
- Darren Tipton
- G01 - MEASURING TESTING
Information Patent Application
WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE
- Publication number 20230160959
- Publication date May 25, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER PROFILING IN AN INTEGRATED CIRCUIT HAVING A CURRENT SENSING C...
- Publication number 20220187358
- Publication date Jun 16, 2022
- NXP USA, Inc.
- Antonio Mauricio Brochi
- G01 - MEASURING TESTING
Information Patent Application
WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE
- Publication number 20220113351
- Publication date Apr 14, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER CONSUMPTION MEASUREMENT ASSEMBLY AND METHOD, AND CHIP POWER C...
- Publication number 20220099741
- Publication date Mar 31, 2022
- CHANGXIN MEMORY TECHNOLOGIES, INC
- Xinwang CHEN
- G01 - MEASURING TESTING
Information Patent Application
PHASE CONTROLLED CODEC BLOCK SCAN OF A PARTITIONED CIRCUIT DEVICE
- Publication number 20210311121
- Publication date Oct 7, 2021
- TEXAS INSTRUMENTS INCORPORATED
- PRAKASH NARAYANAN
- G01 - MEASURING TESTING
Information Patent Application
WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE
- Publication number 20210088584
- Publication date Mar 25, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PHASE CONTROLLED CODEC BLOCK SCAN OF A PARTITIONED CIRCUIT DEVICE
- Publication number 20200355744
- Publication date Nov 12, 2020
- TEXAS INSTRUMENTS INCORPORATED
- PRAKASH NARAYANAN
- G01 - MEASURING TESTING
Information Patent Application
POWER-AWARE SCAN PARTITIONING
- Publication number 20200311329
- Publication date Oct 1, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ankita Patidar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NOVEL METHOD FOR REDUCING POWER CONSUMPTION IN SCANNABLE FLIP-FLOPS...
- Publication number 20200292617
- Publication date Sep 17, 2020
- Samsung Electronics Co., Ltd.
- Matthew BERZINS
- G01 - MEASURING TESTING
Information Patent Application
BUILT-IN SELF-TEST IN A DATA PROCESSING APPARATUS
- Publication number 20200278395
- Publication date Sep 3, 2020
- ARM Limited
- Joseph Samuel HERD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE
- Publication number 20200124667
- Publication date Apr 23, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR IDENTIFYING A FAULT AT A DEVICE OUTPUT AND SYSTEM THEREFOR
- Publication number 20190120897
- Publication date Apr 25, 2019
- NXP B.V.
- Robert Meyer
- G01 - MEASURING TESTING
Information Patent Application
WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE
- Publication number 20190120899
- Publication date Apr 25, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
REGULATOR CONTROL DURING SCAN SHIFT AND CAPTURE CYCLES
- Publication number 20190094302
- Publication date Mar 28, 2019
- Silicon Laboratories Inc.
- Vivek Sarda
- G05 - CONTROLLING REGULATING
Information Patent Application
POWER-AWARE SCAN PARTITIONING
- Publication number 20190094303
- Publication date Mar 28, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ankita Patidar
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION IN SCANNABLE CIRCUIT
- Publication number 20180340979
- Publication date Nov 29, 2018
- Samsung Electronics Co., Ltd.
- Matthew BERZINS
- G01 - MEASURING TESTING
Information Patent Application
WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE
- Publication number 20180321307
- Publication date Nov 8, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE
- Publication number 20180128875
- Publication date May 10, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, AND SELF-DIAGNOSIS METHOD...
- Publication number 20180003771
- Publication date Jan 4, 2018
- Renesas Electronics Corporation
- Takuro NISHIKAWA
- G01 - MEASURING TESTING
Information Patent Application
SOLID STATE SWITCH POWER EMULATOR
- Publication number 20170350941
- Publication date Dec 7, 2017
- U.S. ARMY RESEARCH LABORATORY ATTN: RDRL-LOC-I
- Richard L. Thomas
- G01 - MEASURING TESTING
Information Patent Application
ADAPTING SCAN-BIST ARCHITECTURES FOR LOW POWER OPERATION
- Publication number 20170269158
- Publication date Sep 21, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
ADAPTING SCAN ARCHITECTURES FOR LOW POWER OPERATION
- Publication number 20170248656
- Publication date Aug 31, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
A METHOD AND APPARATUS FOR SCAN CHAIN DATA MANAGEMENT
- Publication number 20150331047
- Publication date Nov 19, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Michael Priel
- G01 - MEASURING TESTING
Information Patent Application
SCAN TEST SYSTEM
- Publication number 20150247899
- Publication date Sep 3, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Sergey Sofer
- G01 - MEASURING TESTING
Information Patent Application
Fault-Driven Scan Chain Configuration For Test-Per-Clock
- Publication number 20140372820
- Publication date Dec 18, 2014
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
Scan Chain Stitching For Test-Per-Clock
- Publication number 20140372821
- Publication date Dec 18, 2014
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
Test-Per-Clock Based On Dynamically-Partitioned Reconfigurable Scan...
- Publication number 20140372818
- Publication date Dec 18, 2014
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
Logic Built-In Self-Test with High Test Coverage and Low Switching...
- Publication number 20140365840
- Publication date Dec 11, 2014
- Xijiang Lin
- G01 - MEASURING TESTING
Information Patent Application
CORE CIRCUIT TEST ARCHITECTURE
- Publication number 20140359388
- Publication date Dec 4, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING

Power distribution; Power saving

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Method of finding optimized analog measurement hardware settings as...

Test access port architecture to facilitate multiple testing modes

Power consumption measurement assembly and method, and chip power c...

Power-sensitive scan-chain testing

Power profiling in an integrated circuit having a current sensing c...

Wafer scale testing using a 2 signal JTAG interface

Automatic test pattern generation circuitry in multi power domain s...

Wafer scale testing using a 2 signal JTAG interface

Phase controlled codec block scan of a partitioned circuit device

Isolation logic test circuit and associated test method

Power-aware scan partitioning

Test access port architecture to facilitate multiple testing modes

Wafer scale testing using a 2 signal JTAG interface

Augmenting an integrated circuit (IC) design simulation model to im...

Method for reducing power consumption in scannable flip-flops witho...

Phase controlled codec block scan of a partitioned circuit device

Systems on chips, integrated circuits, and operating methods of the...

Built-in self-test in a data processing apparatus

Channel circuitry, tap linking module, scan tap, debug tap domains

Power saving scannable latch output driver

Test access port architecture to facilitate multiple testing modes

Dynamically power noise adaptive automatic test pattern generation

Low-power shift with clock staggering

Method and apparatus for at-speed scan shift frequency test optimiz...

Regulator control during scan shift and capture cycles

Power-aware scan partitioning

2D compression-based low power ATPG

Wafer with dio bidirectional lead, n dies, domains, clock leads

Method for identifying a fault at a device output and system therefor

Semiconductor integrated circuit and semiconductor integrated circu...

Patents Applicationslast 30 patents

METHOD OF FINDING OPTIMIZED ANALOG MEASUREMENT HARDWARE SETTINGS AS...

WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE

POWER PROFILING IN AN INTEGRATED CIRCUIT HAVING A CURRENT SENSING C...

WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE

POWER CONSUMPTION MEASUREMENT ASSEMBLY AND METHOD, AND CHIP POWER C...

PHASE CONTROLLED CODEC BLOCK SCAN OF A PARTITIONED CIRCUIT DEVICE

WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE

PHASE CONTROLLED CODEC BLOCK SCAN OF A PARTITIONED CIRCUIT DEVICE

POWER-AWARE SCAN PARTITIONING

NOVEL METHOD FOR REDUCING POWER CONSUMPTION IN SCANNABLE FLIP-FLOPS...

BUILT-IN SELF-TEST IN A DATA PROCESSING APPARATUS

WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE

METHOD FOR IDENTIFYING A FAULT AT A DEVICE OUTPUT AND SYSTEM THEREFOR

WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE

REGULATOR CONTROL DURING SCAN SHIFT AND CAPTURE CYCLES

POWER-AWARE SCAN PARTITIONING

SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION IN SCANNABLE CIRCUIT

WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE

WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE

SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, AND SELF-DIAGNOSIS METHOD...

SOLID STATE SWITCH POWER EMULATOR

ADAPTING SCAN-BIST ARCHITECTURES FOR LOW POWER OPERATION

ADAPTING SCAN ARCHITECTURES FOR LOW POWER OPERATION

A METHOD AND APPARATUS FOR SCAN CHAIN DATA MANAGEMENT

SCAN TEST SYSTEM

Fault-Driven Scan Chain Configuration For Test-Per-Clock

Scan Chain Stitching For Test-Per-Clock

Test-Per-Clock Based On Dynamically-Partitioned Reconfigurable Scan...

Logic Built-In Self-Test with High Test Coverage and Low Switching...

CORE CIRCUIT TEST ARCHITECTURE