Patent Application
20150137898
This application claims priority to European Patent Application No. 13192650.3 filed on Nov. 13, 2013, the contents of which are hereby incorporated by reference.
The present disclosure is generally related to the field of oscillators for use in e.g. wireless low-power applications.
Oscillators used in phase-locked-loops (PLLs) form an important part of transceivers encountered in the field of wireless low power applications. Ultra-low-power (ULP) transceivers enable short-range networks of autonomous sensor nodes for wireless personal area networks (WPANs), wireless body area networks (WBANs), Internet-of-things etc. A Phase Locked Loop (PLL) forms an essential block of such transceivers. Radio frequency (RF) PLLs for frequency synthesis and modulation however consume a significant share of the total transceiver power. Hence, in order to realize ULP WPAN radios the availability of highly power efficient PLLs, preferably in the sub-mW range, is highly desirable.
All-digital PLLs have been proposed to achieve savings in both area cost and power dissipation. Compared to analog PLLs, all-digital PLLs (ADPLLs) are preferred in nanoscale CMOS as they dramatically reduce the chip area and further offer benefits of programmability, capability of extensive self-calibrations and easy portability. In this way power-efficient wireless applications, like e.g. biomedical applications and wireless sensor networks, can be envisaged.
An LC-tank based oscillator is typically used within a phase-locked-loop (PLL) for frequency synthesis in wireless applications. The oscillation occurs at the resonance frequency of the LC tank. This frequency is corrected to the required value by a negative feedback configuration. As illustrated in
Digital inverters can act as power efficient buffers. They are constructed using at least one pair of complementary transistors, i.e. a p-channel and an n-channel transistor with their gate terminals and their drain terminals connected together. Process, voltage or temperature variations (commonly referred to as PVT variations) affect the circuit characteristics and hence its performance and power efficiency. Process variation is a term used to refer to a variation of fabrication parameters (doping concentration, length, width of transistor etc.) when designing an integrated circuit (i.e. a functional circuit). Process corners represent the extremes of these parameter variations within which the circuit must function correctly. A p-channel and n-channel transistor fabricated at these process corners may run slower or faster than specified and at lower or higher temperatures and voltages.
Digital inverter quality is measured using the Voltage Transfer Curve (VTC), which plots the inverter output voltage as a function of its input voltage. From such a graph, inverter parameters including noise tolerance, gain and operating logic levels can be obtained. Ideally, the VTC appears as an inverted step function, indicating precise and abrupt switching between an ‘on’ and an ‘off’ state. In real inverters, however, a gradual transition region exists. The VTC indicates that for a low input voltage, the circuit outputs a high voltage, whereas for high input voltage the output tapers off towards the low level. The slope of this transition region is a measure of quality: steep (close to infinity) slopes yield precise switching. The tolerance to noise can be measured by comparing the minimum input to the maximum output for each region of operation (on/off state).
To enable operation with low-input swings, the inverter should be biased at the point where the inverter gain is the highest (maximum sensitivity point Vm), see
As the DC level of the oscillator output is prone to process, voltage and temperature variations, this DC level may vary. Conventionally, a self-biased inverter is used as an oscillator buffer, which is AC-coupled to the oscillator output by means of a large coupling capacitor Cbias.
However, the passive components used in this approach do not scale down with advancements in semiconductor technology. Hence, such a solution occupies a large area leading to high system costs. Moreover, the large resistor Rbias used for biasing is a source of significant thermal noise, which couples into the oscillator output, thereby degrading its phase noise performance. Thus the oscillator needs to expend more current to maintain the required phase noise levels. Furthermore, the large decoupling capacitor introduces significant parasitics, thereby loading the output node of the oscillator. This increases the power consumption and reduces the maximum operable frequency of the oscillator. Thus a self-biased inverter used as a buffering circuit poses a serious challenge in scaling down the power consumption and area.
In the paper “A 915 MHz, Ultra-Low Power 2-Tone Transceiver With Enhanced Interference Resilience” (X. Huang et al., IEEE Journal Solid State Circuits, vol. 47, no. 12, December 2012, pp. 3197-3207) an AC-coupled LO buffer is used to isolate the low-swing oscillator from the power amplifier. It uses passive components and hence does not scale with technology. Also, it needs additional biasing, adding to the total power consumption.
Consequently, there is a need for an oscillator buffer wherein the above-mentioned drawbacks of the prior art solutions are avoided or overcome.
It is an object of embodiments of the present disclosure to provide for an inverter based oscillator buffer wherein the use of passive components is avoided. It is a further object to provide a method for calibrating the oscillator buffer.
The above objective is accomplished by the solution according to the present disclosure.
A first aspect the disclosure relates to a buffering circuit for buffering an oscillator signal, the buffering circuit including a plurality of PMOS and NMOS transistor pairs connected in parallel, each pair having connected gate terminals and connected drain terminals forming an inverter circuit, each pair arranged for receiving via a direct coupling an sinusoidal oscillator signal with a variable DC level at its gate terminal, and each pair further being connected with an additional PMOS and NMOS transistor. The buffering circuit further includes a control circuit arranged for receiving an output signal output by the inverter circuits, for deriving information on the DC level of the output signal, and for adjusting a voltage transfer curve expressing a relationship between a voltage at the input and output of the buffering circuit to match the variable DC level, by switching on or off the additional PMOS and NMOS transistors based on the derived information.
The proposed solution indeed allows for avoiding passive components. A DC coupling between the oscillator and the buffering circuit is possible. Variations in the DC level can be dealt with by providing a control circuit that receives at its input the buffer output signal and determines an indication of its DC level. Next the voltage transfer curve at the buffer input can be adjusted by appropriately switching the additional transistors in the circuit such that the DC-level at the buffer input and the maximum sensitivity point on the VTC are at the same voltage level.
In an embodiment the control circuit is arranged for deriving the information on the DC level by averaging the output signal.
In an embodiment the inverter circuit is implemented in CMOS.
In a potentially advantageous embodiment the transistor pairs of the plurality are sized such that they form binary weights. The gate widths of transistors belonging to different pairs then have a ratio that is a power of 2.
In another embodiment, the control circuit is arranged for adjusting the voltage transfer curve of the inverter circuit by generating code words and hence its output DC-level.
The disclosure also relates to a device comprising an oscillator and a buffering circuit as previously described.
Potentially advantageously, the oscillator is a voltage controlled oscillator or a digitally controlled oscillator.
In one embodiment the device comprises a further buffer arranged for receiving the output signal of the preceding buffer circuit. This is especially useful when a large load is applied, as it allows reducing the size of the preceding buffer circuit.
In an embodiment the oscillator of the device is part of a phase-locked loop.
In another aspect, the disclosure relates to a method for calibrating a buffering circuit, comprising applying via a direct coupling a sinusoidal oscillator signal with variable DC level to a circuit comprising a plurality of PMOS and NMOS transistor pairs connected in parallel, each pair having connected gate terminals and connected drain terminals forming an inverter circuit, each pair arranged for receiving the oscillator signal at its gate terminal, and each pair further being connected with an additional PMOS and NMOS transistor. The method also includes deriving information on the DC level of an output signal output by the inverter circuits, and adjusting a voltage transfer curve expressing a relationship between a voltage at the input and output of the buffering circuit to match the variable DC level, by switching on or off the additional PMOS and NMOS transistors based on the derived information.
For purposes of summarizing the disclosure and the advantages achieved over the prior art, certain objects and advantages of the disclosure have been described herein above. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment of the disclosure. Thus, for example, those skilled in the art will recognize that the disclosure may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objects or advantages as may be taught or suggested herein.
The above and other aspects of the disclosure will be apparent from and elucidated with reference to the embodiment(s) described hereinafter.
The present disclosure will now be described further, by way of example, with reference to the accompanying drawings, wherein like reference numerals refer to like elements in the various figures.
The present disclosure will be described with respect to particular embodiments and with reference to certain drawings but the disclosure is not limited thereto but only by the claims.
Furthermore, the terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequence, either temporally, spatially, in ranking or in any other manner. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the disclosure described herein are capable of operation in other sequences than described or illustrated herein.
It is to be noticed that the term “comprising”, used in the claims, should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. It is thus to be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the scope of the expression “a device comprising means A and B” should not be limited to devices consisting only of components A and B. It means that with respect to the present disclosure, the only relevant components of the device are A and B.
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment, but may. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner, as would be apparent to one of ordinary skill in the art from this disclosure, in one or more embodiments.
Similarly it should be appreciated that in the description of exemplary embodiments of the disclosure, various features of the disclosure are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed disclosure requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this disclosure.
Furthermore, while some embodiments described herein include some but not other features included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the disclosure, and form different embodiments, as would be understood by those in the art. For example, in the following claims, any of the claimed embodiments can be used in any combination.
It should be noted that the use of particular terminology when describing certain features or aspects of the disclosure should not be taken to imply that the terminology is being re-defined herein to be restricted to include any specific characteristics of the features or aspects of the disclosure with which that terminology is associated.
In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the disclosure may be practiced without these specific details. In other instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Hereto, in the context of the present disclosure an AC coupled circuit refers to a circuit with the output of a preceding circuit connected to a succeeding circuit by means of a decoupling capacitor, thereby blocking the DC signal while allowing the AC signal to pass through. A DC coupled circuit refers to a circuit where two consecutive circuits are connected directly without any decoupling capacitor, thereby allowing both AC and DC signals to pass through.
Also in the context of the present disclosure, a DC level of a sinusoidal signal refers to the average value of the signal in one cycle. Stated otherwise, it is the level about which the sinusoidal wave oscillates.
In the present disclosure bulky passive components are avoided by providing a DC coupling of the oscillator output to the buffer. Depending on the input DC level (DC level of the sinusoidal signal from the oscillator), the VTC of the buffer is shifted to ensure operation at maximum sensitivity across process, voltage and temperature (PVT) variations. In this way, an area efficient low-power buffer is realized which can operate with low input swings over PVT variations. The oscillator used in this disclosure can be e.g. a Voltage Controlled Oscillator (VCO), a Digitally Controlled Oscillator (DCO) or an oscillator operating in an open loop configuration. Advantageously the oscillator may be part of a PLL.
In the proposed solution decoupling the capacitor Cbias and the biasing resistor Rbias is avoided and the oscillator output is connected directly to the buffer. Consequently, the variation in the DC level of the oscillator output affects the operation of the buffer. Thus, to ensure the oscillator buffer always operates at its maximum sensitivity point, it is proposed to shift its VTC so that the DC level of the oscillator output corresponds to the maximum sensitivity point of the buffer. A more detailed explanation is provided below.
As explained previously, operation at the maximum sensitivity point Vm of the inverter results in the maximum possible gain. Thus, a low-swing input signal can be boosted to rail-to-rail levels, i.e. VDD to GND. Operating at the maximum sensitivity point of the buffer also results in a buffer output with 50% duty cycle for a sinusoidal input, as the input sinusoidal signal has equal duration for voltages above and below its DC level, hence the output signal also has a 50% duty cycle. However, any input voltage Vin greater than or lower than the input voltage value corresponding to maximum sensitivity point Vm results in an output voltage Vout with (i) a low swing (amplitude) and (ii) a lower or a higher duty cycle, as the inverter does not operate in its linear region. The duty cycle of the output voltage will increase or decrease depending on whether the input DC level is smaller than or greater than the voltage corresponding to the maximum sensitivity point Vm. For example, a very low output swing is observed for input voltage Vin having an average value close to zero or VDD. In case the DC-level of Vin is close to VDD, the duty cycle of the output voltage is small, nearly 0. Similarly, if the DC-level of Vin is close to zero, the duty cycle of the output voltage is, nearly 100%. The information on the duty cycle of the buffer output voltage is used for calibrating (shifting) the buffer's VTC along the X-axis to the desired position across PVT variations, assuring compensation for any variations in the input DC level of the buffer. Any calibration circuit that can monitor and detect deviation in a duty cycle of a signal may be used for this purpose.
In the solution of the present disclosure a DC-coupled oscillator buffer is presented. The DC level at the buffer input is determined by the oscillator's output DC level. The oscillator can be, for example, a voltage controlled oscillator (VCO) or a digitally controlled oscillator (DCO). The buffer's VTC is shifted along the X-axis to ensure its maximum sensitivity point tracks the DC level of the oscillator output, which changes due to process, voltage and temperature variations. The disclosure further presents a technique for tuning the DC coupled oscillator buffer. A feedback loop is provided comprising a control circuit adapted for adjusting the DC level of the buffer output by changing the voltage transfer curve of the buffer. Thus, the proposed solution aims at tuning the VTC of the inverter to match the maximum sensitivity point with the DC level of the VCO/DCO output.
A control circuit 4 is provided for shifting the buffer VTC to the required level. One possible way to realize this shift can be to detect the duty cycle of the buffer output by averaging the waveform to obtain the DC level. If for example the output voltage has an average value (i.e. DC level) greater than VDD/2, this indicates that its duty cycle is greater than 50% (the duration of the positive waveform is longer than the negative waveform). This translates to an input DC level lower than the input voltage corresponding to the maximum sensitivity point Vm of the buffer. Hence, the control circuitry turns on more NMOS transistors to shift the VTC to the left, so that a 50% duty cycle of Vout is achieved (i.e. the output voltage has an average value equal to VDD/2). Similarly, if the average is less than VDD/2, more PMOS transistors are enabled to ensure an output voltage Vout with 50% duty cycle.
The number of transistors and their gate width should be sized accordingly to account for PVT variations and the load to be driven. The variation in DC level of the oscillator output is estimated via circuit simulations across process corners representing the extremes of the parameter variations (such as doping concentrations, length, width etc.). The extremes represent the case when all the process variations either deviate towards a transistor with reduced currents (slow corner) or increased currents (fast corner). The number and width of the switchable PMOS and NMOS transistors is then chosen to cover this variation with an extra margin (e.g. 5%). For example, in
The subsequent buffer 22 in
Since the proposed structure avoids any passive components, it occupies a very small area and is aligned with the technology scaling. Moreover, the power consumption is reduced by avoiding driving the large parasitics associated with the decoupling capacitors. Also, noise feed-through from the bias resistor is absent, thereby allowing lower current consumption for a given phase noise requirement compared to the conventional approach.
The proposed buffer 21 requires a minimum setup of one default NMOS-PMOS transistor pair and an additional switchable NMOS-PMOS pair whose source terminals are connected to GND and VDD, respectively, via switches. The actual number of switchable NMOS-PMOS pairs required is determined by the range of VTC shift that is needed.
While the present disclosure has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive. The foregoing description details certain embodiments of the disclosure. It will be appreciated, however, that no matter how detailed the foregoing appears in text, the disclosure may be practiced in many ways. The disclosure is not limited to the disclosed embodiments.
Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed disclosure, from a study of the drawings, the disclosure and the appended claims. In the claims, the word “comprising” does not exclude other elements or steps, and the indefinite article “a” or “an” does not exclude a plurality. A single processor or other unit may fulfil the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. A computer program may be stored/distributed on a suitable medium, such as an optical storage medium or a solid-state medium supplied together with or as part of other hardware, but may also be distributed in other forms, such as via the Internet or other wired or wireless telecommunication systems. Any reference signs in the claims should not be construed as limiting the scope.
| Number | Date | Country | Kind |
|---|---|---|---|
| 13192650.3 | Nov 2013 | EP | regional |
