Claims
- 1. An external terminal for an IC package, comprising:
- a base plate;
- a plated base structure formed over the surface of said base plate and comprising at least three plated and annealed base layers, the total thickness of said plated base layers being at least 3 .mu.m, each of said plated base layers having a dense recrystallized grain structure produced by an annealing process that promotes the growth of grains of the plated base layers, said annealing process being conducted individually on each of said at least three plated base layers after its formation; and
- a surface layer formed over an uppermost one of said plated base layers.
- 2. The outer lead according to claim 1, wherein said plated base layers are formed of nickel (Ni) or a nickel alloy.
- 3. The outer lead according to claim 1, wherein said surface layer is formed of gold (Au) or a gold alloy.
- 4. The outer lead according to claim 1, wherein said base plate is formed of a material having a thermal expansion coefficient substantially equal to that of said package of said semiconductor IC package.
- 5. The outer lead according to claim 4, wherein said package is formed of alumina and said base plate is formed of a Fe/Ni alloy.
- 6. The outer lead according to claim 1, wherein a package type of said semiconductor IC package is one of a flat package type and a pin grid array type.
- 7. An external terminal for an IC package, comprising:
- a base plate;
- a plated base structure formed over the surface of said base plate and comprising at least three plated and annealed base layers of nickel (Ni) or a nickel alloy, the total thickness of said plated base layers being at least 3 .mu.m, each of said plated base layers having a dense recrystallized grain structure produced by an annealing process that promotes growth of grains of the plated base layers, said annealing process being conducted individually on each of said at least three plated base layers after its formation; and
- a surface layer of gold (Au) or a gold alloy, formed over an uppermost one of said plated base layers.
- 8. The outer lead according to claim 7, wherein said base plate is formed of a material having a thermal expansion coefficient substantially equal to that of said package of said semiconductor IC package.
- 9. The outer lead according to claim 7, wherein said package is formed of alumina, and said base plate is formed of a Fe/Ni alloy.
- 10. The outer lead according to claim 7, wherein a package type of said semiconductor IC package is one of a flat package type and a pin grid array type.
Priority Claims (1)
Number |
Date |
Country |
Kind |
5-243833 |
Sep 1993 |
JPX |
|
Parent Case Info
This application is a continuation of application Ser. No. 08/236,195 filed May 4, 1994, now abandoned.
US Referenced Citations (1)
Number |
Name |
Date |
Kind |
5010388 |
Sasame et al. |
Apr 1991 |
|
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Continuations (1)
|
Number |
Date |
Country |
Parent |
236195 |
May 1994 |
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