Patent Application
20250226014
A memory bank is a unit of data storage in electronics, which is hardware-dependent. In a computer, for example, the memory bank may be determined by the physical organization of the hardware memory. In a typical static random-access memory (static RAM or SRAM), a bank may include multiple rows and columns of storage units, and is usually spread out across circuits. An SRAM is a type of semiconductor memory that uses bi-stable latching circuitry (e.g., a flip-flop or a portion thereof) to store each bit. In a single read or write operation, generally only one bank is accessed. Certain types of memory may implement a register file.
A common feature of most modern memories is the use of a hierarchical bitline arrangement in which, instead of a single bitline that runs the complete height of a column of memory cells and connects to each cell in the column, a multi-level structure is used. Effectively, a single bitline is broken up into multiple “local bitlines”, each of which connects to the memory cells in a part of the column. A “global bitline” also runs the height of the column, and is connected to the local bitlines via switches. “Global bitline” refers to a bitline that spans groups of memory cells each with local bitlines. “Memory cell” refers to any circuit that stores a binary value. The memory controller connects to the global bitline, and not directly to the local bitlines. “Memory controller” refers to logic that generates control signals for reading, writing, and managing memory cells. “Logic” refers to machine memory circuits and non-transitory machine readable media comprising machine-executable instructions (software and firmware), and/or circuitry (hardware) which by way of its material and/or material-energy configuration comprises control and/or procedural signals, and/or settings and values (such as resistance, impedance, capacitance, inductance, current/voltage ratings, etc.), that may be applied to influence the operation of a device. Magnetic media, electronic circuits, electrical and optical memory (both volatile and nonvolatile), and firmware are examples of logic. Logic specifically excludes pure signals or software per se (however does not exclude machine memories comprising software and thereby forming configurations of matter). During a memory access, only a local bitline in the relevant part of the column is connected (via its local-to-global switch) to the global bitline.
Often bit cell based register files are typically organized in multiple array banks. Each bank may be organized with multiple bit-cells on a local bitline. Generally, a bitline conveys information to or from a memory cell when a memory access (e.g., read, write) occurs.
Generally, a read bitline is attached to two circuits. The first circuit comprises a keeper or pull-up device which serves the purpose of retaining the state of the bitline when it is not actively driven. The second circuit comprises a separate precharge device that pulls the bitline “high” or up after the evaluation phase of the memory access completes.
Often the demands placed on the bitline cause issues with accessing the memory cells. For example, the keeper device is required to work across a wide range of process, voltage and temperature (PVT) variations, and prevent the bitline from leaking current and transitioning to “low” when it is not desired. In another example, a contention may exist between the keeper device (pulling the bitline “high”) and a bank's bitline pull-down device (pulling the bitline “low”).
To easily identify the discussion of any particular element or act, the most significant digit or digits in a reference number refer to the figure number in which that element is first introduced.
Embodiments of a read latch for machine memories are described. The disclosed read latch implementations exhibit improved performance and lower power consumption compared to conventional read latch structures of substantially the same circuit area. Power savings and noise margins are especially improved at processes at which vddr>>vddw.
Circuit embodiments are disclosed wherein a bit-storing cell includes a first read/write voltage domain crossing and a read latch is coupled to the bit-storing cell via a read bitline. “Read/write voltage domain crossing” refers to a gate or gates of a circuit net where different terminals of the gate(s) are configured to operate in both the read voltage domain and the write voltage domain. “Read voltage domain” herein refers to the voltage domain (range of high and low voltage levels) in which readout logic of a memory system operates. “Write voltage domain” refers to herein refers to the voltage domain (range of high and low voltage levels) in which the bit-writing and storing logic of a memory system operates. The read latch includes a second read/write voltage domain crossing.
In one aspect, the second read/write voltage domain crossing is configured in a pull-down network of the read latch. “Pull-down network” refers to gates and connections within a circuit net that operate to pull down the voltage at a node of the circuit net to logic ground. The pull-down network is configured on a latching node of the read latch, and a keeper circuit may be coupled between the read bitline and the latching node. “Latching node” refers to the node within a latch circuit net where the signal applied to the latch input is captured and stored when the latch is toggled (e.g., by a clock). In another aspect, the second read/write voltage domain crossing is configured at the terminals of a single transistor of the pull-down network.
Other technical features may be readily apparent to one skilled in the art from the following figures, descriptions, and claims.
The transistor MN4 is coupled to the voltage domain vddw of the bit-storing cell 302, and to the voltage domain vddr of the readout logic. When there is a large gap between these supply voltages, particularly at the process corner where vddw is at a minimum rated level and vddr is at a maximum rated level (vddw<<vddr), the transistor MN4 generates a reduced channel current Iread during a read evaluation operation, which in turn increases the clock-to-Q time of the read latch 306.
The read bit line rblb is coupled to a keeper circuit 304. The keeper circuit 304 comprises PMOS transistors MP5 and MP6. The read bit line rblb is further coupled to an output read latch 306 via PMOS transistor MP2. Signal rpcb is applied to pre-charge rblb and the keeper signal rkeepb maintains the pre-charge long enough for the bit value on rblb to settle at node lat (i.e., the setup and hold time) for capture by the read latch 306 upon receipt of the read clock reclk. In this example the read latch 306 comprises NMOS transistors MN6-MN8 and PMOS transistors MP3 and MP4.
At the process corner vddw<<vddr, the lower levels of Iread through transistor MN4 may necessitate a reduction in the frequency of the read clock rdclk to account for the lengthened settling time of the read-out bit value at node lat. This can result in slower, lower bandwidth memory device performance.
Counterintuitively, the impact of the Iread reduction arising from the voltage domain crossing at transistor MN4 may be mitigated in one embodiment by configuring another voltage domain crossing within the read latch 502. In the embodiment depicted in
The lat node of the read latch 502 is coupled to a pull-up network comprising transistors MP2, MP3, and MP4, and to a pull-down network comprising transistors MN6, MN7, MN8, and MN9.
Transistor MN6 shuts off after resetting the read latch 502, and the channel current Ilat through MN9 is modulated by vddw. As Iread decreases with changes to vddw, the current through MN8 and MN9 decreases due to the gating of MN9 with vddw. The trip point of the read latch 502 shifts due to the lat node discharging more slowly, such that the clock-to-Q time of the read latch 502 decreases in accordance with the decrease in Iread.
Configurations in accordance with this embodiment may achieve a substantial improvement of the clock-to-Q delay of the read latch 502, especially at process node vddw<<vddr. Negative impact on read bandwidth (e.g., due to increases in clock-to-Q of the read latch 502) arising from a higher slew of Iread at vddw<<vddr (and more generally for any vddw<vddr process) may be mitigated. An additional benefit is that the timing window for the keeper circuit 304 remains relatively stable across different vddr-vddw processes.
Under certain operating conditions, such as when lat=0, fb=vddr, rblb=vddr, reclk=0, rkpb=vddr, and vddw collapses below operational margins, the embodiment of
The local IO drivers 702 share common IO logic 712 (i.e., GIO). In some memory technologies, a local bit line may extend through more than two memory banks, but generally less than all of the memory banks in the memory. A global read bit line grblb may extend from the memory controller (e.g., column multiplexer 108) to traverse the memory banks, wherein it splits off into local read bit lines rblb.
Output of the NAND gate is input to a NOR gate. Timing and width of the reclk pulse output from the NOR gate is configured for example using a delay line, e.g., a string of inverters. The delay may be a fixed amount, or may be tunable, in manners known in the art. Both the timing and the width of the reclk pulse to trigger the read latches are determined by the delay configured in the delay line and the latch 1002.
Various functional operations described herein may be implemented in logic that is referred to using a noun or noun phrase reflecting said operation or function. For example, an association operation may be carried out by an “associator” or “correlator”. Likewise, switching may be carried out by a “switch”, selection by a “selector”, and so on. “Logic” refers to machine memory circuits and non-transitory machine readable media comprising machine-executable instructions (software and firmware), and/or circuitry (hardware) which by way of its material and/or material-energy configuration comprises control and/or procedural signals, and/or settings and values (such as resistance, impedance, capacitance, inductance, current/voltage ratings, etc.), that may be applied to influence the operation of a device. Magnetic media, electronic circuits, electrical and optical memory (both volatile and nonvolatile), and firmware are examples of logic. Logic specifically excludes pure signals or software per se (however does not exclude machine memories comprising software and thereby forming configurations of matter). Logic symbols in the drawings should be understood to have their ordinary interpretation in the art in terms of functionality and various structures that may be utilized for their implementation, unless otherwise indicated.
Within this disclosure, different entities (which may variously be referred to as “units,” “circuits,” other components, etc.) may be described or claimed as “configured” to perform one or more tasks or operations. This formulation—[entity] configured to [perform one or more tasks]—is used herein to refer to structure (i.e., something physical, such as an electronic circuit). More specifically, this formulation is used to indicate that this structure is arranged to perform the one or more tasks during operation. A structure can be said to be “configured to” perform some task even if the structure is not currently being operated. A “credit distribution circuit configured to distribute credits to a plurality of processor cores” is intended to cover, for example, an integrated circuit that has circuitry that performs this function during operation, even if the integrated circuit in question is not currently being used (e.g., a power supply is not connected to it). Thus, an entity described or recited as “configured to” perform some task refers to something physical, such as a device, circuit, memory storing program instructions executable to implement the task, etc. This phrase is not used herein to refer to something intangible.
The term “configured to” is not intended to mean “configurable to.” An unprogrammed FPGA, for example, would not be considered to be “configured to” perform some specific function, although it may be “configurable to” perform that function after programming.
Reciting in the appended claims that a structure is “configured to” perform one or more tasks is expressly intended not to invoke 35 U.S.C. § 112(f) for that claim element. Accordingly, claims in this application that do not otherwise include the “means for” [performing a function] construct should not be interpreted under 35 U.S.C § 112(f).
As used herein, the term “based on” is used to describe one or more factors that affect a determination. This term does not foreclose the possibility that additional factors may affect the determination. That is, a determination may be solely based on specified factors or based on the specified factors as well as other, unspecified factors. Consider the phrase “determine A based on B.” This phrase specifies that B is a factor that is used to determine A or that affects the determination of A. This phrase does not foreclose that the determination of A may also be based on some other factor, such as C. This phrase is also intended to cover an embodiment in which A is determined based solely on B. As used herein, the phrase “based on” is synonymous with the phrase “based at least in part on.”
As used herein, the phrase “in response to” describes one or more factors that trigger an effect. This phrase does not foreclose the possibility that additional factors may affect or otherwise trigger the effect. That is, an effect may be solely in response to those factors, or may be in response to the specified factors as well as other, unspecified factors. Consider the phrase “perform A in response to B.” This phrase specifies that B is a factor that triggers the performance of A. This phrase does not foreclose that performing A may also be in response to some other factor, such as C. This phrase is also intended to cover an embodiment in which A is performed solely in response to B.
As used herein, the terms “first,” “second,” etc. are used as labels for nouns that they precede, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.), unless stated otherwise. For example, in a register file having eight registers, the terms “first register” and “second register” can be used to refer to any two of the eight registers, and not, for example, just logical registers 0 and 1.
When used in the claims, the term “or” is used as an inclusive or and not as an exclusive or. For example, the phrase “at least one of x, y, or z” means any one of x, y, and z, as well as any combination thereof.
As used herein, a recitation of “and/or” with respect to two or more elements should be interpreted to mean only one element, or a combination of elements. For example, “element A, element B, and/or element C” may include only element A, only element B, only element C, element A and element B, element A and element C, element B and element C, or elements A, B, and C. In addition, “at least one of element A or element B” may include at least one of element A, at least one of element B, or at least one of element A and at least one of element B. Further, “at least one of element A and element B” may include at least one of element A, at least one of element B, or at least one of element A and at least one of element B.
Although the terms “step” and/or “block” may be used herein to connote different elements of methods employed, the terms should not be interpreted as implying any particular order among or between various steps herein disclosed unless and except when the order of individual steps is explicitly described.
Having thus described illustrative embodiments in detail, it will be apparent that modifications and variations are possible without departing from the scope of the intended invention as claimed. The scope of inventive subject matter is not limited to the depicted embodiments but is rather set forth in the following Claims.
