Overcurrent, overcharge, and overdischarge detection and responsive switch control

Abstract

A charge/discharge control circuit includes a control circuit which outputs a control signal to a charge control terminal and a discharge control terminal respectively, a charge/discharge monitoring circuit which monitors charge/discharge of a secondary battery, a charger detection circuit connected to a charger detection terminal and configured to detect a charger connection, and a load open detection circuit connected to the charger detection terminal and configured to detect a state of a load. In response to reception of a signal to instruct turning on of a charge control FET from the charger detection circuit, the control circuit turns on the charge control FET even when the control circuit turned off the charge control FET in response to the signal to instruct turning off of the charge control FET from the charge/discharge monitoring circuit.

Description

RELATED APPLICATIONS

This application claims priority under 35 U.S.C. § 119 to Japanese Patent Application No. 2017-083839 filed on Apr. 20, 2017, the entire content of which is hereby incorporated by reference.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to a charge/discharge control circuit and a battery apparatus.

Background Art

There has heretofore been known a battery apparatus having a charge/discharge control circuit equipped with a first power supply terminal connected to a first electrode of a secondary battery, a second power supply terminal connected to a second electrode of the secondary battery, a charge control terminal connected to a gate terminal of a charge control FET which controls charging to the secondary battery, a discharge control terminal connected to a gate terminal of a discharge control FET which controls discharging from the secondary battery, an overcharge detection circuit which detects overcharge of the secondary battery, an overdischarge detection circuit which detects overdischarge of the secondary battery, and a charger detection terminal for detecting whether a charger is connected (refer to, for example, FIGS. 1 and 5 in Japanese Patent No. 5437770). In such a battery apparatus, although not specified in Japanese Patent No. 5437770, the charger detection terminal has also generally been used as a terminal for monitoring the state of a load connected to the battery apparatus.

Further, there has also been known a battery apparatus which is equipped with a charge/discharge control circuit having an overcurrent detection terminal and an overcurrent detection circuit to improve the detection accuracy of a discharge overcurrent and a charge overcurrent by providing a resistor having one end connected to a second electrode of a secondary battery and the other end connected to a source terminal of a discharge control FET and an overcurrent detection terminal, and detecting a potential difference generated across the resistor by a current flowing through the resistor (refer to, for example, Japanese Patent Application Laid-Open No. 2014-166071).

On the other hand, comparing a charge overcurrent generated by the connection of an abnormal charger and a discharge overcurrent generated due to the abnormality of a connected load, the latter generally becomes often large. Accordingly, the discharge control FET is required to have a high current capability, whereas the charge control FET can have a lower current capability. Consequently, there has been a growing demand for a charge/discharge control circuit with which a battery apparatus can be configured in such a manner that a charging path and a discharging path are separated (refer to, for example, FIG. 4 in Japanese Patent No. 5437770), and a low cost FET having low current capability can be used for a charge control FET.

SUMMARY OF THE INVENTION

Configuring the battery apparatus in which the charging path and the discharging path are separated from each other in such a manner that the detection of a connection state of a charger and the detection of the overcurrent with high accuracy, both illustrated in Japanese Patent No. 5437770, are both possible, the following phenomena, however, occur.

That is, in an overcharge detection state, in which the charge/discharge control circuit turns off the charge control FET after the secondary battery is charged by the charger and the voltage of the secondary battery becomes a voltage more than or equal to an overcharge voltage, once the load connected to the battery apparatus takes an abnormal state and a large current flows, the charge/discharge control circuit is brought into a discharge overcurrent detection state in which the discharge control FET is turned off by detection of a discharge overcurrent. At this time it is not possible to monitor the state of the load because the terminal (charger detection terminal) for monitoring the state of the load is separated from the load. Thus, even if an abnormal state of the connected load is released, the battery apparatus cannot recover from the discharge overcurrent state until the disconnection of the charger is detected, and the voltage of the secondary battery falls below the overcharge voltage to turn on the charge control FET.

The present invention aims to provide a charge/discharge control circuit and a battery apparatus in which a charging path and a discharging path are separated, and which is capable of monitoring the state of the load at a release from an abnormal state of the connected load which caused a discharge overcurrent detection in a discharge overcurrent detection state after being in an overcharge detection state.

In one aspect of the present invention, there is provided a charge/discharge control circuit equipped with a first power supply terminal connected to a first electrode of a secondary battery, a second power supply terminal connected to a second electrode of the secondary battery, a charge control terminal connected to a gate terminal of a charge control FET which controls charging to the secondary battery, a discharge control terminal connected to a gate terminal of a discharge control FET which controls discharging from the secondary battery, an overcurrent detection terminal connected to a source terminal of the discharge control FET, a charger detection terminal connected to a charger, a control circuit configure to output a control signal to the charge control terminal and the discharge control terminal respectively, a charge/discharge monitoring circuit connected to the first power supply terminal and the second power supply terminal, configured to monitor charge/discharge of the secondary battery, and configured to output a signal to instruct turning off of the charge control FET or the discharge control FET to the control circuit in response to detection of overcharge or overdischarge of the secondary battery, an overcurrent detection circuit connected to the overcurrent detection terminal and configured to output a signal to instruct turning off of the discharge control FET to the control circuit according to detection of a discharge overcurrent, based on a voltage of the overcurrent detection terminal, a charger detection circuit connected to the charger detection terminal and configured to output a signal to instruct turning on of the charge control FET to the control circuit according to detection of disconnection of the charger based on a voltage of the charger detection terminal, and a load open detection circuit connected to the charger detection terminal and configured to output a signal to instruct turning on of the discharge control FET to the control circuit according to detection based on the voltage of the charger detection terminal that a load connected to the charger detection terminal is in a normal state, and in which the control circuit turns on the charge control FET in response to the signal to instruct turning on of the charge control FET from the charger detection circuit, even when the control circuit turns off the charge control FET in response to the signal to instruct turning off of the charge control FET from the charge/discharge monitoring circuit.

Further, in another aspect of the present invention, there is provided a battery apparatus equipped with a secondary battery, a charge/discharge terminal connected to a first electrode of the secondary battery, a resistor having one end connected to a second electrode of the secondary battery, a discharge control FET having a source terminal connected to the other end of the resistor, a charge control FET having a drain terminal connected to a drain terminal of the discharge control FET, a charge terminal connected to a source terminal of the charge control FET, and a discharge terminal connected to a connecting point of the charge control FET and the discharge control FET, and in which a charger is connected between the charge/discharge terminal and the charge terminal, and a load is connected between the charge/discharge terminal and the discharge terminal.

According to the present invention, in a battery apparatus which includes the above charge/discharge control circuit, and in which a charging path and a discharging path are separated from each other, monitoring the state of the load is capable at a release from an abnormal state of the connected load which caused the discharge overcurrent detection in a discharge overcurrent detection state after being in an overcharge detection state. Since the control circuit turns on the charge control FET in response to a signal to instruct turning on of the charge control FET even when the control circuit turns off the charge control FET in response to the signal to instruct turning off of the charge control FET from the charge/discharge monitoring circuit, the load open detection circuit can be connected to the load through the charger detection terminal and the charge control FET which has been turned on, thereby making it possible to monitor the state of the load. Thus, release from the abnormal state of the connected load turns on the discharge control FET, permitting recovery from the discharge overcurrent detection state.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating a battery apparatus equipped with a charge/discharge control circuit according to one embodiment of the present invention;

FIG. 2 is a circuit diagram illustrating an example of a charger detection circuit illustrated in FIG. 1;

FIG. 3 is a circuit diagram illustrating an example of a load open detection circuit illustrated in FIG. 1, and

FIG. 4 is a flow diagram illustrating example functions performed by the charge/discharge control circuit illustrated in FIG. 1.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Embodiments of the present invention will hereinafter be described with reference to the accompanying drawings.

FIG. 1 is a diagram illustrating a battery apparatus 10 equipped with a charge/discharge control circuit 1 according to an embodiment of the present invention.

The battery apparatus 10 is equipped with the charge/discharge control circuit 1, a secondary battery 2, a charge/discharge terminal P+, a discharge terminal DIS−, a charge terminal CHA−, a charge control FET3, a discharge control FET4, and a resistor 5. The charge control FET3 controls charging to the secondary battery 2. The discharge control FET4 controls discharging from the secondary battery 2.

The charge/discharge terminal P+ is connected to a first electrode 2a of the secondary battery 2. One end of the resistor 5 is connected to a second electrode 2b of the secondary battery 2. A source terminal of the discharge control FET4 is connected to the other end of the resistor 5. A drain terminal of the charge control FET3 is connected to a drain terminal of the discharge control FET4. The charge terminal CHA− is connected to a source terminal of the charge control FET3. The discharge terminal DIS− is connected to a connecting point (drain terminals of both FETs) of the charge control FET3 and the discharge control FET4.

A charger 20 is connected between the charge/discharge terminal P+ and the charge terminal CHA−. A load 30 is connected between the charge/discharge terminal P+ and the discharge terminal DIS−.

The battery apparatus 10 has thus a configuration in which a charging path and a discharging path are separated from each other.

The charge/discharge control circuit 1 is equipped with a first power supply terminal 1A, a second power supply terminal 1B, a charge control terminal 1C, a discharge control terminal 1D, an overcurrent detection terminal 1E, and a charger detection terminal 1F. Further, the charge/discharge control circuit 1 is equipped with a charge/discharge monitoring circuit 1a, a control circuit 1b, an overcurrent detection circuit 1c, a charger detection circuit 1d, and a load open detection circuit 1e. The charge/discharge monitoring circuit 1a is connected to the first power supply terminal 1A and the second power supply terminal 1B and monitors a charge/discharge state of the secondary battery 2. The control circuit 1b controls the charge control FET3 and the discharge control FET4. The overcurrent detection circuit 1c detects a discharge overcurrent from the secondary battery 2 and a charge overcurrent to the secondary battery 2. The charger detection circuit 1d detects a connecting state of the charger 20.

The first power supply terminal 1A is connected to the first electrode 2a of the secondary battery 2 and thereby supplies a first power supply voltage VDD to each circuit in the charge/discharge control circuit 1. The second power supply terminal 1B is connected to the second electrode 2b of the secondary battery 2 and thereby supplies a second power supply voltage VSS to each circuit in the charge/discharge control circuit 1. The control circuit 1b is connected to the charge/discharge monitoring circuit 1a, the overcurrent detection circuit 1c, the charger detection circuit 1d, and the load open detection circuit 1e. Also, the control circuit 1b is connected to the charge control terminal 1C. The charge control terminal 1C is connected to a gate terminal of the charge control FET3. Further, the control circuit 1b is connected to the discharge control terminal 1D. The discharge control terminal 1D is connected to a gate terminal of the discharge control FET4. The overcurrent detection circuit 1c is connected to the overcurrent detection terminal 1E. The overcurrent detection terminal 1E is connected to the other end of the resistor 5. The charger detection circuit 1d and the load open detection circuit 1e are connected to the charger detection terminal 1F. The charger detection terminal 1F is connected to the source terminal of the charge control FET3.

The charger detection terminal 1F is also used as a terminal for monitoring the state of the load connected to the battery apparatus 10.

The battery apparatus 10 having such a configuration operates as follows.

First, the charger 20 is connected between the charge/discharge terminal P+ and the charge terminal CHA−, and then the charger 20 performs charging to the secondary battery 2. The charging to the secondary battery 2 continues, and the voltage of the secondary battery 2 becomes a voltage equal to or higher than an overcharge voltage, then the charge/discharge monitoring circuit 1a outputs a signal to instruct the turning off of the charge control FET3 to the control circuit 1b. In response to the signal, the control circuit 1b turns off the charge control FET3 and thereby enters an overcharge detection state.

In such an overcharge detection state, the load 30 is connected between the charge/discharge terminal P+ and the discharge terminal DIS−, and the load 30 goes into an abnormal state to make a large current flow, then a potential difference developed across the resistor 5 becomes large, exceeding a voltage determined to be a discharge overcurrent. The overcurrent detection circuit 1c detects the discharge overcurrent and outputs a signal to instruct turning off of the discharge control FET4 to the control circuit 1b. In response to the signal, the control circuit 1b turns off the discharge control FET4.

The battery apparatus 10 is thus brought into a state in which both charging and discharging are prohibited.

Thereafter, the charger 20 is disconnected, and the charger detection circuit 1d detects based on the voltage of the charger detection terminal 1F connected to the charge terminal CHA—that the charger 20 is not connected, and outputs a signal to instruct turning on of the charge control FET3 to the control circuit 1b. As is illustrated at 402 in FIG. 4, although, at this time, the control circuit 1b turns off the charge control FET3 based on the instruction issued from the charge/discharge monitoring circuit 1a as described above, the control circuit 1b turns on the charge control FET3 while giving priority to the signal instructing the turning on of the charge control FET3 from the charger detection circuit 1d.

Since the voltage of the secondary battery 2 does not arise higher once the charger 20 is disconnected even if the secondary battery 2 is in the overcharged state, no problem occurs at turning on of the charge control FET3 by the control circuit 1b, as is illustrated at 402 in FIG. 4.

The charge control FET3 turns on in the above-described manner, the charger detection terminal 1F is then brought into a state of being connected to the load 30 through the charge control FET3. Thus, the load open detection circuit 1e becomes capable of detecting the state of the load 30, based on the voltage of the charger detection terminal 1F. Then, as is illustrated at 404 in FIG. 4, the abnormal state of the load 30 is released, i.e., the load 30 returns to its normal state or the load 30 is disconnected, the load open detection circuit 1e detects that the load 30 is in the normal state or disconnected, and outputs a signal to instruct turning on of the discharge control FET4 to the control circuit 1b. The control circuit 1b turns on the discharge control FET4 based on the signal.

Thus, the battery apparatus 10 returns to a state in which both of the charging and the discharging are permitted.

According to the present embodiment as described above, in response to release from the abnormal state of the load 30 connected to the battery apparatus 10 in a discharge overcurrent detection state in which the discharge control FET is turned off by a large current flow caused by an abnormal state of the load 30 after being in the overcharge detection state in which the charge control FET3 is off, the charge control FET3 turns on based on the disconnection of the charger 20, and hence the load open detection circuit 1e is capable of detecting that the abnormal state of the connected load 30 has been released. Thus, once the disconnection of the charger 20 is detected, the battery apparatus 10 can recover from the discharge overcurrent state without waiting for the falling of the voltage of the secondary battery 2 below the overcharge voltage to turn on the charge control FET3.

FIG. 2 is a circuit diagram illustrating one example of the charger detection circuit 1d illustrated in FIG. 1.

The charger detection circuit 1d of the present example is equipped with a constant current source 1d1 and an NMOS transistor 1d2.

The constant current source 1d1 has one end which receives the first power supply voltage VDD corresponding to the voltage of the first power supply terminal 1A. The NMOS transistor 1d2 has a drain terminal connected to the other end of the constant current source 1d1, a gate terminal which receives the second power supply voltage VSS corresponding to the voltage of the second power supply terminal 1B, and a source terminal connected to the charger detection terminal 1F. Further, a connecting point of the constant current source 1d1 and the drain terminal of the NMOS transistor 1d2 serves as the output of the charger detection circuit 1d.

The charger detection circuit 1d having such a configuration determines whether the charger 20 is connected based on the voltage of the charger detection terminal 1F as described below.

Since the voltage of the charger 20 is larger than the voltage of the secondary battery 2, the voltage of the charger detection terminal 1F becomes lower than second power supply voltage VSS when the charger 20 is connected between the charge/discharge terminal P+ and the charge terminal CHA−. As a result, the NMOS transistor 1d2 turns on, and the charger detection circuit 1d outputs a signal of an L level indicating that the charger 20 is connected, to the control circuit 1b.

On the other hand, when the charger 20 is not connected between the charge/discharge terminal P+ and the charge terminal CHA−, the voltage of the charger detection terminal 1F becomes the second power supply voltage VSS which is the same voltage as the voltage of the gate terminal of the NMOS transistor 1d2. Then, the NMOS transistor 1d2 turns off. Thus, the charger detection circuit 1d outputs a signal of an H level indicating that the charger 20 is being disconnected, to the control circuit 1b.

FIG. 3 is a circuit diagram illustrating one example of the load open detection circuit 1e illustrated in FIG. 1.

The load open detection circuit 1e of the present example is equipped with a resistor 1e1, an NMOS transistor 1e2, a comparator 1e3, and a reference voltage source 1e4.

One end of the resistor 1e1 and a non-inversion input terminal of the comparator 1e3 are connected to the charger detection terminal 1F. The NMOS transistor 1e2 has a drain terminal connected to the other end of the resistor 1e1, a gate terminal which receives the output of the control circuit 1b, and a source terminal which receives the second power supply voltage VSS. The voltage of the reference voltage source 1e4 is supplied to an inversion input terminal of the comparator 1e3. Further, the output of the comparator 1e3 is the output of the load open detection circuit 1e. The voltage of the reference voltage source 1e4 is set to a voltage value to be a criterion for determining whether the status of the load 30 connected to the charger detection terminal 1F is abnormal.

The load open detection circuit 1e having such a configuration determines whether the load 30 is in the abnormal state based on the voltage of the charger detection terminal 1F as described below.

In response to the off-state of the discharge control FET4, the control circuit 1b supplies a signal of an H level to the gate terminal of the NMOS transistor 1e2. Thus, the NMOS transistor 1e2 turns on. Since the discharge control FET4 is off, the charger detection terminal 1F becomes a state of being connected to the charge/discharge terminal P+ through the charge control FET3 and the load 30. Accordingly, the voltage of the charger detection terminal 1F becomes a voltage obtained by dividing a difference between the voltage of the charge/discharge terminal P+ and the second power supply voltage VSS by a resistance ratio between the load 30 and the resistor 1e1.

At this time, when the load 30 is in the abnormal state, the voltage of the charger detection terminal 1F rises and becomes almost the voltage of the charge/discharge terminal P+. Thus, the comparator 1e3 outputs a signal of an H level indicating that the load 30 is abnormal, to the control circuit 1b. The control circuit 1b maintains an off state of the discharge control FET4 based on the signal.

On the other hand, when the load 30 is in a normal state or disconnected, the voltage of the charger detection terminal 1F becomes the second power supply voltage VSS and hence falls below the voltage of the reference voltage source 1e4 since the NMOS transistor 1e2 is on. Thus, the comparator 1e3 outputs a signal of an L level indicating that the load 30 is in the normal state or not connected, to the control circuit 1b. Based on the signal, the control circuit 1b turns on the discharge control FET4 which has been turned off.

Further, in response to the on-state of the discharge control FET4 the control circuit 1b supplies a signal of an L level to the gate terminal of the NMOS transistor 1e2. Thus, the NMOS transistor 1e2 turns off. Since the discharge control FET4 is on, the charger detection terminal 1F becomes a state of being connected to the second electrode 2b of the secondary battery 2 through the charge control FET3, the discharge control FET4, and the resistor 5. Accordingly, the voltage of the charger detection terminal 1F becomes the second power supply voltage VSS. Thus, the comparator 1e3 outputs a signal of an L level indicating that the load 30 is normal, to the control circuit 1b. Therefore, the control circuit 1b maintains an on state of the discharge control FET4.

Although the embodiments of the present invention and their modifications have been described above, these embodiments and their modifications have been presented as examples and are not intended to limit the scope of the invention. These embodiments and their modifications can be implemented in various other forms, and various omissions, substitutions and modifications can be made within the scope not departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention and also included in the invention described in the scope of the appended claims and within the scope of equivalency thereof. Further, the above-described embodiments and their modifications can be appropriately combined with each other.

For example, since the charge/discharge control circuit of the present invention exhibits a desired effect in the battery apparatus in which the charging path and the discharging path are separated, the above embodiment has illustrated only the example in which the charge/discharge control circuit of the present invention is used in the battery apparatus 10 in which the charging path and the discharging path are separated. However, the charge/discharge control circuit of the present invention can also be used in a battery apparatus in which a charging path and a discharging path are in common. That is, the charge/discharge control circuit of the present invention can be applied to both of the battery apparatus in which the charging path and the discharging path are separated, and the battery apparatus in which the charging path and the discharging path are in common, and provide high versatility.

Further, although FIG. 2 has illustrated the example in which the charger detection circuit 1d is configured by the constant current source 1d1 and the NMOS transistor 1d2, the charger detection circuit 1d may be configured instead by use of a comparator.

Claims

1. A charge/discharge control circuit, comprising: a first power supply terminal connected to a first electrode of a secondary battery;a second power supply terminal connected to a second electrode of the secondary battery;a charge control terminal connected to a gate terminal of a charge control FET which controls charging to the secondary battery;a discharge control terminal connected to a gate terminal of a discharge control FET which controls discharging from the secondary battery;an overcurrent detection terminal connected to a source terminal of the discharge control FET;a charger detection terminal connected to a charger;a control circuit configured to output a control signal to the charge control terminal and the discharge control terminal respectively;a charge/discharge monitoring circuit connected to the first power supply terminal and the second power supply terminal, configured to monitor charge/discharge of the secondary battery, and configured to output a signal to instruct turning off of the charge control FET or the discharge control FET to the control circuit in response to detection of overcharge or overdischarge of the secondary battery;an overcurrent detection circuit connected to the overcurrent detection terminal and configured to output a signal to instruct turning off of the discharge control FET to the control circuit according to detection of a discharge overcurrent, based on a voltage of the overcurrent detection terminal;a charger detection circuit connected to the charger detection terminal and configured to output a signal to instruct turning on of the charge control FET to the control circuit in response to detecting, by the charger detection circuit, that the charger is disconnected based on a voltage of the charger detection terminal; anda load open detection circuit connected to the charger detection terminal and configured to output a signal to instruct turning on of the discharge control FET to the control circuit according to detection based on the voltage of the charger detection terminal that a load connected to the charger detection terminal is in a normal state,wherein the control circuit is configured to turn on the charge control FET in response to the signal to instruct turning on of the charge control FET from the charger detection circuit responsive to detecting that the charger is disconnected, even when the control circuit turns off the charge control FET in response to the signal to instruct turning off of the charge control FET from the charge/discharge monitoring circuit, andwherein the charger detection terminal is connected to the load through the charge control FET, and the load open detection circuit is connected to the load through the charger detection terminal and the charge control FET.

2. A battery apparatus comprising: the charge/discharge control circuit according to claim 1;the secondary battery having the first electrode and the second electrode;a charge/discharge terminal connected to the first electrode of the secondary battery;a resistor having one end connected to the second electrode of the secondary battery;the discharge control FET having the source terminal connected to another end of the resistor;the charge control FET having a drain terminal connected to a drain terminal of the discharge control FET;a charge terminal connected to a source terminal of the charge control FET; anda discharge terminal connected to a connecting point of the charge control FET and the discharge control FET.