Patent Application
20170170325
One embodiment of the present invention relates to an oxide semiconductor film. One embodiment of the present invention relates to a semiconductor device including an oxide semiconductor film and a display device including the semiconductor device.
Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, and a manufacturing method. In addition, one embodiment of the present invention relates to a process, a machine, manufacture, and a composition of matter. In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, a driving method thereof, and a manufacturing method thereof.
In this specification and the like, a semiconductor device generally means a device that can function by utilizing semiconductor characteristics. A semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are each an embodiment of a semiconductor device. An imaging device, a display device, a liquid crystal display device, a light-emitting device, an electro-optical device, a power generation device (including a thin film solar cell, an organic thin film solar cell, and the like), and an electronic appliance may each include a semiconductor device.
As a semiconductor material applicable to a transistor, an oxide semiconductor has been attracting attention. For example, Patent Document 1 discloses a semiconductor device achieving high field-effect mobility (simply referred to “mobility” or “μFE” in some cases) with such a structure that a plurality of oxide semiconductor layers are stacked, the oxide semiconductor layer functioning as a channel in the plurality of oxide semiconductor layers contains indium and gallium, and the proportion of indium is higher than the proportion of gallium.
Non-Patent Document 1 discloses that an oxide semiconductor containing indium, gallium, and zinc has a homologous series represented by In1−xGa1+xO3(ZnO)m (x fulfills −1≦x≦1, and m is a natural number). Furthermore, Non-Patent Document 1 discloses a solid solution range of the homologous series. For example, in the solid solution range of the homologous series in the case where m is 1, x ranges from −0.33 to 0.08, and in the solid solution range of the homologous series in the case where m is 2, x ranges from −0.68 to 0.32.
It is preferable for a transistor using an oxide semiconductor film for a channel region to have a high field-effect mobility. However, an increase in the field-effect mobility of the transistor causes a problem in that the transistor is likely to have normally-on characteristics. Here, the “normally-on” refers to a state in which a channel exists even when voltage is not applied to the gate electrode and current flows in the transistor.
Furthermore, in a transistor using an oxide semiconductor film for a channel region, an oxygen vacancy which is formed in the oxide semiconductor film adversely affects the transistor characteristics. For example, oxygen vacancy formed in the oxide semiconductor film is bonded with hydrogen to serve as a carrier supply source. The carrier supply source generated in the oxide semiconductor film causes a change in the electrical characteristics, typically, shift in the threshold voltage, of the transistor including the oxide semiconductor film.
When the amount of oxygen vacancies in the oxide semiconductor film is too large, the threshold voltage of the transistor is shifted in the negative direction, and the transistor has normally-on characteristics. Thus, in the channel region of the oxide semiconductor film, the amount of oxygen vacancies is preferably small or the amount with which the normally-on characteristics are not exhibited.
In view of the foregoing problems, an object of one embodiment of the present invention is to provide an oxide semiconductor film which enables a high field-effect mobility when the oxide semiconductor film is used for a channel region of the transistor. Another object of one embodiment of the present invention is to prevent a change in electrical characteristics of a transistor including an oxide semiconductor film and to improve the reliability of the transistor. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another object of one embodiment of the present invention is to provide a novel semiconductor device. Another object of one embodiment of the present invention is to provide a novel display device.
Note that the description of the above object does not disturb the existence of other objects. In one embodiment of the present invention, there is no need to achieve all the objects. Objects other than the above objects will be apparent from and can be derived from the description of the specification and the like.
One embodiment of the present invention is an oxide semiconductor film containing In, M (M is any one of Al, Ga, Y, and Sn), and Zn, and the oxide semiconductor film includes a region with a film density higher than or equal to 6.3 g/cm3 and lower than 6.5 g/cm3.
Another embodiment of the present invention is an oxide semiconductor film containing In, M (M is any one of Al, Ga, Y, and Sn), and Zn, and when the oxide semiconductor film is etched using a phosphoric acid aqueous solution obtained by diluting 85 vol % phosphoric acid with water 100 times, the oxide semiconductor film includes a region obtained by etching at an etching rate that is higher than or equal to 10 nm/min and lower than or equal to 45 nm/min.
In the above embodiments, the oxide semiconductor film preferably includes a crystal part, and the crystal part preferably includes a region having c-axis alignment and a region having alignment different from the c-axis alignment.
In the above embodiments, it is preferable that the oxide semiconductor film have an atomic ratio in a neighborhood of In:M:Zn=4:2:3 and in the case where the proportion of In is 4, the proportion of M be greater than or equal to 1.5 and less than or equal to 2.5 and the proportion of Zn be greater than or equal to 2 and less than or equal to 4.
Another embodiment of the present invention is a semiconductor device including an oxide semiconductor film, and the semiconductor device includes the oxide semiconductor film over a first insulating film, a gate insulating film over the oxide semiconductor film, a gate electrode over the gate insulating film, and a second insulating film over the oxide semiconductor film and the gate electrode. The oxide semiconductor film includes a channel region in contact with the gate insulating film, a source region in contact with the second insulating film, and a drain region in contact with the second insulating film. The oxide semiconductor film includes a region with a film density higher than or equal to 6.3 g/cm3 and lower than 6.5 g/cm3.
Another embodiment of the present invention is a semiconductor device including an oxide semiconductor film, and the semiconductor device includes a gate electrode, a gate insulating film over the gate electrode, the oxide semiconductor film over the gate insulating film, and a pair of electrodes over the oxide semiconductor film. The oxide semiconductor film includes a region with a film density higher than or equal to 6.3 g/cm3 and lower than 6.5 g/cm3.
In the above embodiments, it is preferable that the oxide semiconductor film include In, M (M is Al, Ga, Y, or Sn), and Zn. In the above embodiments, the oxide semiconductor film preferably includes a crystal part, and the crystal part preferably includes a region having c-axis alignment and a region having alignment different from the c-axis alignment.
Another embodiment of the present invention is a display device including the semiconductor device according to any one of the above embodiments, and a display element. Another embodiment of the present invention is a display module including the display device and a touch sensor. Another embodiment of the present invention is an electronic device including the semiconductor device according to any one of the above embodiments, the display device, or the display module, and an operation key or a battery.
According to one embodiment of the present invention, an oxide semiconductor film which enables a high field-effect mobility can be provided in the case where the oxide semiconductor film is used for a channel region of a transistor. According to one embodiment of the present invention, a change in electrical characteristics can be suppressed and reliability can be improved in a transistor including an oxide semiconductor film. Alternatively, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided. According to one embodiment of the present invention, a novel display device can be provided.
Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily achieve all the effects listed above. Other effects will be apparent from and can be derived from the description of the specification, the drawings, the claims, and the like.
Hereinafter, embodiments will be described with reference to drawings. However, the embodiments can be implemented in many different modes, and it will be readily appreciated by those skilled in the art that modes and details thereof can be changed in various ways without departing from the spirit and scope of the present invention. Thus, the present invention should not be interpreted as being limited to the following description of the embodiments.
In the drawings, the size, the layer thickness, or the region is exaggerated for clarity in some cases. Therefore, the size, the layer thickness, or the region is not limited to the illustrated scale. Note that the drawings are schematic views showing ideal examples, and embodiments of the present invention are not limited to shapes or values shown in the drawings.
Note that in this specification, ordinal numbers such as “first”, “second”, and “third” are used in order to avoid confusion among components, and the terms do not limit the components numerically.
In this specification, terms for describing arrangement, such as “over”, “above”, “under”, and “below”, are used for convenience in describing a positional relation between components with reference to drawings. Furthermore, the positional relationship between components is changed as appropriate in accordance with a direction in which each component is described. Thus, there is no limitation on terms used in this specification, and description can be made appropriately depending on the situation.
In this specification and the like, a transistor is an element having at least three terminals of a gate, a drain, and a source. The transistor has a channel region between a drain (a drain terminal, a drain region, or a drain electrode) and a source (a source terminal, a source region, or a source electrode), and current can flow through the drain, the channel region, and the source. Note that in this specification and the like, a channel region refers to a region through which current mainly flows.
Furthermore, functions of a source and a drain might be switched when transistors having different polarities are employed or a direction of current flow is changed in circuit operation, for example. Therefore, the terms “source” and “drain” can be switched in this specification and the like.
Note that in this specification and the like, the term “electrically connected” includes the case where components are connected through an object having any electric function. There is no particular limitation on the “object having any electric function” as long as electric signals can be transmitted and received between components that are connected through the object. Examples of an “object having any electric function” are a switching element such as a transistor, a resistor, an inductor, a capacitor, and an element with a variety of functions as well as an electrode and a wiring.
In this specification and the like, the term “parallel” indicates that the angle formed between two straight lines is greater than or equal to −10° and less than or equal to 10°, and accordingly also includes the case where the angle is greater than or equal to −5° and less than or equal to 5°. In addition, the term “perpendicular” means that the angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°. Thus, the case where the angle is greater than or equal to 85° and less than or equal to 95° is also included.
In this specification and the like, the terms “film” and “layer” can be interchanged with each other depending on the case or circumstances. For example, the term “conductive layer” can be changed into the term “conductive film” in some cases. In addition, the term “insulating film” can be changed into the term “insulating layer” in some cases.
Unless otherwise specified, off-state current in this specification and the like refers to drain current of a transistor in an off state (also referred to as a non-conducting state and a cutoff state). Unless otherwise specified, the off state of an n-channel transistor means that the voltage between its gate and source (Vgs: gate-source voltage) is lower than the threshold voltage Vth, and the off state of a p-channel transistor means that the gate-source voltage Vgs is higher than the threshold voltage Vth. For example, the off-state current of an n-channel transistor sometimes refers to a drain current that flows when the gate-source voltage Vgs is lower than the threshold voltage Vth.
The off-state current of a transistor depends on Vgs in some cases. Thus, “the off-state current of a transistor is lower than or equal to I” may mean “there is Vgs with which the off-state current of the transistor becomes lower than or equal to I”. Furthermore, “the off-state current of a transistor” means “the off-state current in an off state at predetermined Vgs”, “the off-state current in an off state at Vgs in a predetermined range”, “the off-state current in an off state at Vgs with which sufficiently reduced off-state current is obtained”, or the like.
As an example, the assumption is made of an n-channel transistor where the threshold voltage Vth is 0.5 V and the drain current is 1×10−9 A at Vgs of 0.5 V, 1×10−13 A at Vgs of 0.1 V, 1×10−19 A at Vgs of −0.5 V, and 1×10−22 A at Vgs of −0.8 V. The drain current of the transistor is 1×10−19 A or lower at Vgs of −0.5 V or at Vgs in the range of −0.8 V to −0.5 V; therefore, it can be said that the off-state current of the transistor is 1×10−19 A or lower. Since there is Vgs at which the drain current of the transistor is 1×10−22 A or lower, it may be said that the off-state current of the transistor is 1×10−22 A or lower.
In this specification and the like, the off-state current of a transistor with a channel width W is sometimes represented by a current value per channel width W or by a current value per given channel width (e.g., 1 μm). In the latter case, the off-state current may be expressed in the unit with the dimension of current per length (e.g., A/μm).
The off-state current of a transistor depends on temperature in some cases. Unless otherwise specified, the off-state current in this specification may be an off-state current at room temperature, 60° C., 85° C., 95° C., or 125° C. Alternatively, the off-state current may be an off-state current at a temperature at which the reliability required in a semiconductor device or the like including the transistor is ensured or a temperature at which the semiconductor device or the like including the transistor is used (e.g., temperature in the range of 5° C. to 35° C.). The description “an off-state current of a transistor is lower than or equal to I” may refer to a situation where there is Vgs at which the off-state current of a transistor is lower than or equal to I at room temperature, 60° C., 85° C., 95° C., 125° C., a temperature at which the reliability required in a semiconductor device or the like including the transistor is ensured, or a temperature at which the semiconductor device or the like including the transistor is used (e.g., temperature in the range of 5° C. to 35° C.).
The off-state current of a transistor depends on voltage Vas between its drain and source in some cases. Unless otherwise specified, the off-state current in this specification may be an off-state current at Vds of 0.1 V, 0.8 V, 1 V, 1.2 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 10 V, 12 V, 16 V, or 20 V. Alternatively, the off-state current might be an off-state current at Vas at which the required reliability of a semiconductor device or the like including the transistor is ensured or Vas at which the semiconductor device or the like including the transistor is used. The description “an off-state current of a transistor is lower than or equal to a current I” may mean that there is Vgs at which the off-state current of the transistor is lower than or equal to the current I at a voltage Vds of 0.1 V, 0.8 V, 1 V, 1.2 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 10 V, 12 V, 16 V, or 20 V, at a voltage Vds at which the reliability of a semiconductor device or the like including the transistor is ensured, or at a voltage Vds at which in the semiconductor device or the like including the transistor is used.
In the above description of off-state current, a drain may be replaced with a source. That is, the off-state current sometimes refers to a current that flows through a source of a transistor in the off state.
In this specification and the like, the term “leakage current” sometimes expresses the same meaning as “off-state current”. In this specification and the like, the off-state current sometimes refers to current that flows between a source and a drain of a transistor in the off state, for example.
In this specification and the like, a “semiconductor” includes characteristics of an “insulator” in some cases when the conductivity is sufficiently low, for example. Further, a “semiconductor” and an “insulator” cannot be strictly distinguished from each other in some cases because a border between the “semiconductor” and the “insulator” is not clear. Accordingly, a “semiconductor” in this specification and the like can be called an “insulator” in some cases. Similarly, an “insulator” in this specification and the like can be called a “semiconductor” in some cases. An “insulator” in this specification and the like can be called a “semi-insulator” in some cases.
In this specification and the like, a “semiconductor” includes characteristics of a “conductor” in some cases when the conductivity is sufficiently high, for example. Further, a “semiconductor” and a “conductor” cannot be strictly distinguished from each other in some cases because a border between the “semiconductor” and the “conductor” is not clear. Accordingly, a “semiconductor” in this specification and the like can be called a “conductor” in some cases. Similarly, a “conductor” in this specification and the like can be called a “semiconductor” in some cases.
In this specification and the like, an impurity in a semiconductor refers to an element that is not a main component of the semiconductor film. For example, an element with a concentration lower than 0.1 atomic % is an impurity. If a semiconductor contains an impurity, the density of states (DOS) may be formed therein, the carrier mobility may be decreased, or the crystallinity may be decreased, for example. In the case where the semiconductor includes an oxide semiconductor, examples of an impurity which changes the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components; specific examples are hydrogen (included in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. When the semiconductor is an oxide semiconductor, oxygen vacancies may be formed by entry of impurities such as hydrogen, for example. Furthermore, in the case where the semiconductor includes silicon, examples of an impurity which changes the characteristics of the semiconductor include oxygen, Group 1 elements except hydrogen, Group 2 elements, Group 13 elements, and Group 15 elements.
In this embodiment, an oxide semiconductor film which is one embodiment of the present invention is described.
The oxide semiconductor film of one embodiment of the present invention includes indium (In), M (M is Al, Ga, Y, or Sn), and zinc (Zn). Specifically, M is preferably gallium (Ga). In the following description, Ga is used as M
An oxide semiconductor film containing In has high carrier mobility (electron mobility), for example. An oxide semiconductor film has high energy gap (Eg) by containing Ga, for example. Note that Ga is an element having high bonding energy with oxygen, which is higher than the bonding energy of In with oxygen. In addition, an oxide semiconductor film containing Zn is easily crystallized.
The oxide semiconductor film of one embodiment of the present invention preferably has a crystal structure exhibiting a single phase, particularly, homologous series. For example, the oxide semiconductor film has a composition of In1+MM1−xO3(ZnO)y structure (x satisfies 0<x<0.5, and y is approximately 1) where the content of In is higher than that of M, so that the carrier density (electron mobility) of the oxide semiconductor film can be high.
In particular, the oxide semiconductor film of one embodiment of the present invention preferably has a composition in the neighborhood of the In1+xM1−xO3(ZnO)y structure (x satisfies 0<x<0.5, and y is approximately 1), specifically a composition in the neighborhood of a structure where In:M:Zn=1.33:0.67:1 (around In:M:Zn=4:2:3).
In this specification and the like, “neighborhood” means a range of ±1, preferably ±0.5 with respect to the proportion of atoms of a metal element. For example, in the case where the oxide semiconductor film has a composition in the neighborhood of In:Ga:Zn=4:2:3 where the proportion of In is 4, the proportion of Ga may be greater than or equal to 1 and less than or equal to 3 (1≦Ga≦3) and the proportion of Zn is greater than or equal to 2 and less than or equal to 4 (2≦Zn≦4), preferably the proportion of Ga is greater than or equal to 1.5 and less than or equal to 2.5 (1.5≦Ga≦2.5) and the proportion of Zn is greater than or equal to 2 and less than or equal to 4 (2≦Zn≦4).
The oxide semiconductor film of one embodiment of the present invention has a high film density. Specifically, the oxide semiconductor film has a region where the film density is higher than or equal to 6.3 g/cm3 and lower than 6.5 g/cm3.
When the oxide semiconductor film having the above composition and the above film density is used for a channel region of a transistor, a semiconductor device with high field-effect mobility and high reliability can be provided.
Examples of a method for forming the oxide semiconductor film of one embodiment of the present invention include a sputtering method, a pulsed laser deposition (PLD) method, a plasma-enhanced chemical vapor deposition (PECVD) method, a thermal chemical vapor deposition (CVD) method, an atomic layer deposition (ALD) method, and a vacuum evaporation method. As an example of a thermal CVD method, a metal organic chemical vapor deposition (MOCVD) method can be given. It is particularly preferable that the oxide semiconductor film of one embodiment of the present invention be formed with use of a sputtering apparatus because the oxide semiconductor film can have a high film density.
Here, the film density of the oxide semiconductor film of one embodiment of the present invention is described with reference to
First, methods for fabricating Samples A1 to A12 are described below.
Sample A1 is a sample in which a 100-nm-thick oxide semiconductor film containing indium, gallium, and zinc (hereinafter, the film is referred to as an IGZO film) is deposited over a glass substrate. The deposition conditions of the IGZO film were as follows: the substrate temperature was room temperature (R.T.); an argon gas with a flow rate of 180 sccm and an oxygen gas with a flow rate of 20 sccm were introduced into a chamber of a sputtering apparatus; the pressure was 0.6 Pa; and an alternating current (AC) power of 2.5 kW was applied to a metal oxide target containing indium, gallium, and zinc (In:Ga:Zn=4:2:4.1 [atomic ratio]). Note that the proportion of oxygen flow rate with respect to the total gas flow rate is referred to as an oxygen flow rate ratio in some cases. Thus, the oxygen flow rate ratio for fabricating Sample A1 was 10%.
Sample A2 is a sample in which a 100-nm-thick IGZO film is deposited over a glass substrate. The deposition conditions of the oxide semiconductor film in Sample A2 were as follows: an argon gas with a flow rate of 140 sccm and an oxygen gas with a flow rate of 60 sccm were introduced into a chamber of a sputtering apparatus; and the conditions other than the flow rates of the argon gas and the oxygen gas were the same as those for Sample A1 described above. Note that the oxygen flow rate ratio for fabricating Sample A2 was 30%.
Sample A3 is a sample in which a 100-nm-thick IGZO film is deposited over a glass substrate. The deposition conditions of the oxide semiconductor film in Sample A3 were as follows: an argon gas with a flow rate of 100 sccm and an oxygen gas with a flow rate of 100 sccm were introduced into a chamber of a sputtering apparatus; and the conditions other than the flow rates of the argon gas and the oxygen gas were the same as those for Sample A1 described above. Note that the oxygen flow rate ratio for fabricating Sample A3 was 50%.
Sample A4 is a sample in which a 100-nm-thick IGZO film is deposited over a glass substrate. The deposition conditions of the oxide semiconductor film in Sample A4 were as follows: the substrate temperature was 100° C.; and the conditions other than the substrate temperature were the same as those for Sample A1 described above. Note that the oxygen flow rate ratio for fabricating Sample A4 was 10%.
Sample A5 is a sample in which a 100-nm-thick IGZO film is deposited over a glass substrate. The deposition conditions of the oxide semiconductor film in Sample A5 were as follows: the substrate temperature was 100° C.; and the conditions other than the substrate temperature were the same as those for Sample A2 described above. Note that the oxygen flow rate ratio for fabricating Sample A5 was 30%.
Sample A6 is a sample in which a 100-nm-thick IGZO film is deposited over a glass substrate. The deposition conditions of the oxide semiconductor film in Sample A6 were as follows: the substrate temperature was 100° C.; and the conditions other than the substrate temperature were the same as those for Sample A3 described above. Note that the oxygen flow rate ratio for fabricating Sample A6 was 50%.
Sample A7 is a sample in which a 100-nm-thick IGZO film is deposited over a glass substrate. The deposition conditions of the oxide semiconductor film in Sample A7 were as follows: the substrate temperature was 130° C.; and the conditions other than the substrate temperature were the same as those for Sample A1 described above. Note that the oxygen flow rate ratio for fabricating Sample A7 was 10%.
Sample A8 is a sample in which a 100-nm-thick IGZO film is deposited over a glass substrate. The deposition conditions of the oxide semiconductor film in Sample A8 were as follows: the substrate temperature was 130° C.; and the conditions other than the substrate temperature were the same as those for Sample A2 described above. Note that the oxygen flow rate ratio for fabricating Sample A8 was 30%.
Sample A9 is a sample in which a 100-nm-thick IGZO film is deposited over a glass substrate. The deposition conditions of the oxide semiconductor film in Sample A9 were as follows: the substrate temperature was 130° C.; and the conditions other than the substrate temperature were the same as those for Sample A3 described above. Note that the oxygen flow rate ratio for fabricating Sample A9 was 50%.
Sample A10 is a sample in which a 100-nm-thick IGZO film is deposited over a glass substrate. The deposition conditions of the oxide semiconductor film in Sample A10 were as follows: the substrate temperature was 170° C.; and the conditions other than the substrate temperature were the same as those for Sample A1 described above. Note that the oxygen flow rate ratio for fabricating Sample A10 was 10%.
Sample A11 is a sample in which a 100-nm-thick IGZO film is deposited over a glass substrate. The deposition conditions of the oxide semiconductor film in Sample A11 were as follows: the substrate temperature was 170° C.; and the conditions other than the substrate temperature were the same as those for Sample A2 described above. Note that the oxygen flow rate ratio for fabricating Sample A11 was 30%.
Sample A12 is a sample in which a 100-nm-thick IGZO film is deposited over a glass substrate. The deposition conditions of the oxide semiconductor film in Sample A12 were as follows: the substrate temperature was 170° C.; and the conditions other than the substrate temperature were the same as those for Sample A3 described above. Note that the oxygen flow rate ratio for fabricating Sample A12 was 50%.
Table 1 shows the deposition conditions and film densities of the oxide semiconductor films in Samples A1 to A12.
Note that X-ray reflectometry (XRR) was used for measurement of the film densities of the oxide semiconductor films.
As shown in
The ideal film density of the oxide semiconductor film satisfying In:Ga:Zn=1:1:1 [atomic ratio] is 6.357 g/cm3 that is the ideal density of single crystal InGaZnO4. On the other hand, the oxide semiconductor satisfying In:Ga:Zn=4:2:3 [atomic ratio] has no ideal crystal structure. Note that Non-Patent Document 1 discloses that the density of crystal powder satisfying In:Ga:Zn=4:2:3 [atomic ratio] is 6.462 g/cm3. Thus, in this specification and the like, the ideal film density of the oxide semiconductor film satisfying In:Ga:Zn=4:2:3 [atomic ratio] is assumed to be 6.462 g/cm3, on the basis of the density of crystal powder satisfying In:Ga:Zn=4:2:3 [atomic ratio].
However, in some cases, the deposited oxide semiconductor film has a composition different from that represented by In:Ga:Zn=4:2:3 [atomic ratio] or a crystal structure different from that of a single crystal. Alternatively, a slight error is caused in the film density of the deposited oxide semiconductor film in some cases, depending on the measurement accuracy or analysis accuracy in measuring the film density of the deposited oxide semiconductor by XRR. Thus, the ideal density of the oxide semiconductor film satisfying In:Ga:Zn=4:2:3 [atomic ratio] has a margin of deviation of ±3% of 6.462 g/cm3. In other words, the ideal film density of the oxide semiconductor film satisfying In:Ga:Zn=4:2:3 [atomic ratio] is higher than or equal to 6.268 g/cm3 and lower than or equal to 6.656 g/cm3.
When the thickness of the oxide semiconductor film is thin, e.g., less than or equal to 50 nm, the film density of the oxide semiconductor film cannot be measured accurately in some cases. However, it is sometimes possible to estimate the film density of the oxide semiconductor film on some level by measuring the etching speed (also referred to as etching rate) of the oxide semiconductor film.
The etching rate of the oxide semiconductor film of one embodiment of the present invention is described with reference to
According to
Next, the oxide semiconductor films in Samples A1 to A12 described above were analyzed by X-ray diffraction (XRD), whereby the crystallinity of the oxide semiconductor films was evaluated.
The XRD measurement results of Samples A1 to A12 are shown in
As shown in
From the XRD measurement results shown in
As shown in
Next, a composition, structure, and the like of the oxide semiconductor film of one embodiment of the present invention are described with reference to
First, composition of an oxide semiconductor film is described.
The oxide semiconductor film contains indium (In), M (M is Al, Ga, Y, or Sn), and zinc (Zn) as described above.
Although the element M is aluminum, gallium, yttrium or tin, other the above, the following elements can be used as the element M: boron; silicon; titanium; iron; nickel; germanium; zirconium; molybdenum; lanthanum; cerium; neodymium; hafnium; tantalum; tungsten; and magnesium. Note that two or more of the above elements may be used in combination as the element M
Next, preferred ranges of the atomic ratio of indium, the element M, and zinc contained in an oxide semiconductor according to the present invention are described with reference to
In
Dashed-dotted lines correspond to a line representing the atomic ratio of [In]:[M]:[Zn]=1:1:β(β≧0), a line representing the atomic ratio of [In]:[M]:[Zn]=1:2:β, a line representing the atomic ratio of [In]:[M]:[Zn]=1:3:β, a line representing the atomic ratio of [In]:[M]:[Zn]=1:4:β, a line representing the atomic ratio of [In]:[M]:[Zn]=2:1:β, and a line representing the atomic ratio of [In]:[M]:[Zn]=5:1:β.
Dashed-double dotted lines corresponds to a line representing the atomic ratio of [In]:[M]:[Zn]=(1+γ):2:(1−γ)(−1≦γ≦1). The oxide semiconductor shown in
InMZnO4 has a layered crystal structure (also referred to as a layered structure) and includes one layer that contains indium and oxygen (hereinafter referred to as an In layer) for every two (M,Zn) layers that contain the element M, zinc, and oxygen, as shown in
Indium and the element M can be replaced with each other. Therefore, when the element M in the (M,Zn) layer is replaced with indium, the layer can also be referred to as an (In,M,Zn) layer. In that case, a layered structure that contains one In layer for every two (In,M,Zn) layers is obtained.
An oxide semiconductor whose atomic ratio [In]:[M]:[Zn] is 1:1:2 has a layered structure that contains one In layer for every three (M,Zn) layers. In other words, if [Zn] is higher than [In] and [M], the proportion of the (M,Zn) layer to the In layer becomes higher when the oxide semiconductor is crystallized.
Note that in the case where the number of (M,Zn) layers with respect to In layer is not an integer in the oxide semiconductor, the oxide semiconductor might have plural kinds of layered structures where the number of (M,Zn) layers with respect to In layer is an integer. For example, in the case of [In]:[M]:[Zn]=1:1:1.5, the oxide semiconductor might have the following layered structures: a layered structure of one In layer for every two (M,Zn) layers and a layered structure of one In layer for every three(M,Zn) layers.
For example, in the case where the oxide semiconductor is deposited with a sputtering apparatus, a film having an atomic ratio deviated from the atomic ratio of a target is formed. In particular, [Zn] in the film might be lower than [Zn] in the target depending on the substrate temperature in deposition.
A plurality of phases (e.g., two phases or three phases) exist in the oxide semiconductor in some cases. For example, with an atomic ratio [In]:[M]:[Zn] that is in the neighborhood of 0:2:1, two phases of a spinel crystal structure and a layered crystal structure are likely to exist.
In addition, with an atomic ratio [In]:[M]:[Zn] that in the neighborhood of 1:0:0, two phases of a bixbyite crystal structure and a layered crystal structure are likely to exist. In the case where a plurality of phases exist in the oxide semiconductor, a grain boundary might be formed between different crystal structures.
In addition, the oxide semiconductor containing indium in a higher proportion can have high carrier mobility (electron mobility).
In contrast, when the indium content and the zinc content in an oxide semiconductor become lower, carrier mobility becomes lower. Thus, with an atomic ratio of [In]:[M]:[Zn]=0:1:0 and neighborhoods thereof (e.g., a region C in
Accordingly, an oxide semiconductor in one embodiment of the present invention preferably has an atomic ratio represented by a region A in
A region B in
Note that conditions where a layered structure of an oxide semiconductor is formed are not uniquely determined by the atomic ratio. There is a difference in the degree of difficulty in forming a layered structure among atomic ratios. Even with the same atomic ratio, whether a layered structure is formed or not depends on a formation condition. Therefore, the illustrated regions show atomic ratios at which a layered structure of an oxide semiconductor can be formed; boundaries of the regions A to C are not clear.
<1-6. Structure in which Oxide Semiconductor Film is Used for Transistor>
Next, a structure in which the oxide semiconductor film is used for a transistor is described.
Note that when the oxide semiconductor film is used for a transistor, carrier scattering or the like at a grain boundary can be reduced as compared with a transistor using polycrystalline silicon in a channel region; thus, the transistor can have high field-effect mobility. In addition, the transistor can have high reliability.
Note that the oxide semiconductor film of one embodiment of the present invention has a film density higher than or equal to 6.3 g/cm3 and lower than 6.5 g/cm3. With use of the oxide semiconductor film with such a high film density for a transistor, the transistor can have high reliability.
An oxide semiconductor film with low carrier density is preferably used for a channel region of the transistor. For example, the carrier density of the oxide semiconductor film is preferably higher than or equal to 1×105 cm−3 and lower than 1×1018 cm−3, further preferably higher than or equal to 1×107 cm−3 and lower than or equal to 1×1017 cm−3, still further preferably higher than or equal to 1×109 cm−3 and lower than or equal to 5×1016 cm−3, yet further preferably higher than or equal to 1×1010 cm−3 and lower than or equal to 1×1016 cm−3, and yet still preferably higher than or equal to 1×1011 cm−3 and lower than or equal to 1×1015 cm−3.
A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier generation sources, and thus can have a low carrier density. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states in some cases.
In contrast, when the carrier density of the oxide semiconductor film is increased, the field-effect mobility of the transistor can be increased in some cases. For example, the carrier density of the oxide semiconductor film may be increased as far as the transistor is not in a normally-on state, whereby the field-effect mobility of the transistor can be increased. Note that in order to increase the carrier density of the oxide semiconductor film, the oxide semiconductor film has somewhat n-type conductivity. In other words, the oxide semiconductor film with the increased carrier density is referred to as a “slightly-n” oxide semiconductor film in some cases.
For example, in the case where the voltage (Vg) applied to a gate of the transistor is higher than 0 V and lower than or equal to 30 V, the carrier density of the oxide semiconductor film is preferably higher than 1×1016 cm−3 and lower than 1×1018 cm−3, and further preferably, higher than 1×1016 cm−3 and lower than or equal to 1×1017 cm−3.
Charges trapped by the defect states in the oxide semiconductor film take a long time to be released and may behave like fixed charges. Thus, the transistor in which a channel region is formed in the oxide semiconductor film having a high density of defect states might have unstable electrical characteristics.
To obtain stable electrical characteristics of the transistor, it is effective to reduce the concentration of impurities in the oxide semiconductor film. In order to reduce the concentration of impurities in the oxide semiconductor film, the concentration of impurities in a film that is adjacent to the oxide semiconductor film is preferably reduced. As examples of the impurities, hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, silicon, and the like are given.
Here, the influence of impurities in the oxide semiconductor film will be described.
When silicon or carbon that is one of Group 14 elements is contained in the oxide semiconductor film, defect states are formed in the oxide semiconductor film. Thus, the concentration of silicon or carbon (measured by secondary ion mass spectrometry (SIMS)) in the oxide semiconductor film and around an interface with the oxide semiconductor film is set lower than or equal to 2×1018 atoms/cm3, and preferably lower than or equal to 2×1017 atoms/cm3.
When the oxide semiconductor film contains alkali metal or alkaline earth metal, defect states are formed and carriers are generated, in some cases. Thus, a transistor including an oxide semiconductor film which contains alkali metal or alkaline earth metal is likely to be normally on. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the oxide semiconductor film. Specifically, the concentration of alkali metal or alkaline earth metal of the oxide semiconductor film, which is measured by SIMS, is lower than or equal to 1×1018 atoms/cm3, preferably lower than or equal to 2×1016 atoms/cm3.
When the oxide semiconductor film contains nitrogen, the oxide semiconductor film easily becomes n-type by generation of electrons serving as carriers and an increase of carrier density. Thus, a transistor whose semiconductor includes an oxide semiconductor film that contains nitrogen is likely to be normally-on. For this reason, nitrogen in the oxide semiconductor film is preferably reduced as much as possible; for example, the concentration of nitrogen in the oxide semiconductor film measured by SIMS is set to be lower than 5×1019 atoms/cm3, preferably lower than or equal to 5×1018 atoms/cm3, further preferably lower than or equal to 1×1018 atoms/cm3, and still further preferably lower than or equal to 5×1017 atoms/cm3.
Hydrogen contained in an oxide semiconductor film reacts with oxygen bonded to a metal atom to be water, and thus causes an oxygen vacancy, in some cases. Entry of hydrogen into the oxygen vacancy generates an electron serving as a carrier in some cases. Furthermore, in some cases, bonding of part of hydrogen to oxygen bonded to a metal atom causes generation of an electron serving as a carrier. Thus, a transistor including an oxide semiconductor film that contains hydrogen is likely to be normally on. Accordingly, it is preferable that hydrogen in the oxide semiconductor film be reduced as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor film measured by SIMS is set lower than 1×1020 atoms/cm3, preferably lower than 1×1019 atoms/cm3, further preferably lower than 5×1018 atoms/cm3, and still further preferably lower than 1×1018 atoms/cm3.
When an oxide semiconductor film with sufficiently reduced impurity concentration is used for a channel formation region in a transistor, the transistor can have stable electrical characteristics.
The energy gap of the oxide semiconductor film is preferably 2 eV or more or 2.5 eV or more.
The thickness of the oxide semiconductor film is greater than or equal to 3 nm and less than or equal to 200 nm, preferably greater than or equal to 3 nm and less than or equal to 100 nm, further preferably greater than or equal to 3 nm and less than or equal to 60 nm.
When the oxide semiconductor film is an In-M-Zn oxide, as the atomic ratio of metal elements in a sputtering target used for formation of the In-M-Zn oxide, In:M:Zn=1:1:0.5, In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:1.5, In:M:Zn=2:1:2.3, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:4.1, In:M:Zn=5:1:7, or the like is preferable.
Note that the atomic ratios of metal elements in the formed oxide semiconductor films may each vary from the above atomic ratio of metal elements in the sputtering target within a range of approximately ±40%. For example, when a sputtering target with an atomic ratio of In:Ga:Zn=4:2:4.1 is used, the atomic ratio of In to Ga and Zn in the oxide semiconductor film may be 4:2:3 or in the neighborhood of 4:2:3. In the case where a sputtering target whose atomic ratio of In to Ga and Zn is 5:1:7 is used, the atomic ratio of In to Ga and Zn in the deposited oxide semiconductor film may be in the neighborhood of 5:1:6.
Next, a structure of the oxide semiconductor film is described.
An oxide semiconductor film is classified into a single crystal oxide semiconductor film and a non-single-crystal oxide semiconductor film. Examples of a non-single-crystal oxide semiconductor include a c-axis-aligned crystalline oxide semiconductor (CAAC-OS), a polycrystalline oxide semiconductor, a nanocrystalline oxide semiconductor (nc-OS), an amorphous-like oxide semiconductor (a-like OS), and an amorphous oxide semiconductor.
From another perspective, an oxide semiconductor film is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor. Examples of a crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and an nc-OS.
An amorphous structure is generally thought to be isotropic and have no non-uniform structure, to be metastable and not to have fixed positions of atoms, to have a flexible bond angle, and to have a short-range order but have no long-range order, for example.
In other words, a stable oxide semiconductor cannot be regarded as a completely amorphous oxide semiconductor. Moreover, an oxide semiconductor that is not isotropic (e.g., an oxide semiconductor that has a periodic structure in a microscopic region) cannot be regarded as a completely amorphous oxide semiconductor. In contrast, an a-like OS, which is not isotropic, has an unstable structure that contains a void. Because of its instability, an a-like OS is close to an amorphous oxide semiconductor in terms of physical properties.
First, a CAAC-OS is described.
A CAAC-OS is one of oxide semiconductors having a plurality of c-axis aligned crystal parts (also referred to as pellets).
Analysis of a CAAC-OS by XRD is described. For example, when the structure of a CAAC-OS including an InGaZnO4 crystal that is classified into the space group R-3m is analyzed by an out-of-plane method, a peak appears at a diffraction angle (2θ) of around 31° as shown in
On the other hand, in structural analysis of the CAAC-OS by an in-plane method in which an X-ray is incident on the CAAC-OS in a direction parallel to the formation surface, a peak appears at a 2θ of around 56°. This peak is derived from the (110) plane of the InGaZnO4 crystal. When analysis (φ scan) is performed with 2θ fixed at around 56° and with the sample rotated using a normal vector to the sample surface as an axis (0 axis), as shown in
Next, a CAAC-OS analyzed by electron diffraction will be described. For example, when an electron beam with a probe diameter of 300 nm is incident on a CAAC-OS including an InGaZnO4 crystal in a direction parallel to the formation surface of the CAAC-OS, a diffraction pattern (also referred to as a selected-area electron diffraction pattern) shown in
In a combined analysis image (also referred to as a high-resolution TEM image) of a bright-field image and a diffraction pattern of a CAAC-OS, which is obtained using a transmission electron microscope (TEM), a plurality of pellets can be observed. However, even in the high-resolution TEM image, a boundary between pellets, that is, a crystal grain boundary is not clearly observed in some cases. Thus, in the CAAC-OS, a reduction in electron mobility due to the grain boundary is less likely to occur.
In
In
As described above, the CAAC-OS has c-axis alignment, its pellets (nanocrystals) are connected in an a-b plane direction, and the crystal structure has distortion. For this reason, the CAAC-OS can also be referred to as an oxide semiconductor including a c-axis-aligned a-b-plane-anchored (CAA) crystal.
The CAAC-OS is an oxide semiconductor with high crystallinity. Entry of impurities, formation of defects, or the like might decrease the crystallinity of an oxide semiconductor. This means that the CAAC-OS has small amounts of impurities and defects (e.g., oxygen vacancies).
Note that the impurity means an element other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element. For example, an element (specifically, silicon or the like) having higher strength of bonding to oxygen than a metal element included in an oxide semiconductor extracts oxygen from the oxide semiconductor, which results in disorder of the atomic arrangement and reduced crystallinity of the oxide semiconductor. A heavy metal such as iron or nickel, argon, carbon dioxide, or the like has a large atomic radius (or molecular radius), and thus disturbs the atomic arrangement of the oxide semiconductor and decreases crystallinity.
The characteristics of an oxide semiconductor having impurities or defects might be changed by light, heat, or the like. For example, impurities contained in the oxide semiconductor might serve as carrier traps or carrier generation sources. For example, oxygen vacancy in the oxide semiconductor might serve as a carrier trap or serve as a carrier generation source when hydrogen is captured therein.
The CAAC-OS having small amounts of impurities and oxygen vacancies is an oxide semiconductor with low carrier density. Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. A CAAC-OS has a low impurity concentration and a low density of defect states. Thus, the CAAC-OS can be referred to as an oxide semiconductor having stable characteristics.
[nc-OS]
Next, an nc-OS is described.
Analysis of an nc-OS by XRD is described. When the structure of an nc-OS is analyzed by an out-of-plane method, a peak indicating orientation does not appear. That is, a crystal of an nc-OS does not have orientation.
For example, when an electron beam with a probe diameter of 50 nm is incident on a 34-nm-thick region of a thinned nc-OS including an InGaZnO4 crystal in the direction parallel to the formation surface, a ring-like diffraction pattern (a nanobeam electron diffraction pattern) is observed as shown in
Furthermore, an electron diffraction pattern in which spots are arranged in an approximately regular hexagonal shape is observed in some cases as shown in
As described above, in the nc-OS, a microscopic region (for example, a region with a size greater than or equal to 1 nm and less than or equal to 10 nm, in particular, a region with a size greater than or equal to 1 nm and less than or equal to 3 nm) has a periodic atomic arrangement. There is no regularity of crystal orientation between different pellets in the nc-OS. Thus, the orientation of the whole film is not observed. Accordingly, the nc-OS cannot be distinguished from an a-like OS or an amorphous oxide semiconductor, depending on an analysis method.
Since there is no regularity of crystal orientation between the pellets (nanocrystals) as mentioned above, the nc-OS can also be referred to as an oxide semiconductor including random aligned nanocrystals (RANC) or an oxide semiconductor including non-aligned nanocrystals (NANC).
The nc-OS is an oxide semiconductor that has high regularity as compared with an amorphous oxide semiconductor. Therefore, the nc-OS is likely to have a lower density of defect states than an a-like OS and an amorphous oxide semiconductor. Note that there is no regularity of crystal orientation between different pellets in the nc-OS. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.
[a-like OS]
An a-like OS has a structure intermediate between those of the nc-OS and the amorphous oxide semiconductor.
The a-like OS has an unstable structure because it contains a void. To verify that an a-like OS has an unstable structure as compared with a CAAC-OS and an nc-OS, a change in structure caused by electron irradiation is described below.
An a-like OS, an nc-OS, and a CAAC-OS are prepared as samples. Each of the samples is an In—Ga—Zn oxide.
First, a high-resolution cross-sectional TEM image of each sample is obtained. The high-resolution cross-sectional TEM images show that all the samples have crystal parts.
It is known that a unit cell of an InGaZnO4 crystal has a structure in which nine layers including three In—O layers and six Ga—Zn—O layers are stacked in the c-axis direction. Accordingly, the spacing between these adjacent layers is equivalent to the lattice spacing on the (009) plane (also referred to as a d value). The value is calculated to be 0.29 nm from crystal structure analysis. Accordingly, a portion where the spacing between lattice fringes is greater than or equal to 0.28 nm and less than or equal to 0.30 nm is regarded as a crystal part of InGaZnO4 in the following description. Each of lattice fringes corresponds to the a-b plane of the InGaZnO4 crystal.
In this manner, growth of the crystal part in the a-like OS is induced by electron irradiation. In contrast, in the nc-OS and the CAAC-OS, growth of the crystal part is hardly induced by electron irradiation. Therefore, the a-like OS has an unstable structure as compared with the nc-OS and the CAAC-OS.
The a-like OS has a lower density than the nc-OS and the CAAC-OS because it contains a void. Specifically, the density of the a-like OS is higher than or equal to 78.6% and lower than 92.3% of the density of the single crystal oxide semiconductor having the same composition. The density of each of the nc-OS and the CAAC-OS is higher than or equal to 92.3% and lower than 100% of the density of the single crystal oxide semiconductor having the same composition. Note that it is difficult to deposit an oxide semiconductor having a density of lower than 78% of the density of the single crystal oxide semiconductor.
As described above, in the case of an oxide semiconductor whose atomic ratio of In to Ga and Zn is 1:1:1, the density of single-crystal InGaZnO4 is 6.357 g/cm3. Accordingly, in the case of the oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, for example, the density of the a-like OS is higher than or equal to 5.0 g/cm3 and lower than 5.9 g/cm3. Furthermore, for example, in the case of the oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, the density of each of the nc-OS and the CAAC-OS is higher than or equal to 5.9 g/cm3 and lower than 6.3 g/cm3.
Note that in the case where an oxide semiconductor having a certain composition does not exist in a single crystal structure, single crystal oxide semiconductors with different compositions are combined at an adequate ratio, which makes it possible to calculate density equivalent to that of a single crystal oxide semiconductor with the desired composition. The density of a single crystal oxide semiconductor having the desired composition can be estimated using a weighted average according to the combination ratio of the single crystal oxide semiconductors with different compositions. Note that it is preferable to use as few kinds of single crystal oxide semiconductors as possible to estimate the density.
As described above, oxide semiconductors have various structures and various properties. Note that an oxide semiconductor may be a stacked layer including two or more films of an amorphous oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS, for example.
Note that the structure described in this embodiment can be used in appropriate combination with any of the structures described in the other embodiments or examples.
In this embodiment, a transistor that can be used for a semiconductor device of one embodiment of the present invention will be described in detail.
In this embodiment, a transistor with a top-gate structure is described with reference to
The transistor 100 illustrated in
Furthermore, the insulating film 116 contains nitrogen or hydrogen. The insulating film 116 is in contact with the source region 108s and the drain region 108d, so that nitrogen or hydrogen that is contained in the insulating film 116 is added to the source region 108s and the drain region 108d. The source region 108s and the drain region 108d each have a high carrier density when nitrogen or hydrogen is added thereto.
The transistor 100 may further include an insulating film 118 over the insulating film 116, a conductive film 120a electrically connected to the source region 108s through an opening 141a provided in the insulating films 116 and 118, and a conductive film 120b electrically connected to the drain region 108d through an opening 141b provided in the insulating films 116 and 118.
In this specification and the like, the insulating film 104 may be referred to as a first insulating film, the insulating film 110 may be referred to as a second insulating film, the insulating film 116 may be referred to as a third insulating film, and the insulating film 118 may be referred to as a fourth insulating film. The conductive film 112 functions as a gate electrode, the conductive film 120a functions as a source electrode, and the conductive film 120b functions as a drain electrode.
The insulating film 110 functions as a gate insulating film. The insulating film 110 includes an excess oxygen region. Since the insulating film 110 includes the excess oxygen region, excess oxygen can be supplied to the channel region 108i included in the oxide semiconductor film 108. As a result, oxygen vacancies that might be formed in the channel region 108i can be filled with excess oxygen, which can provide a highly reliable semiconductor device.
To supply excess oxygen to the oxide semiconductor film 108, excess oxygen may be supplied to the insulating film 104 that is formed under the oxide semiconductor film 108. However, in that case, excess oxygen contained in the insulating film 104 might also be supplied to the source region 108s and the drain region 108d included in the oxide semiconductor film 108. When excess oxygen is supplied to the source region 108s and the drain region 108d, the resistance of the source region 108s and the drain region 108d might be increased.
In contrast, in the structure in which the insulating film 110 formed over the oxide semiconductor film 108 contains excess oxygen, excess oxygen can be selectively supplied only to the channel region 108i. Alternatively, the carrier density of the source and drain regions 108s and 108d can be selectively increased after excess oxygen is supplied to the channel region 108i and the source and drain regions 108s and 108d, in which case an increase in the resistance of the source and drain regions 108s and 108d can be prevented.
Furthermore, each of the source region 108s and the drain region 108d included in the oxide semiconductor film 108 preferably contains an element that forms an oxygen vacancy or an element that is bonded to an oxygen vacancy. Typical examples of the element that forms an oxygen vacancy or the element that is bonded to an oxygen vacancy include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and a rare gas. Typical examples of the rare gas element are helium, neon, argon, krypton, and xenon. The element that forms an oxygen vacancy is diffused from the insulating film 116 to the source region 108s and the drain region 108d in the case where the insulating film 116 contains one or more such elements. In addition or alternatively, the element that forms an oxygen vacancy is added to the source region 108s and the drain region 108d by impurity addition treatment.
An impurity element added to the oxide semiconductor film cuts a bond between a metal element and oxygen in the oxide semiconductor film, so that an oxygen vacancy is formed. Alternatively, when the impurity element is added to the oxide semiconductor film, oxygen bonded to a metal element in the oxide semiconductor film is bonded to the impurity element, and the oxygen is released from the metal element, whereby an oxygen vacancy is formed. As a result, the oxide semiconductor film has a higher carrier density and thus the conductivity thereof becomes higher.
Next, details of other components included in the semiconductor device illustrated in
A material having heat resistance high enough to withstand heat treatment in the manufacturing process can be used for the substrate 102.
Specifically, non-alkali glass, soda-lime glass, potash glass, crystal glass, quartz, sapphire, or the like can be used. Alternatively, an inorganic insulating film may be used. Examples of the inorganic insulating film include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and an aluminum oxide film.
The non-alkali glass preferably has a thickness greater than or equal to 0.2 mm and less than or equal to 0.7 mm, for example. The non-alkali glass may be polished to obtain the above thickness.
Using the non-alkali glass, a large-sized glass substrate having any of the following sizes can be used: the 6th generation (1500 mm×1850 mm), the 7th generation (1870 mm×2200 mm), the 8th generation (2200 mm×2400 mm), the 9th generation (2400 mm×2800 mm), and the 10th generation (2950 mm×3400 mm). Thus, a large-sized display device can be manufactured.
Alternatively, as the substrate 102, a single-crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon or silicon carbide, a compound semiconductor substrate made of silicon germanium or the like, an SOI substrate, or the like may be used.
Alternatively, an inorganic material such as metal may be used as the substrate 102. Examples of the inorganic material such as a metal include stainless steel or aluminum.
Alternatively, for the substrate 102, an organic material such as a resin, a resin film, or plastic may be used. Examples of the resin film include polyester, polyolefin, polyamide (e.g., nylon or aramid), polyimide, polycarbonate, polyurethane, an acrylic resin, an epoxy resin, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (PES), and a resin having a siloxane bond.
Alternatively, for the substrate 102, a composite material of a combination of an inorganic material and an organic material may be used. Examples of the composite material include a resin film to which a metal plate or a thin glass plate is bonded, a resin film into which a fibrous or particulate metal or a fibrous or particulate glass is dispersed, and an inorganic material into which a fibrous or particulate resin is dispersed.
Note that the substrate 102 may be formed using one or more of an insulating film, a semiconductor film, and a conductive film as long as it can at least support a film or a layer formed thereover and thereunder.
The insulating film 104 can be formed by a sputtering method, a CVD method, an evaporation method, a pulsed laser deposition (PLD) method, a printing method, a coating method, or the like as appropriate. For example, the insulating film 104 can be formed to have a single-layer structure or stacked-layer structure including an oxide insulating film and/or a nitride insulating film. To improve the properties of the interface with the oxide semiconductor film 108, at least a region of the insulating film 104 which is in contact with the oxide semiconductor film 108 is preferably formed using an oxide insulating film. When the insulating film 104 is formed using an oxide insulating film from which oxygen is released by heating, oxygen contained in the insulating film 104 can be moved to the oxide semiconductor film 108 by heat treatment.
The thickness of the insulating film 104 can be greater than or equal to 50 nm, greater than or equal to 100 nm and less than or equal to 3000 nm, or greater than or equal to 200 nm and less than or equal to 1000 nm. By increasing the thickness of the insulating film 104, the amount of oxygen released from the insulating film 104 can be increased, and interface states at the interface between the insulating film 104 and the oxide semiconductor film 108 and oxygen vacancies included in the channel region 108i of the oxide semiconductor film 108 can be reduced.
For example, the insulating film 104 can be formed to have a single-layer structure or stacked-layer structure including silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, a Ga—Zn oxide, or the like. In this embodiment, the insulating film 104 has a stacked-layer structure including a silicon nitride film and a silicon oxynitride film. With the insulating film 104 having such a stack-layer structure including a silicon nitride film as a lower layer and a silicon oxynitride film as an upper layer, oxygen can be efficiently introduced into the oxide semiconductor film 108.
As the oxide semiconductor film 108, the oxide semiconductor film described in Embodiment 1 can be used.
It is preferable that the oxide semiconductor film 108 be formed by a sputtering method because the film density can be high. In the case where the oxide semiconductor film 108 is formed by a sputtering method, a rare gas (typically argon), oxygen, or a mixed gas of a rare gas and oxygen is used as a sputtering gas, as appropriate. In addition, increasing the purity of a sputtering gas is necessary. For example, as an oxygen gas or an argon gas used for a sputtering gas, a gas that is highly purified to have a dew point of −60° C. or lower, preferably −100° C. or lower, is used, whereby entry of moisture or the like into the oxide semiconductor film 108 can be minimized.
When the oxide semiconductor film 108 is formed by a sputtering method, each chamber of a sputtering apparatus is preferably evacuated to a high vacuum (to the degree of approximately 5×10−7 Pa to 1×10−4 Pa) by an adsorption vacuum pump such as a cryopump so that water and the like acting as impurities for the oxide semiconductor film 108 are removed as much as possible. The partial pressure of gas molecules corresponding to H2O (corresponding to molecules with a m/z of 18) in the chamber is particularly set to be lower than or equal to 1×10−4 Pa, further preferably, lower than or equal to 5×10−5 Pa in a standby state of the sputtering apparatus.
The insulating film 110 functions as a gate insulating film of the transistor 100. In addition, the insulating film 110 has a function of supplying oxygen to the oxide semiconductor film 108, particularly to the channel region 108i. The insulating film 110 can be formed to have a single-layer structure or a stacked-layer structure of an oxide insulating film or a nitride insulating film, for example. To improve the interface properties with the oxide semiconductor film 108, a region which is in the insulating film 110 and in contact with the oxide semiconductor film 108 is preferably formed using at least an oxide insulating film. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride may be used for the insulating film 110.
The thickness of the insulating film 110 can be greater than or equal to 5 nm and less than or equal to 400 nm, greater than or equal to 5 nm and less than or equal to 300 nm, or greater than or equal to 10 nm and less than or equal to 250 nm.
It is preferable that the insulating film 110 have few defects and typically have as few signals observed by electron spin resonance (ESR) spectroscopy as possible. Examples of the signals include a signal due to an E′ center observed at a g-factor of 2.001. Note that the E′ center is due to the dangling bond of silicon. As the insulating film 110, a silicon oxide film or a silicon oxynitride film whose spin density of a signal due to the E′ center is lower than or equal to 3×1017 spins/cm3 and preferably lower than or equal to 5×1016 spins/cm3 may be used.
In addition to the above-described signal, a signal due to nitrogen dioxide (NO2) might be observed in the insulating film 110. The signal is split into three signals according to nuclear spin of N; a first signal, a second signal, and a third signal. The first signal is observed at a g-factor of greater than or equal to 2.037 and less than or equal to 2.039. The second signal is observed at a g-factor of greater than or equal to 2.001 and less than or equal to 2.003. The third signal is observed at a g-factor of greater than or equal to 1.964 and less than or equal to 1.966.
It is suitable to use an insulating film whose spin density due to nitrogen dioxide (NO2) is higher than or equal to 1×1017 spins/cm3 and lower than 1×1018 spins/cm3 as the insulating film 110, for example.
Note that a nitrogen oxide (NOx) such as a nitrogen dioxide (NO2) forms a level in the insulating film 110. The level is positioned in the energy gap of the oxide semiconductor film 108. Thus, when nitrogen oxide (NOx) is diffused to the interface between the insulating film 110 and the oxide semiconductor film 108, an electron might be trapped by the level on the insulating film 110 side. As a result, the trapped electron remains in the vicinity of the interface between the insulating film 110 and the oxide semiconductor film 108; thus, the threshold voltage of the transistor is shifted in the positive direction. Accordingly, the use of a film with a low nitrogen oxide content as the insulating film 110 can reduce a shift of the threshold voltage of the transistor.
As an insulating film that releases a small amount of nitrogen oxide (NOx), for example, a silicon oxynitride film can be used. The silicon oxynitride film releases more ammonia than nitrogen oxide (NOx) in thermal desorption spectroscopy (TDS); the typical released amount of ammonia is greater than or equal to 1×1018 cm−3 and less than or equal to 5×1019 cm−3. Note that the released amount of ammonia is the total amount of ammonia released by heat treatment in a range from 50° C. to 650° C. or a range from 50° C. to 550° C. in TDS.
Since nitrogen oxide (NOx) reacts with ammonia and oxygen in heat treatment, the use of an insulating film that releases a large amount of ammonia reduces nitrogen oxide (NOx).
Note that in the case where the insulating film 110 is analyzed by SIMS, the nitrogen concentration in the film is preferably lower than or equal to 6×1020 atoms/cm3.
The insulating film 110 may be formed using a high-k material such as hafnium silicate (HfSiOx), hafnium silicate to which nitrogen is added (HfSixOyNz), hafnium aluminate to which nitrogen is added (HfAlxOyNz), or hafnium oxide. The use of such a high-k material enables a reduction in gate leakage current of a transistor.
The insulating film 116 contains nitrogen or hydrogen. The insulating film 116 may contain fluorine. The insulating film 116 is a nitride insulating film, for example. The nitride insulating film can be formed using silicon nitride, silicon nitride oxide, silicon oxynitride, silicon nitride fluoride, silicon fluoronitride, or the like. The hydrogen concentration in the insulating film 116 is preferably higher than or equal to 1×1022 atoms/cm3. Furthermore, the insulating film 116 is in contact with the source region 108s and the drain region 108d of the oxide semiconductor film 108. Thus, the concentration of an impurity (nitrogen or hydrogen) in the source region 108s and the drain region 108d in contact with the insulating film 116 is increased, leading to an increase in the carrier density of the source region 108s and the drain region 108d.
As the insulating film 118, an oxide insulating film can be used. Alternatively, a stack including an oxide insulating film and a nitride insulating film can be used as the insulating film 118. The insulating film 118 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, gallium oxide, or Ga—Zn oxide.
Furthermore, the insulating film 118 preferably functions as a barrier film against hydrogen, water, and the like from the outside.
The thickness of the insulating film 118 can be greater than or equal to 30 nm and less than or equal to 500 nm, or greater than or equal to 100 nm and less than or equal to 400 nm.
The conductive films 112, 120a, and 120b can be formed by a sputtering method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, a thermal CVD method, or the like. Furthermore, as the conductive films 112, 120a, and 120b, a conductive metal film, a conductive film that has a function of reflecting visible light, or a conductive film having a function of transmitting visible light may be used.
A material containing a metal element selected from aluminum, gold, platinum, silver, copper, chromium, tantalum, titanium, molybdenum, tungsten, nickel, iron, cobalt, palladium, and manganese can be used for the metal film having conductivity. Alternatively, an alloy containing any of the above metal elements may be used.
For the metal film having conductivity, specifically a two-layer structure in which a copper film is stacked over a titanium film, a two-layer structure in which a copper film is stacked over a titanium nitride film, a two-layer structure in which a copper film is stacked over a tantalum nitride film, or a three-layer structure in which a titanium film, a copper film, and a titanium film are stacked in this order may be used. In particular, a conductive film containing a copper element is preferably used because the resistance can be reduced. As an example of the conductive film containing a copper element, an alloy film containing copper and manganese is given. The alloy film is preferable because it can be processed by a wet etching method.
A tantalum nitride film is preferably used as each of the conductive films 112, 120a, and 120b. Such a tantalum nitride film has conductivity and a high barrier property against copper or hydrogen. The tantalum nitride film can be used most preferably as a metal film in contact with the oxide semiconductor film 108 or a metal film in the vicinity of the oxide semiconductor film 108 because the amount of hydrogen released from the tantalum nitride film is small.
As the conductive film having conductivity, a conductive macromolecule or a conductive polymer may be used.
For the conductive film having a function of reflecting visible light, a material containing a metal element selected from gold, silver, copper, and palladium can be used. In particular, a conductive film containing a silver element is preferably used because reflectance of visible light can be improved.
For the conductive film having a function of transmitting visible light, a material containing an element selected from indium, tin, zinc, gallium, and silicon can be used. Specifically, an In oxide, a Zn oxide, an In—Sn oxide (also referred to as ITO), an In—Sn—Si oxide (also referred to as ITSO), an In—Zn oxide, an In—Ga—Zn oxide, or the like can be used.
As the conductive film having a function of transmitting visible light, a film containing graphene or graphite may be used. The film containing graphene can be formed in the following manner: a film containing graphene oxide is formed and is reduced. As a reducing method, a method with application of heat, a method using a reducing agent, or the like can be employed.
The conductive films 112, 120a, and 120b can be formed by electroless plating. As a material formed by the electroless plating, one or more of Cu, Ni, Al, Au, Sn, Co, Ag, and Pd can be used. Particularly, Cu or Ag is preferable because the resistance of the conductive film can be low.
In the case where the conductive film is formed by electroless plating, a diffusion prevention film may be formed below the conductive film so as to prevent diffusion of constituent elements of the conductive film into the outside. In addition, a seed layer that enables the conductive film to grow may be formed between the diffusion prevention film and the conductive film. The diffusion prevention film can be formed by, for example, a sputtering method. As the diffusion prevention film, for example, a tantalum nitride film or a titanium nitride film can be used. The seed layer can be formed by an electroless plating method. Alternatively, the seed layer can be formed using a material the same as a material of the conductive film that can be formed by an electroless plating method.
Note that an oxide semiconductor typified by an In—Ga—Zn oxide may be used for the conductive film 112. The oxide semiconductor can have a high carrier density when nitrogen or hydrogen is supplied from the insulating film 116. In other words, the oxide semiconductor functions as an oxide conductor (OC). Accordingly, the oxide semiconductor can be used for a gate electrode.
The conductive film 112 can have, for example, a single-layer structure of an oxide conductor (OC), a single-layer structure of a metal film, or a stacked-layer structure of an oxide conductor (OC) and a metal film.
Note that it is suitable that the conductive film 112 has a single-layer structure of a light-shielding metal film or a stacked-layer structure of an oxide conductor (OC) and a light-shielding metal film because the channel region 108i formed under the conductive film 112 can be shielded from light. In the case where the conductive film 112 has a stacked-layer structure of an oxide semiconductor or an oxide conductor (OC) and a light-shielding metal film, formation of a metal film (e.g., a titanium film or a tungsten film) over the oxide semiconductor or the oxide conductor (OC) produces any of the following effects: the resistance of the oxide semiconductor or the oxide conductor (OC) is reduced by the diffusion of the constituent element of the metal film to the oxide semiconductor or oxide conductor (OC) side, the resistance is reduced by damage (e.g., sputtering damage) during the deposition of the metal film, and the resistance is reduced when oxygen vacancies are formed by the diffusion of oxygen in the oxide semiconductor or the oxide conductor (OC) to the metal film.
The thickness of the conductive films 112, 120a, and 120b can be greater than or equal to 30 nm and less than or equal to 500 nm, or greater than or equal to 100 nm and less than or equal to 400 nm.
A structural example which is different from the transistor illustrated in
The transistor 100A illustrated in
The transistor 100A includes the conductive film 106 and an opening 143 in addition to the components of the transistor 100 described above.
Note that the opening 143 is provided in the insulating films 104 and 110. The conductive film 106 is electrically connected to the conductive film 112 through the opening 143. Thus, the same potential is applied to the conductive film 106 and the conductive film 112. Note that different potentials may be applied to the conductive film 106 and the conductive film 112 without providing the opening 143. Alternatively, the conductive film 106 may be used as a light-shielding film without providing the opening 143. When the conductive film 106 is formed using a light-shielding material, for example, light irradiating the channel region 108i from the bottom can be reduced.
In the case of using the transistor 100A, the conductive film 106 functions as a first gate electrode (also referred to as bottom gate electrode), and the conductive film 112 functions as a second gate electrode (also referred to as top gate electrode). The insulating film 104 functions as a first gate insulating film, and the insulating film 110 functions as a second gate insulating film.
The conductive film 106 can be formed using a material similar to the above-described materials of the conductive films 112, 120a, and 120b. It is particularly suitable to use a material containing copper for the conductive film 106 because the resistance can be reduced. It is suitable that, for example, each of the conductive films 106, 120a, and 120b has a stacked-layer structure in which a copper film is over a titanium nitride film, a tantalum nitride film, or a tungsten film. In that case, when the transistor 100A is used as a pixel transistor and/or a driving transistor of a display device, parasitic capacitance generated between the conductive films 106 and 120a and between the conductive films 106 and 120b can be reduced. Thus, the conductive films 106, 120a, and 120b can be used not only as the first gate electrode, the source electrode, and the drain electrode of the transistor 100A, but also as power source supply wirings, signal supply wirings, connection wirings, or the like of the display device.
In this manner, the transistor 100A illustrated in
As illustrated in
Furthermore, the length of the conductive film 112 in the channel width direction is larger than the length of the oxide semiconductor film 108 in the channel width direction. In the channel width direction, the whole oxide semiconductor film 108 is covered with the conductive film 112 with the insulating film 110 interposed therebetween. Since the conductive film 112 is connected to the conductive film 106 through the opening 143 provided in the insulating films 104 and 110, a side surface of the oxide semiconductor film 108 in the channel width direction faces the conductive film 112 with the insulating film 110 interposed therebetween.
In other words, in the channel width direction of the transistor 100A, the conductive films 106 and 112 are connected to each other through the opening 143 provided in the insulating films 104 and 110, and the conductive films 106 and 112 surround the oxide semiconductor film 108 with the insulating films 104 and 110 interposed therebetween.
Such a structure enables the oxide semiconductor film 108 included in the transistor 100A to be electrically surrounded by electric fields of the conductive film 106 functioning as the first gate electrode and the conductive film 112 functioning as the second gate electrode. A device structure of a transistor, like that of the transistor 100A, in which electric fields of the first gate electrode and the second gate electrode electrically surround the oxide semiconductor film 108 in which a channel region is formed can be referred to as a surrounded channel (s-channel) structure.
Since the transistor 100A has the s-channel structure, an electric field for inducing a channel can be effectively applied to the oxide semiconductor film 108 by the conductive film 106 or the conductive film 112; thus, the current drive capability of the transistor 100A can be improved and high on-state current characteristics can be obtained. Since the on-state current can be increased, it is possible to reduce the size of the transistor 100A. Furthermore, since the transistor 100A has a structure in which the oxide semiconductor film 108 is surrounded by the conductive film 106 and the conductive film 112, the mechanical strength of the transistor 100A can be increased.
When seen in the channel width direction of the transistor 100A, an opening different from the opening 143 may be formed on the side of the oxide semiconductor film 108 on which the opening 143 is not formed.
When a transistor has a pair of gate electrodes between which a semiconductor film is interposed as in the case of the transistor 100A, a signal A may be applied to one gate electrode and a fixed potential Vb may be applied to the other gate electrode. Alternatively, one of the gate electrodes may be supplied with the signal A, and the other gate electrode may be supplied with a signal B. Alternatively, one of the gate electrodes may be supplied with a fixed potential Va, and the other gate electrode may be supplied with the fixed potential Vb.
The signal A is, for example, a signal for controlling the on/off state. The signal A may be a digital signal with two kinds of potentials, a potential V1 and a potential V2 (V1>V2). For example, the potential V1 can be a high power supply potential, and the potential V2 can be a low power supply potential. The signal A may be an analog signal.
The fixed potential Vb is, for example, a potential for controlling a threshold voltage VthA of the transistor. The fixed potential Vb may be the potential V1 or the potential V2. In that case, a potential generator circuit for generating the fixed potential Vb is not necessary, which is preferable. The fixed potential Vb may be different from the potential V1 or the potential V2. When the fixed potential Vb is low, the threshold voltage VthA can be high in some cases. As a result, the drain current flowing when the gate-source voltage Vgs is 0 V can be reduced, and leakage current in a circuit including the transistor can be reduced in some cases. The fixed potential Vb may be, for example, lower than the low power supply potential. On the other hand, in some cases, the threshold voltage VthA can be low by setting the fixed potential Vb high. As a result, drain current generated when the gate-source voltage Vgs is a high power supply potential can be increased and the operating speed of the circuit including the transistor can be improved in some cases. The fixed potential Vb may be, for example, higher than the low power supply potential.
The signal B is, for example, a signal for controlling the on/off state. The signal B may be a digital signal with two kinds of potentials, a potential V3 and a potential V4 (V3>V4). For example, the potential V3 can be a high power supply potential, and the potential V4 can be a low power supply potential. The signal B may be an analog signal.
When both the signal A and the signal B are digital signals, the signal B may have the same digital value as the signal A. In this case, it may be possible to increase the on-state current of the transistor and the operating speed of the circuit including the transistor. Here, the potential V1 and the potential V2 of the signal A may be different from the potential V3 and the potential V4 of the signal B. For example, if a gate insulating film for the gate to which the signal B is input is thicker than a gate insulating film for the gate to which the signal A is input, the potential amplitude of the signal B (V3−V4) may be larger than the potential amplitude of the signal A (V1−V2). In this manner, the influence of the signal A and that of the signal B on the on/off state of the transistor can be substantially the same in some cases.
When both the signal A and the signal B are digital signals, the signal B may have a digital value different from that of the signal A. In this case, the signal A and the signal B can separately control the transistor, and thus, higher performance can be achieved. The transistor which is, for example, an n-channel transistor can function by itself as a NAND circuit, a NOR circuit, or the like in the following case: the transistor is turned on only when the signal A has the potential V1 and the signal B has the potential V3, or the transistor is turned off only when the signal A has the potential V2 and the signal B has the potential V4. The signal B may be a signal for controlling the threshold voltage VthA. For example, the potential of the signal B in a period in which the circuit including the transistor operates may be different from the potential of the signal B in a period in which the circuit does not operate. The potential of the signal B may vary depending on the operation mode of the circuit. In this case, the potential of the signal B is not necessarily changed as frequently as the potential of the signal A.
When both the signal A and the signal B are analog signals, the signal B may be an analog signal having the same potential as the signal A, an analog signal whose potential is a constant times the potential of the signal A, an analog signal whose potential is higher or lower than the potential of the signal A by a constant, or the like. In this case, it may be possible to increase the on-state current of the transistor and the operating speed of the circuit including the transistor. The signal B may be an analog signal different from the signal A. In this case, the signal A and the signal B can separately control the transistor, and thus, higher performance can be achieved.
The signal A may be a digital signal, and the signal B may be an analog signal. Alternatively, the signal A may be an analog signal, and the signal B may be a digital signal.
When both of the gate electrodes of the transistor are supplied with the fixed potentials, the transistor can function as an element equivalent to a resistor in some cases. For example, in the case where the transistor is an n-channel transistor, the effective resistance of the transistor can be sometimes low (high) when the fixed potential Va or the fixed potential Vb is high (low). When both the fixed potential Va and the fixed potential Vb are high (low), the effective resistance can be lower (higher) than that of a transistor with only one gate in some cases.
Note that the other components of the transistor 100A are similar to those of the transistor 100 described above, and an effect similar to that of the transistor 100A can be obtained.
In addition, an insulating film may be formed over the transistor 100A.
The transistor 100B illustrated in
The insulating film 122 has a function of covering unevenness and the like caused by the transistor or the like. The insulating film 122 has an insulating property and is formed using an inorganic material or an organic material. Examples of the inorganic material include a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, and an aluminum nitride film. Examples of the organic material include photosensitive resin materials such as an acrylic resin and a polyimide resin.
Next, structures of a transistor different from that in
The transistor 100C in
The conductive film 112 in the transistor 100C includes a conductive film 112_1 over the insulating film 110 and a conductive film 112_2 over the conductive film 112_1. For example, with use of an oxide conductive film as the conductive film 112_1, excess oxygen can be added to the insulating film 110. The oxide conductive film can be formed by a sputtering method in an atmosphere containing an oxygen gas. Furthermore, the oxide conductive film can be formed using, for example, an oxide including indium and tin, an oxide including tungsten and indium, an oxide including tungsten, indium, and zinc, an oxide including titanium and indium, an oxide including titanium, indium, and tin, an oxide including indium and zinc, an oxide including silicon, indium, and tin, an oxide including indium, gallium, and zinc, and the like.
As illustrated in
Each of the conductive film 112 and the insulating film 110 of the transistor 100C has a tapered shape. More specifically, the lower end portion of the conductive film 112 is located outward from the upper end portion of the conductive film 112. More specifically, the lower end portion of the conductive film 110 is located outward from the upper end portion of the insulating film 110. The lower end portion of the conductive film 112 is substantially aligned with the upper end portion of the insulating film 110.
It is preferable that the conductive film 112 and the insulating film 110 of the transistor 100C are formed to have tapered shapes because the coverage with the insulating film 116 can be improved as compared with the case where each of the conductive film 112 and the insulating film 110 of the transistor 100A has a rectangular shape.
The other components of the transistor 100C are similar to those of the transistor 100A described above and have similar effects.
The transistor 100D illustrated in
The conductive film 112 in the transistor 100D includes the conductive film 112_1 over the insulating film 110 and the conductive film 112_2 over the conductive film 112_1. The lower end portion of the conductive film 112_1 is located outward from the upper end portion of the conductive film 112_2. For example, the conductive film 112_1, the conductive film 112_2, and the insulating film 110 are processed with one mask, the conductive film 112_2 is processed by a wet etching method, and each of the conductive film 112_1 and the insulating film 110 is processed by a dry etching method, whereby the above-described structure can be obtained.
With the structure of the transistor 100D, regions 108f are formed in the oxide semiconductor film 108 in some cases. The regions 108f are formed between the channel region 108i and the source region 108s and between the channel region 108i and the drain region 108d.
The regions 108f function as high-resistance regions or low-resistance regions. The high-resistance regions have the same level of resistance as the channel region 108i and do not overlap with the conductive film 112 functioning as a gate electrode. In the case where the regions 108f are high-resistance regions, the regions 108f function as offset regions. To suppress a decrease in the on-state current of the transistor 100D, the regions 108f functioning as offset regions may each have a length of 1 μm or less in the channel length (L) direction.
The low-resistance regions have a resistance that is lower than that of the channel region 108i and higher than that of the source region 108s and the drain region 108d. In the case where the regions 108f are low-resistance regions, the regions 108f function as lightly doped drain (LDD) regions. The regions 108f functioning as LDD regions can relieve an electric field in the drain region, thereby reducing a change in the threshold voltage of the transistor due to the electric field in the drain region.
Note that when the regions 108f are LDD regions, for example, one or more of nitrogen, hydrogen, and fluorine is supplied to the regions 108f from the insulating film 116; accordingly the LDD regions can be formed. Alternatively, an impurity element is added to the regions 108f from above the conductive film 112_1 with use of the insulating film 110 and the conductive film 112_1 as masks, so that the impurity is added to the oxide semiconductor film 108 through the conductive film 112_1 and the insulating film 110; accordingly the LDD regions can be formed.
As illustrated in
Note that the other components of the transistor 100D are similar to those of the transistor 100A described above, and an effect similar to that of the transistor 100A can be obtained.
The transistor 100E illustrated in
The conductive film 112 in the transistor 100E includes the conductive film 112_1 over the insulating film 110 and the conductive film 112_2 over the conductive film 112_1. The lower end portion of the conductive film 112_1 is located outward from the lower end portion of the conductive film 112_2. The lower end portion of the insulating film 110 is located outward from the lower end portion of the conductive film 112_1. For example, the conductive film 112_1, the conductive film 112_2, and the insulating film 110 are processed with one mask, each of the conductive film 112_1 and the conductive film 112_2 is processed by a wet etching method, and the insulating film 110 is processed by a dry etching method, whereby the above-described structure can be obtained.
As like the transistor 100D, the transistor 100E includes the regions 108f that are formed in the oxide semiconductor film 108. The regions 108f are formed between the channel region 108i and the source region 108s and between the channel region 108i and the drain region 108d.
As illustrated in
Note that the other components of the transistor 100E are similar to those of the transistor 100A described above, and an effect similar to that of the transistor 100A can be obtained.
Next, structures of a transistor different from that of the transistor 100A in
The transistors 100F, 100G, 100H, 100J, and 100K are different from the above-described transistor 100A in the structure of the oxide semiconductor film 108. Note that the other components of the transistors are similar to those of the transistor 100A described above, and an effect similar to that of the transistor 100A can be obtained.
The oxide semiconductor film 108 of the transistor 100F illustrated in
The oxide semiconductor film 108 of the transistor 100G illustrated in
The oxide semiconductor film 108 of the transistor 100H illustrated in
The oxide semiconductor film 108 of the transistor 100J illustrated in
The oxide semiconductor film 108 of the transistor 100K illustrated in
A side surface of the channel region 108i in the channel width (W) direction or a region in the vicinity of the side surface is easily damaged by processing, resulting in a defect (e.g., oxygen vacancy), or easily contaminated by an impurity attached thereto. Therefore, even when the channel region 108i is substantially intrinsic, stress such as an electric field applied thereto activates the side surface of the channel region 108i in the channel width (W) direction or the region in the vicinity of the side surface and turns it into a low-resistance (n-type) region easily. Moreover, if the side surface of the channel region 108i in the channel width (W) direction or the region in the vicinity of the side surface is an n-type region, a parasitic channel may be formed because the n-type region serves as a carrier path.
Thus, in the transistor 100J and the transistor 100K, the channel region 108i has a stacked-layer structure and side surfaces of the channel region 108i in the channel width (W) direction are covered with one layer of the stacked layers. With such a structure, defects on or in the vicinity of the side surfaces of the channel region 108i can be suppressed or adhesion of an impurity to the side surfaces of the channel region 108i or to regions in the vicinity of the side surfaces can be reduced.
Here, a band structure of the insulating film 104, the oxide semiconductor films 108_1, 108_2, and 108_3, and the insulating film 110, a band structure of the insulating film 104, the oxide semiconductor films 108_2 and 108_3, and the insulating film 110, and a band structure of the insulating film 104, the oxide semiconductor films 108_1 and 108_2, and the insulating film 110 will be described with reference to
In the band structure of
In the band structure of
In the band structure of
As illustrated in
To form a continuous junction between the oxide semiconductor films 108_1, 108_2, and 108_3, it is necessary to form the films successively without exposure to the air by using a multi-chamber deposition apparatus (sputtering apparatus) provided with a load lock chamber.
With the band structure of
By providing the oxide semiconductor films 108_1 and 108_3, the oxide semiconductor film 108_2 can be distanced away from defect states that may be formed in the oxide semiconductor film 108_2.
In addition, the defect states might be more distant from the vacuum level than the conduction band minimum (Ec) of the oxide semiconductor film 108_2 functioning as a channel region, so that electrons are likely to be accumulated in the defect states. When the electrons are accumulated in the defect states, the electrons become negative fixed electric charge, so that the threshold voltage of the transistor is shifted in the positive direction. Therefore, it is preferable that the defect states be closer to the vacuum level than the conduction band minimum (Ec) of the oxide semiconductor film 108_2. Such a structure inhibits accumulation of electrons in the defect states. As a result, the on-state current and the field-effect mobility of the transistor can be increased.
The energy level of the conduction band minimum of each of the oxide semiconductor films 108_1 and 108_3 is closer to the vacuum level than that of the oxide semiconductor film 108_2. Typically, a difference in energy level between the conduction band minimum of the oxide semiconductor film 108_2 and the conduction band minimum of each of the oxide semiconductor films 108_1 and 108_3 is 0.15 eV or more or 0.5 eV or more and 2 eV or less or 1 eV or less. That is, the electron affinity of the oxide semiconductor film 108_2 is higher than those of the oxide semiconductor films 108_1 and 108_3. The difference between the electron affinity of each of the oxide semiconductor films 108_1 and 108_3 and the electron affinity of the oxide semiconductor film 108_2 is 0.15 eV or more or 0.5 eV or more and 2 eV or less or 1 eV or less.
In such a structure, the oxide semiconductor film 108_2 serves as a main current path. In other words, the oxide semiconductor film 108_2 functions as a channel region, and the oxide semiconductor films 108_1 and 108_3 function as oxide insulating films. The oxide semiconductor films 108_1 and 108_3 are each preferably formed using an oxide semiconductor film containing one or more metal elements constituting the oxide semiconductor film 108_2 in which a channel region is formed. In such a structure, interface scattering hardly occurs at the interface between the oxide semiconductor films 108_1 and 108_2 and the interface between the oxide semiconductor films 108_2 and 108_3. Thus, the transistor can have high field-effect mobility because the transfer of carriers is not hindered at the interface.
To prevent each of the oxide semiconductor films 108_1 and 108_3 from functioning as part of a channel region, a material having sufficiently low conductivity is used for the oxide semiconductor films 108_1 and 108_3. Thus, each of the oxide semiconductor films 108_1 and 108_3 can also be referred to as “oxide insulating film” owing to its physical property and/or function. Alternatively, a material which has a smaller electron affinity (a difference in energy level between the vacuum level and the conduction band minimum) than the oxide semiconductor film 108_2 and has a difference in energy level in the conduction band minimum from the oxide semiconductor film 108_2 (band offset) is used for the oxide semiconductor films 108_1 and 108_3. Furthermore, to inhibit generation of a difference between threshold voltages due to the value of the drain voltage, it is preferable to form the oxide semiconductor films 108_1 and 108_3 using a material whose energy level of the conduction band minimum is closer to the vacuum level than that of the oxide semiconductor film 108_2. For example, a difference between the energy level of the conduction band minimum of the oxide semiconductor film 108_2 and the energy level of the conduction band minimum of each of the oxide semiconductor films 108_1 and 108_3 is preferably 0.2 eV or more and further preferably 0.5 eV or more.
It is preferable that the oxide semiconductor films 108_1 and 108_3 not have a spinel crystal structure. This is because if the oxide semiconductor films 108_1 and 108_3 have a spinel crystal structure, constituent elements of the conductive films 120a and 120b might be diffused to the oxide semiconductor film 108_2 at the interface between the spinel crystal structure and another region. Note that each of the oxide semiconductor films 108_1 and 108_3 is preferably a CAAC-OS described later, in which case a higher blocking property against constituent elements of the conductive films 120a and 120b, for example, copper elements, can be obtained.
Although the example where an oxide semiconductor film formed using a metal oxide target whose atomic ratio of In to Ga and Zn is 1:3:2, is used as each of the oxide semiconductor films 108_1 and 108_3 is described in this embodiment, one embodiment of the present invention is not limited thereto. For example, an oxide semiconductor film formed using a metal oxide target whose atomic ratio of In to Ga and Zn is 1:1:1, 1:1:1.2, 1:3:4, 1:3:6, 1:4:5, 1:5:6, or 1:10:1 may be used as each of the oxide semiconductor films 108_1 and 108_3. Alternatively, oxide semiconductor films formed using a metal oxide target whose atomic ratio of Ga to Zn is 10:1 may be used as the oxide semiconductor films 108_1 and 108_3. In that case, it is suitable that an oxide semiconductor film formed using a metal oxide target whose atomic ratio of In to Ga and Zn is 1:1:1 is used as the oxide semiconductor film 108_2 and that an oxide semiconductor film formed using a metal oxide target whose atomic ratio of Ga to Zn is 10:1 is used as each of the oxide semiconductor films 108_1 and 108_3. This is because the difference between the conduction band minimum of the oxide semiconductor film 108_2 and the conduction band minimum of the oxide semiconductor film 108_1 or 108_3 can be 0.6 eV or more.
When the oxide semiconductor films 108_1 and 108_3 are formed using a metal oxide target having an atomic ratio of In:Ga:Zn=1:1:1, the oxide semiconductor films 108_1 and 108_3 have an atomic ratio of In:Ga:Zn=1:β1 (0<β1≦2):β2 (0<β2≦2) in some cases. When the oxide semiconductor films 108_1 and 108_3 are formed using a metal oxide target having an atomic ratio of In:Ga:Zn=1:3:4, the oxide semiconductor films 108_1 and 108_3 have an atomic ratio of In:Ga:Zn=1:β3 (1≦β3≦5):β4 (2≦β4≦6) in some cases. When the oxide semiconductor films 108_1 and 108_3 are formed using a metal oxide target having an atomic ratio of In:Ga:Zn=1:3:6, the oxide semiconductor films 108_1 and 108_3 have an atomic ratio of In:Ga:Zn=1:β5 (1≦β5≦5):β6 (4≦β6≦8) in some cases.
The structure described in this embodiment can be used in appropriate combination with the structure described in any of the other embodiments.
In this embodiment, a transistor that can be used for the semiconductor device of one embodiment of the present invention is described in detail.
In this embodiment, bottom-gate transistors are described with reference
The transistor 300A illustrated in
In the transistor 300A, the insulating films 306 and 307 each function as a gate insulating film of the transistor 300A, and the insulating films 314, 316, and 318 each function as a protective insulating film of the transistor 300A. Moreover, in the transistor 300A, the conductive film 304 functions as a gate electrode, the conductive film 312a functions as a source electrode, and the conductive film 312b functions as a drain electrode.
In this specification and the like, the insulating films 306 and 307 may be referred to as a first insulating film, the insulating films 314 and 316 may be referred to as a second insulating film, and the insulating film 318 may be referred to as a third insulating film.
The transistor 300A illustrated in
The transistor 300B illustrated in
In the transistor 300B, the insulating films 306 and 307 each function as a gate insulating film of the transistor 300B, the insulating films 314 and 316 each function as a protective insulating film of the oxide semiconductor film 308, and the insulating film 318 functions as a protective insulating film of the transistor 300B. Moreover, in the transistor 300B, the conductive film 304 functions as a gate electrode, the conductive film 312a functions as a source electrode, and the conductive film 312b functions as a drain electrode.
The transistor 300B in
The transistor 300C in
The transistor 300D in
In the transistor 300D, the insulating films 306 and 307 each function as a first gate insulating film of the transistor 300D, and the insulating films 314, 316, and 318 each function as a second gate insulating film of the transistor 300D. Moreover, in the transistor 300D, the conductive film 304 functions as a first gate electrode, the conductive film 320a functions as a second gate electrode, and the conductive film 320b functions as a pixel electrode used for a display device. The conductive film 312a and the conductive film 312b function as a source electrode and a drain electrode, respectively.
As illustrated in
The structure of the transistor 300D is not limited to that described above, in which the openings 342b and 342c are provided so that the conductive film 320b is connected to the conductive film 304. For example, a structure in which only one of the openings 342b and 342c is provided so that the conductive film 320b is connected to the conductive film 304, or a structure in which the openings 342b and 342c are not provided and the conductive film 320b is not connected to the conductive film 304 may be employed. Note that in the case where the conductive film 320b is not connected to the conductive film 304, it is possible to apply different potentials to the conductive film 320b and the conductive film 304.
The conductive film 320b is connected to the conductive film 312b through an opening 342a provided in the insulating films 314, 316, and 318.
Note that the transistor 300D has the s-channel structure described above.
The oxide semiconductor film 308 included in the transistor 300A in
The oxide semiconductor film 308 of the transistor 300E illustrated in
Note that the conductive film 304, the insulating film 306, the insulating film 307, the oxide semiconductor film 308, the oxide semiconductor film 308_1, the oxide semiconductor film 308_2, the oxide semiconductor film 308_3, the conductive film 312a, the conductive film 312b, the insulating film 314, the insulating film 316, the insulating film 318, and the conductive films 320a and 320b can be formed using the materials and formation methods of the conductive film 106, the insulating film 116, the insulating film 114, the oxide semiconductor film 108, the oxide semiconductor film 108_1, the oxide semiconductor film 108_2, the oxide semiconductor film 108_3, the conductive film 120a, the conductive film 120b, the insulating film 104, the insulating film 118, the insulating film 116, and the conductive film 112 described in the above embodiment.
The transistor 300G in
The insulating film 306 and the insulating film 307 has an opening 351, and a conductive film 312c electrically connected to the conductive film 304 through the opening 351 is provided over the insulating film 306 and the insulating film 307. The insulating films 314 and 316 have an opening 352a reaching the conductive film 312b and an opening 352b reaching the conductive film 312c.
Note that the oxide semiconductor film 308 includes the oxide semiconductor film 308_2 that is on the conductive film 304 side and the oxide semiconductor film 308_3 over the oxide semiconductor film 308_2.
The insulating film 318 is provided over the transistor 300G. The insulating film 318 is formed to cover the insulating film 316, the conductive film 320a, and the conductive film 320b.
In the transistor 300G, the insulating films 306 and 307 each function as a first gate insulating film of the transistor 300G, the insulating films 314 and 316 each function as a second gate insulating film of the transistor 300G, and the insulating film 318 functions as a protective insulating film of the transistor 300G. In the transistor 300G, the conductive film 304 functions as a first gate electrode, the conductive film 320a functions as a second gate electrode, and the conductive film 320b functions as a pixel electrode used for a display device. Furthermore, in the transistor 300G, the conductive film 312a functions as a source electrode, and the conductive film 312b functions as a drain electrode. Moreover, in the transistor 300G, the conductive film 312c functions as a connection electrode.
The transistor 300G has the s-channel structure described above.
The structures of the transistors 300A to 300G can be freely combined with each other.
The structure described in this embodiment can be used in appropriate combination with the structure described in any of the other embodiments.
In this embodiment, an example of a display device that includes any of the transistors described in the embodiment above is described below with reference to
In the display device 700, a flexible printed circuit (FPC) terminal portion 708 electrically connected to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 is provided in a region different from the region which is surrounded by the sealant 712 and positioned over the first substrate 701. Furthermore, an FPC 716 is connected to the FPC terminal portion 708, and a variety of signals and the like are supplied to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 through the FPC 716. Furthermore, a signal line 710 is connected to the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708. The variety of signals and the like are applied to the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708 via the signal line 710 from the FPC 716.
A plurality of gate driver circuit portions 706 may be provided in the display device 700. An example of the display device 700 in which the source driver circuit portion 704 and the gate driver circuit portion 706 are formed over the first substrate 701 where the pixel portion 702 is also formed is described; however, the structure is not limited thereto. For example, only the gate driver circuit portion 706 may be formed over the first substrate 701 or only the source driver circuit portion 704 may be formed over the first substrate 701. In this case, a substrate over which a source driver circuit, a gate driver circuit, or the like is formed (e.g., a driver circuit board formed using a single-crystal semiconductor film or a polycrystalline semiconductor film) may be formed on the first substrate 701. Note that there is no particular limitation on the method of connecting a separately prepared driver circuit substrate, and a chip on glass (COG) method, a wire bonding method, or the like can be used.
The pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 included in the display device 700 include a plurality of transistors.
The display device 700 can include any of a variety of elements. As examples of the elements, electroluminescent (EL) element (e.g., an EL element containing organic and inorganic materials, an organic EL element, an inorganic EL element, or an LED), a light-emitting transistor element (a transistor which emits light depending on current), an electron emitter, a liquid crystal element, an electronic ink display, an electrophoretic element, an electrowetting element, a plasma display panel (PDP), a micro electro mechanical systems (MEMS) display (e.g., a grating light valve (GLV), a digital micromirror device (DMD), a digital micro shutter (DMS) element, or an interferometric modulator display (IMOD) element), and a piezoelectric ceramic display can be given.
An example of a display device including an EL element is an EL display. Examples of display devices including electron emitters are a field emission display (FED) and an SED-type flat panel display (SED: surface-conduction electron-emitter display). Examples of display devices including liquid crystal elements include a liquid crystal display (e.g., a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct-view liquid crystal display, or a projection liquid crystal display). Display devices having electronic ink or electrophoretic elements include electronic paper and the like. In the case of a transflective liquid crystal display or a reflective liquid crystal display, some of or all of pixel electrodes function as reflective electrodes. For example, some or all of pixel electrodes are formed to contain aluminum, silver, or the like. In such a case, a memory circuit such as an SRAM can be provided under the reflective electrodes. Thus, the power consumption can be further reduced.
As a display method in the display device 700, a progressive method, an interlace method, or the like can be employed. Furthermore, color elements controlled in a pixel at the time of color display are not limited to three colors: R, G, and B (R, G, and B correspond to red, green, and blue, respectively). For example, four pixels of the R pixel, the G pixel, the B pixel, and a W (white) pixel may be included. Alternatively, a color element may be composed of two colors among R, G, and B as in PenTile layout. The two colors may differ among color elements. Alternatively, one or more colors of yellow, cyan, magenta, and the like may be added to RGB. Furthermore, the size of a display region may be different depending on respective dots of the color components. Embodiments of the disclosed invention are not limited to a display device for color display; the disclosed invention can also be applied to a display device for monochrome display.
A coloring layer (also referred to as a color filter) may be used to obtain a full-color display device in which white light (W) is used for a backlight (e.g., an organic EL element, an inorganic EL element, an LED, or a fluorescent lamp). As the coloring layer, red (R), green (G), blue (B), yellow (Y), or the like may be combined as appropriate, for example. With the use of the coloring layer, higher color reproducibility can be obtained than in the case without the coloring layer. In this case, by providing a region with the coloring layer and a region without the coloring layer, white light in the region without the coloring layer may be directly utilized for display. By partly providing the region without the coloring layer, a decrease in luminance due to the coloring layer can be suppressed, and 20% to 30% of power consumption can be reduced in some cases when an image is displayed brightly. Note that in the case where full-color display is performed using a self-luminous element such as an organic EL element or an inorganic EL element, elements may emit light of their respective colors R, G, B, Y, and W. By using a self-luminous element, power consumption can be further reduced as compared to the case of using the coloring layer in some cases.
As a coloring system, any of the following systems may be used: the above-described color filter system in which part of white light is converted into red light, green light, and blue light through color filters; a three-color system in which red light, green light, and blue light are used; and a color conversion system or a quantum dot system in which part of blue light is converted into red light or green light.
In this embodiment, a structure including a liquid crystal element and an EL element as display elements is described with reference to
Common portions between
The display device 700 illustrated in each of
The transistors 750 and 752 each have a structure similar to that of the transistor 100B described above. Note that the transistor 750 and the transistor 752 may each have the structure of any of the other transistors described in the above embodiments.
The transistors used in this embodiment each include an oxide semiconductor film which is highly purified and in which formation of oxygen vacancies is suppressed. The transistor can have low off-state current. Accordingly, an electrical signal such as an image signal can be held for a longer period, and a writing interval can be set longer in an on state. Accordingly, the frequency of refresh operation can be reduced, which leads to an effect of suppressing power consumption.
In addition, the transistor used in this embodiment can have relatively high field-effect mobility and thus is capable of high-speed operation. For example, with such a transistor which can operate at high speed used for a liquid crystal display device, a switching transistor in a pixel portion and a driver transistor in a driver circuit portion can be formed over one substrate. That is, a semiconductor device formed using a silicon wafer or the like is not additionally needed as a driver circuit, by which the number of components of the semiconductor device can be reduced. In addition, the transistor which can operate at high speed can be used also in the pixel portion, whereby a high-quality image can be provided.
A capacitor 790 includes a lower electrode that is formed through a step of processing the same conductive film as a conductive film functioning as a first gate electrode of the transistor 750 and an upper electrode that is formed through a step of processing the same conductive film as a conductive film functioning as a source electrode or a drain electrode of the transistor 750. Furthermore, between the lower electrode and the upper electrode, an insulating film that is formed through a step of forming the same insulating film as an insulating film functioning as a first gate insulating film of the transistor 750 and an insulating film that is formed through a step of forming the same insulating film as an insulating film functioning as a protective insulating film of the transistor 750 are provided. That is, the capacitor 790 has a stacked-layer structure in which the insulating films functioning as a dielectric film are positioned between a pair of electrodes.
In each of
Although
The signal line 710 is formed through the same process as the conductive films functioning as source electrodes and drain electrodes of the transistors 750 and 752. In the case where the signal line 710 is formed using a material including a copper element, signal delay or the like due to wiring resistance is reduced, which enables display on a large screen.
The FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and the FPC 716. Note that the connection electrode 760 is formed through the same process as the conductive films functioning as source electrodes and drain electrodes of the transistors 750 and 752. The connection electrode 760 is electrically connected to a terminal included in the FPC 716 through the anisotropic conductive film 780.
For example, a glass substrate can be used as the first substrate 701 and the second substrate 705. A flexible substrate may be used as the first substrate 701 and the second substrate 705. Examples of the flexible substrate include a plastic substrate.
A structure body 778 is provided between the first substrate 701 and the second substrate 705. The structure body 778 is a columnar spacer obtained by selective etching of an insulating film and provided to control the distance (cell gap) between the first substrate 701 and the second substrate 705. Note that a spherical spacer may be used as the structure body 778.
Furthermore, a light-blocking film 738 functioning as a black matrix, a coloring film 736 functioning as a color filter, and an insulating film 734 in contact with the light-blocking film 738 and the coloring film 736 are provided on the second substrate 705 side.
The display device 700 illustrated in
The conductive film 772 is electrically connected to the conductive film functioning as a source electrode or a drain electrode included in the transistor 750. The conductive film 772 is formed over the planarization insulating film 770 to function as a pixel electrode, i.e., one electrode of the display element.
A conductive film that transmits visible light or a conductive film that reflects visible light can be used for the conductive film 772. For example, a material including one kind selected from indium (In), zinc (Zn), and tin (Sn) is preferably used for the conductive film that transmits visible light. For example, a material including aluminum or silver may be used for the conductive film that reflects visible light.
In the case where a conductive film that reflects visible light is used for the conductive film 772, the display device 700 is a reflective-type liquid crystal display device. Alternatively, a conductive film that transmits visible light is used for the conductive film 772, the display device 700 is a transmissive liquid crystal display device.
When a structure over the conductive film 772 is changed, a driving method of a liquid crystal element can vary. An example of this case is illustrated in
Although not illustrated in
In the case where a liquid crystal element is used as the display element, a thermotropic liquid crystal, a low-molecular liquid crystal, a high-molecular liquid crystal, a polymer-dispersed liquid crystal, a ferroelectric liquid crystal, an anti-ferroelectric liquid crystal, or the like can be used. Such a liquid crystal material exhibits a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, or the like depending on conditions.
Alternatively, in the case of employing a horizontal electric field mode, a liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used. A blue phase is one of liquid crystal phases, which is generated just before a cholesteric phase changes into an isotropic phase while temperature of cholesteric liquid crystal is increased. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition in which several weight percent or more of a chiral material is mixed is used for the liquid crystal layer in order to improve the temperature range. The liquid crystal composition which includes liquid crystal exhibiting a blue phase and a chiral material has a short response time and optical isotropy, which makes the alignment process unneeded. An alignment film does not need to be provided and rubbing treatment is thus not necessary; accordingly, electrostatic discharge damage caused by the rubbing treatment can be prevented and defects and damage of the liquid crystal display device in the manufacturing process can be reduced. Moreover, the liquid crystal material which exhibits a blue phase has a small viewing angle dependence.
In the case where a liquid crystal element is used as the display element, a twisted nematic (TN) mode, an in-plane-switching (IPS) mode, a fringe field switching (FFS) mode, an axially symmetric aligned micro-cell (ASM) mode, an optically compensated birefringence (OCB) mode, a ferroelectric liquid crystal (FLC) mode, an antiferroelectric liquid crystal (AFLC) mode, or the like can be used.
Furthermore, a normally black liquid crystal display device such as a transmissive liquid crystal display device utilizing a vertical alignment (VA) mode may also be used for the display device 700. There are some examples of a vertical alignment mode; for example, a multi-domain vertical alignment (MVA) mode, a patterned vertical alignment (PVA) mode, an ASV mode, or the like can be employed.
The display device 700 illustrated in
Examples of materials that can be used for an organic compound include a fluorescent material and a phosphorescent material. Examples of materials that can be used for a quantum dot include a colloidal quantum dot material, an alloyed quantum dot material, a core-shell quantum dot material, and a core quantum dot material. The quantum dot containing elements belonging to Groups 12 and 16, elements belonging to Groups 13 and 15, or elements belonging to Groups 14 and 16, may be used. Alternatively, a quantum dot material containing an element such as cadmium (Cd), selenium (Se), zinc (Zn), sulfur (S), phosphorus (P), indium (In), tellurium (Te), lead (Pb), gallium (Ga), arsenic (As), or aluminum (Al) may be used.
In the display device 700 shown in
The coloring film 736 is provided to overlap with the light-emitting element 782, and the light-blocking film 738 is provided to overlap with the insulating film 730 and to be included in the lead wiring portion 711 and in the source driver circuit portion 704. The coloring film 736 and the light-blocking film 738 are covered with the insulating film 734. A space between the light-emitting element 782 and the insulating film 734 is filled with a sealing film 732. Although a structure with the coloring film 736 is described as the display device 700 in
<4-4. Structure Example of Display Device Provided with Input/Output Device>
An input/output device may be provided in the display device 700 illustrated in
First, the touch panel 791 illustrated in
The touch panel 791 illustrated in
Note that the touch panel 791 includes the light-blocking film 738, an insulating film 792, an electrode 793, an electrode 794, an insulating film 795, an electrode 796, and an insulating film 797. Changes in the mutual capacitance in the electrodes 793 and 794 can be detected when an object such as a finger or a stylus approaches, for example.
A portion in which the electrode 793 intersects with the electrode 794 is illustrated in the upper portion of the transistor 750 illustrated in
The electrode 793 and the electrode 794 are provided in a region overlapping with the light-blocking film 738. As illustrated in
In addition, since the electrodes 793 and 794 do not overlap with the light-emitting element 782, the electrodes 793 and 794 can be formed using a metal material with low visible light transmittance. In the case where the electrode 793 and the electrode 794 do not overlap with the liquid crystal element 775, a metal material having low transmittance with respect to visible light can be used for the electrode 793 and the electrode 794.
Thus, as compared with the case of using an oxide material whose transmittance of visible light is high, resistance of the electrodes 793 and 794 can be reduced, whereby sensitivity of the sensor of the touch panel can be increased.
For example, a conductive nanowire may be used for the electrodes 793, 794, and 796. The nanowires may have a mean diameter greater than or equal to 1 nm and less than or equal to 100 nm, preferably greater than or equal to 5 nm and less than or equal to 50 nm, further preferably greater than or equal to 5 nm and less than or equal to 25 nm. As the nanowire, a carbon nanotube or a metal nanowire such as an Ag nanowire, a Cu nanowire, or an Al nanowire may be used. For example, in the case where an Ag nanowire is used for any one of or all of the electrodes 793, 794, and 796, the transmittance of visible light can be greater than or equal to 89% and the sheet resistance can be greater than or equal to 40 Ω/square and less than or equal to 100 Ω/square.
Although the structure of the in-cell touch panel is illustrated in
In this manner, the display device of one embodiment of the present invention can be combined with various types of touch panels.
The structure described in this embodiment can be used in appropriate combination with the structure described in any of the other embodiments.
In this embodiment, a display device including a semiconductor device of one embodiment of the present invention will be described with reference to
The display device illustrated in
Part or the whole of the driver circuit portion 504 is preferably formed over a substrate over which the pixel portion 502 is formed. Thus, the number of components and the number of terminals can be reduced. When part or the whole of the driver circuit portion 504 is not formed over the substrate over which the pixel portion 502 is formed, the part or the whole of the driver circuit portion 504 can be mounted by COG or tape automated bonding (TAB).
The pixel portion 502 includes a plurality of circuits for driving display elements arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more) (hereinafter, such circuits are referred to as pixel circuits 501). The driver circuit portion 504 includes driver circuits such as a circuit for supplying a signal (scan signal) to select a pixel (hereinafter, the circuit is referred to as a gate driver 504a) and a circuit for supplying a signal (data signal) to drive a display element in a pixel (hereinafter, the circuit is referred to as a source driver 504b).
The gate driver 504a includes a shift register or the like. The gate driver 504a receives a signal for driving the shift register through the terminal portion 507 and outputs a signal. For example, the gate driver 504a receives a start pulse signal, a clock signal, or the like and outputs a pulse signal. The gate driver 504a has a function of controlling the potentials of wirings supplied with scan signals (hereinafter, such wirings are referred to as scan lines GL_1 to GL_X). Note that a plurality of gate drivers 504a may be provided to control the scan lines GL_1 to GL_X separately. Alternatively, the gate driver 504a has a function of supplying an initialization signal. Without being limited thereto, the gate driver 504a can supply another signal.
The source driver 504b includes a shift register or the like. The source driver 504b receives a signal (image signal) from which a data signal is derived, as well as a signal for driving the shift register, through the terminal portion 507. The source driver 504b has a function of generating a data signal to be written to the pixel circuit 501 which is based on the image signal. In addition, the source driver 504b has a function of controlling output of a data signal in response to a pulse signal produced by input of a start pulse signal, a clock signal, or the like. Furthermore, the source driver 504b has a function of controlling the potentials of wirings supplied with data signals (hereinafter such wirings are referred to as data lines DL_1 to DL_Y). Alternatively, the source driver 504b has a function of supplying an initialization signal. Without being limited thereto, the source driver 504b can supply another signal.
The source driver 504b includes a plurality of analog switches, for example. The source driver 504b can output, as the data signals, signals obtained by time-dividing the image signal by sequentially turning on the plurality of analog switches. The source driver 504b may include a shift register or the like.
A pulse signal and a data signal are input to each of the plurality of pixel circuits 501 through one of the plurality of scan lines GL supplied with scan signals and one of the plurality of data lines DL supplied with data signals, respectively. Writing and holding of the data signal to and in each of the plurality of pixel circuits 501 are controlled by the gate driver 504a. For example, to the pixel circuit 501 in the m-th row and the n-th column (m is a natural number of less than or equal to X, and n is a natural number of less than or equal to Y), a pulse signal is input from the gate driver 504a through the scan line GL_m, and a data signal is input from the source driver 504b through the data line DL_n in accordance with the potential of the scan line GL_m.
The protection circuit 506 illustrated in
The protection circuit 506 is a circuit that electrically connects a wiring connected to the protection circuit to another wiring when a potential out of a certain range is applied to the wiring connected to the protection circuit.
As shown in
In
Each of the plurality of pixel circuits 501 in
The pixel circuit 501 illustrated in
The potential of one of a pair of electrodes of the liquid crystal element 570 is set in accordance with the specifications of the pixel circuit 501 as appropriate. The alignment state of the liquid crystal element 570 depends on written data. A common potential may be supplied to one of the pair of electrodes of the liquid crystal element 570 included in each of the plurality of pixel circuits 501. The potential supplied to the one of the pair of electrodes of the liquid crystal element 570 in the pixel circuit 501 may differ between rows.
As examples of a driving method of the display device including the liquid crystal element 570, any of the following modes can be given: a TN mode, an STN mode, a VA mode, an axially symmetric aligned micro-cell (ASM) mode, an optically compensated birefringence (OCB) mode, a ferroelectric liquid crystal (FLC) mode, an antiferroelectric liquid crystal (AFLC) mode, an MVA mode, a patterned vertical alignment (PVA) mode, an IPS mode, an FFS mode, a transverse bend alignment (TBA) mode, and the like. Other examples of the method of driving the display device include an electrically controlled birefringence (ECB) mode, a polymer-dispersed liquid crystal (PDLC) mode, a polymer network liquid crystal (PNLC) mode, and a guest-host mode. A variety of liquid crystal elements and the driving methods thereof can be used.
In the pixel circuit 501 in the m-th row and the n-th column, one of a source electrode and a drain electrode of the transistor 550 is electrically connected to the data line DL_n, and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. A gate electrode of the transistor 550 is electrically connected to the scan line GL_m. The transistor 550 has a function of controlling whether to write a data signal by being turned on or off.
One of a pair of electrodes of the capacitor 560 is electrically connected to a wiring to which a potential is supplied (hereinafter referred to as a potential supply line VL), and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. The potential of the potential supply line VL is set in accordance with the specifications of the pixel circuit 501 as appropriate. The capacitor 560 functions as a storage capacitor for storing written data.
For example, in the display device including the pixel circuit 501 in
When the transistors 550 are turned off, the pixel circuits 501 in which the data has been written are brought into a holding state. This operation is sequentially performed row by row; thus, an image is displayed.
Alternatively, each of the plurality of pixel circuits 501 in
The pixel circuit 501 illustrated in
One of a source electrode and a drain electrode of the transistor 552 is electrically connected to a wiring to which a data signal is supplied (hereinafter referred to as a data line DL_n). A gate electrode of the transistor 552 is electrically connected to a wiring to which a gate signal is supplied (hereinafter referred to as a scan line GL_m).
The transistor 552 has a function of controlling whether to write a data signal by being turned on or off
One of a pair of electrodes of the capacitor 562 is electrically connected to a wiring to which a potential is supplied (hereinafter referred to as a potential supply line VL_a), and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 552.
The capacitor 562 functions as a storage capacitor for storing written data.
One of a source electrode and a drain electrode of the transistor 554 is electrically connected to the potential supply line VL_a. Furthermore, a gate electrode of the transistor 554 is electrically connected to the other of the source electrode and the drain electrode of the transistor 552.
One of an anode and a cathode of the light-emitting element 572 is electrically connected to a potential supply line VL_b, and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 554.
As the light-emitting element 572, an organic electroluminescent element (also referred to as an organic EL element) can be used, for example. Note that the light-emitting element 572 is not limited to an organic EL element; an inorganic EL element including an inorganic material may be used.
Note that a high power supply potential VDD is supplied to one of the potential supply line VL_a and the potential supply line VL_b, and a low power supply potential VSS is supplied to the other.
For example, in the display device including the pixel circuit 501 in
When the transistors 552 are turned off, the pixel circuits 501 in which the data has been written are brought into a holding state. Furthermore, the amount of current flowing between the source electrode and the drain electrode of the transistor 554 is controlled in accordance with the potential of the written data signal. The light-emitting element 572 emits light with luminance corresponding to the amount of flowing current. This operation is sequentially performed row by row; thus, an image is displayed.
The structure described in this embodiment can be used in appropriate combination with the structure described in any of the other embodiments.
In this embodiment, circuit configuration examples to which the transistors described in the above embodiments can be applied will be described with reference to
Note that in this embodiment, the transistor including an oxide semiconductor described in the above embodiment is referred to as an OS transistor in the following description.
Note that the inverter 800 including the OS transistors can be provided over a CMOS circuit including Si transistors. Since the inverter 800 can be provided so as to overlap with the CMOS circuit, no additional area is required for the inverter 800, and thus, an increase in the circuit area can be suppressed.
Each of the OS transistors 810 and 820 includes a first gate functioning as a front gate, a second gate functioning as a back gate, a first terminal functioning as one of a source and a drain, and a second terminal functioning as the other of the source and the drain.
The first gate of the OS transistor 810 is connected to its second terminal. The second gate of the OS transistor 810 is connected to a wiring that supplies the signal SBG. The first terminal of the OS transistor 810 is connected to a wiring which supplies a voltage VDD. The second terminal of the OS transistor 810 is connected to the output terminal OUT.
The first gate of the OS transistor 820 is connected to the input terminal IN. The second gate of the OS transistor 820 is connected to the input terminal IN. The first terminal of the OS transistor 820 is connected to the output terminal OUT. The second terminal of the OS transistor 820 is connected to a wiring which supplies a voltage VSS.
The signal SBG can be supplied to the second gate of the OS transistor 810 to control the threshold voltage of the OS transistor 810.
The signal SBG includes a voltage VBG_A for shifting the threshold voltage in the negative direction and a voltage VBG_B for shifting the threshold voltage in the positive direction. The threshold voltage of the OS transistor 810 can be shifted in the negative direction to be a threshold voltage VTH_A when the voltage VBG_A is applied to the second gate. The threshold voltage of the OS transistor 810 can be shifted in the positive direction to be a threshold voltage VTH_B when the voltage VBG_B is applied to the second gate.
To visualize the above description,
When a high voltage such as the voltage VBG_A is applied to the second gate, the electrical characteristics of the OS transistor 810 can be shifted to match a curve shown by a dashed line 840 in
The shift of the threshold voltage in the positive direction toward the threshold voltage VTH_B can make current less likely to flow in the OS transistor 810.
As illustrated in
Since a state in which current is less likely to flow in the OS transistor 810 as illustrated in
The shift of the threshold voltage in the negative direction toward the threshold voltage VTH_A can make current flow easily in the OS transistor 810.
Note that the threshold voltage of the OS transistor 810 is preferably controlled by the signal SBG before the state of the OS transistor 820 is switched, i.e., before time T1 or T2. For example, as in
Although the timing chart in
The circuit configuration in
The operation with the circuit configuration in
The voltage for controlling the threshold voltage of the OS transistor 810 is supplied to the second gate of the OS transistor 810 before time T3 at which the level of the signal supplied to the input terminal IN is changed to a high level. The signal SF is set to a high level and the OS transistor 850 is turned on, so that the voltage VBG_B for controlling the threshold voltage is supplied to a node NBG.
The OS transistor 850 is turned off after the voltage of the node NBG becomes VBG_B. The off-state current of the OS transistor 850 is extremely low and thus, when the OS transistor 850 is kept in an off-state, the voltage VBG_B which is temporarily held in the node NBG can be kept retained. Therefore, the number of times of operation of supplying the voltage VBG_B to the second gate of the OS transistor 850 can be reduced and accordingly the power consumed to rewrite the voltage VBG_B can be reduced.
Although
The circuit configuration in
The operation with the circuit configuration in
The output waveform IN_B which corresponds to a signal whose logic is inverted from the logic of the signal supplied to the input terminal IN can be used as a signal that controls the threshold voltage of the OS transistor 810. Therefore, the threshold voltage of the OS transistor 810 can be controlled as described with reference to
Moreover, the signal supplied to the input terminal IN is at a low level and the OS transistor 820 is turned off at time T5 in
As described above, in the structure of the inverter including the OS transistor in this embodiment, the voltage of the back gate is switched in accordance with the logic of the signal supplied to the input terminal IN. In such a structure, the threshold voltage of the OS transistor can be controlled. The control of the threshold voltage of the OS transistor by the signal supplied to the input terminal IN can cause a steep change in the voltage of the output terminal OUT. Moreover, shoot-through current between the wirings that supply power supply voltages can be reduced. Thus, power consumption can be reduced.
The structure described in this embodiment can be used in appropriate combination with the structure described in any of the other embodiments.
In this embodiment, examples of a semiconductor device in which the transistor including an oxide semiconductor (OS transistor) described in any of the above embodiments is used in a plurality of circuits will be described with reference to
The power supply circuit 901 is a circuit that generates a voltage VORG used as a reference. The voltage VORG is not necessarily one voltage and can be a plurality of voltages. The voltage VORG can be generated on the basis of a voltage V0 supplied from the outside of the semiconductor device 900. The semiconductor device 900 can generate the voltage VORG on the basis of one power supply voltage supplied from the outside. Thus, the semiconductor device 900 can operate without supply of a plurality of power supply voltages from the outside.
The circuits 902, 904, and 906 operate with different power supply voltages. For example, the power supply voltage of the circuit 902 is a voltage applied on the basis of the voltage VORG and the voltage VSS (VORG>VSS). For example, the power supply voltage of the circuit 904 is a voltage applied on the basis of a voltage VPOG and the voltage VSS (VPOG>VORG). For example, the power supply voltages of the circuit 906 are voltages applied on the basis of the voltage VORG, the voltage VSS, and a voltage VNEG (VORG>VSS>VNEG). When the voltage VSS is equal to a ground potential (GND), the kinds of voltages generated in the power supply circuit 901 can be reduced.
The voltage generation circuit 903 is a circuit that generates the voltage VPOG. The voltage generation circuit 903 can generate the voltage VPOG on the basis of the voltage VORG supplied from the power supply circuit 901. Thus, the semiconductor device 900 including the circuit 904 can operate on the basis of one power supply voltage supplied from the outside.
The voltage generation circuit 905 is a circuit that generates the voltage VNEG. The voltage generation circuit 905 can generate the voltage VNEG on the basis of the voltage VORG supplied from the power supply circuit 901. Thus, the semiconductor device 900 including the circuit 906 can operate on the basis of one power supply voltage supplied from the outside.
The voltage VNEG may be directly supplied to the back gate of the transistor 912. Alternatively, a signal supplied to the gate of the transistor 912 may be generated on the basis of the voltage VORG and the voltage VNEG and the generated signal may also be supplied to the back gate of the transistor 912.
In a circuit diagram illustrated in
A timing chart in
The circuit structure of the voltage generation circuit 903 is not limited to the structure of the circuit diagram shown in
The voltage generation circuit 903A shown in
The voltage generation circuit 903B shown in
A voltage generation circuit 903C shown in
As described above, in any of the structures of this embodiment, a voltage required for circuits included in a semiconductor device can be internally generated. Thus, in the semiconductor device, the number of power supply voltages supplied from the outside can be reduced.
The structures and the like described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.
In this embodiment, a display module and electronic devices, each of which includes a semiconductor device of one embodiment of the present invention, will be described with reference to
In a display module 7000 illustrated in
The semiconductor device of one embodiment of the present invention can be used for the display panel 7006, for example.
The shapes and sizes of the upper cover 7001 and the lower cover 7002 can be changed as appropriate in accordance with the sizes of the touch panel 7004 and the display panel 7006.
The touch panel 7004 can be a resistive touch panel or a capacitive touch panel and overlap with the display panel 7006. Alternatively, a counter substrate (sealing substrate) of the display panel 7006 can have a touch panel function. Alternatively, a photosensor may be provided in each pixel of the display panel 7006 to form an optical touch panel.
The backlight 7007 includes a light source 7008. One embodiment of the present invention is not limited to the structure in
The frame 7009 protects the display panel 7006 and functions as an electromagnetic shield for blocking electromagnetic waves generated by the operation of the printed board 7010. The frame 7009 may also function as a radiator plate.
The printed board 7010 includes a power supply circuit and a signal processing circuit for outputting a video signal and a clock signal. As a power source for supplying power to the power supply circuit, an external commercial power source or the separate battery 7011 may be used. The battery 7011 can be omitted in the case where a commercial power source is used.
The display module 7000 may be additionally provided with a member such as a polarizing plate, a retardation plate, or a prism sheet.
Next,
The camera 8000 includes a housing 8001, a display portion 8002, an operation button 8003, a shutter button 8004, and the like. Furthermore, an attachable lens 8006 is attached to the camera 8000.
Although the lens 8006 of the camera 8000 here is detachable from the housing 8001 for replacement, the lens 8006 may be included in the housing 8001.
Images can be taken with the camera 8000 at the press of the shutter button 8004. In addition, images can be taken at the touch of the display portion 8002 which serves as a touch panel.
The housing 8001 of the camera 8000 includes a mount including an electrode, so that the finder 8100, a stroboscope, or the like can be connected to the housing 8001.
The finder 8100 includes a housing 8101, a display portion 8102, a button 8103, and the like.
The housing 8101 includes a mount for engagement with the mount of the camera 8000 so that the finder 8100 can be connected to the camera 8000. The mount includes an electrode, and an image or the like received from the camera 8000 through the electrode can be displayed on the display portion 8102.
The button 8103 serves as a power button. The on/off state of the display portion 8102 can be turned on and off with the button 8103.
A display device of one embodiment of the present invention can be used in the display portion 8002 of the camera 8000 and the display portion 8102 of the finder 8100.
Although the camera 8000 and the finder 8100 are separate and detachable electronic devices in
The head-mounted display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, a cable 8205, and the like. The mounting portion 8201 includes a battery 8206.
Power is supplied from the battery 8206 to the main body 8203 through the cable 8205. The main body 8203 includes a wireless receiver or the like to receive video data, such as image data, and display it on the display portion 8204. The movement of the eyeball and the eyelid of a user is captured by a camera in the main body 8203 and then coordinates of the points the user looks at are calculated using the captured data to utilize the eye of the user as an input means.
The mounting portion 8201 may include a plurality of electrodes so as to be in contact with the user. The main body 8203 may be configured to sense current flowing through the electrodes with the movement of the user's eyeball to recognize the direction of his or her eyes. The main body 8203 may be configured to sense current flowing through the electrodes to monitor the user's pulse. The mounting portion 8201 may include sensors, such as a temperature sensor, a pressure sensor, or an acceleration sensor so that the user's biological information can be displayed on the display portion 8204. The main body 8203 may be configured to sense the movement of the user's head or the like to move an image displayed on the display portion 8204 in synchronization with the movement of the user's head or the like.
The display device of one embodiment of the present invention can be used in the display portion 8204.
A user can see a display on the display portion 8302 through the lenses 8305. The display portion 8302 can be curved. With an arrangement of the curved display portion 8302, the user can feel a highly realistic sensation. Although a structure in which one display portion 8302 is provided is shown in this embodiment, the structure is not limited thereto, and two display portions 8302 may be provided, for example. In this case, if one display portion is assigned to one eye of the user, three-dimensional display utilizing parallax or the like can be achieved.
The display device of one embodiment of the present invention can be used in the display portion 8302. The display device including the semiconductor device of one embodiment of the present invention has an extremely high resolution; thus, even when an image displayed on the display portion 8302 is magnified using the lenses 8305 as illustrated in
Next,
Electronic devices illustrated in
The electronic devices illustrated in
The electronic devices in
A display device 9500 illustrated in
Each of the plurality of display panels 9501 is flexible. Two adjacent display panels 9501 are provided so as to partly overlap with each other. For example, the light-transmitting regions 9503 of the two adjacent display panels 9501 can be overlapped each other. A display device having a large screen can be obtained with the plurality of display panels 9501. The display device is highly versatile because the display panels 9501 can be wound depending on its use.
Although the display regions 9502 of the adjacent display panels 9501 are separated from each other in
The electronic devices described in this embodiment each include the display portion for displaying some sort of data. Note that the semiconductor device of one embodiment of the present invention can also be used for an electronic device that does not have a display portion.
The structure described in this embodiment can be used in appropriate combination with the structure described in any of the other embodiments.
In this example, the carrier density of an oxide semiconductor film of one embodiment of the present invention was measured. The measurement and its result are described below.
In this example, heat treatment was performed on Sample A1, Sample A4, Sample A7, Sample A10, and Sample A11, which are described in Embodiment 1, and the carrier density of each sample was measured.
As the heat treatment, a first heat treatment was performed at 450° C. for 1 hour in a nitrogen atmosphere and then a second heat treatment was performed at 450° C. for 1 hour in a mixed atmosphere of nitrogen and oxygen.
For the measurement of carrier densities, a Hall effect measurement system (resistivity/Hall measurement system, ResiTest 8310 Series manufactured by TOYO Corporation) was used. The system ResiTest 8310 is capable of measuring alternate current (AC) Hall. In the measurement, the direction and strength of a magnetic field are changed in a certain cycle and in synchronization therewith, so that only a Hall electromotive voltage caused in a sample is detected. Even in the case of a material with low field-effect mobility and high resistivity, a Hall electromotive voltage can be detected.
Specifically,
As shown in
The results suggest that the amount of oxygen vacancies in the oxide semiconductor film increases by the first heat treatment, and that the oxygen vacancies in the oxide semiconductor film are filled with oxygen by the subsequent second heat treatment.
Note that the structure described in this example can be combined as appropriate with any of the structures described in the embodiments or the other examples.
In this example, transistors in each of which the oxide semiconductor film of one embodiment of the present invention was used in a channel region (each transistor with a channel length L of 6.0 μm and a channel width W of 50 μm) were fabricated, and electrical characteristics of the transistors were measured. Note that Samples B1 to B3 were fabricated in this example.
Samples B1 to B3 each have a structure in which 5 transistors each corresponding to the transistor 100B illustrated in
First, the substrate 102 was prepared. As the substrate 102, a glass substrate was used. Next, the conductive film 106 was formed over the substrate 102. For the conductive film 106, a 10-nm-thick titanium film and a 100-nm-thick copper film were formed with a sputtering apparatus.
Next, the insulating film 104 was formed over the substrate 102 and the conductive film 106. Note that in this example, as the insulating film 104, insulating films 104_1, 104_2, 104_3, and 104_4 were successively formed in this order with a PECVD apparatus in a vacuum. A 50-nm-thick silicon nitride film was formed as the insulating film 104_1. A 300-nm-thick silicon nitride film was formed as the insulating film 104_2. A 50-nm-thick silicon nitride film was formed as the insulating film 104_3. A 50-nm-thick silicon oxynitride film was formed as the insulating film 104_4.
Next, an oxide semiconductor film was formed over the insulating film 104 and was processed into an island shape, whereby the oxide semiconductor film 108 was formed. A 40-nm-thick oxide semiconductor film was formed as the oxide semiconductor film 108.
The oxide semiconductor film 108 in Sample B1 was formed under the following conditions: the substrate temperature was 170° C.; an argon gas with a flow rate of 140 sccm and an oxygen gas with a flow rate of 60 sccm were introduced into a chamber of the sputtering apparatus; the pressure was set to 0.6 Pa; and an AC power of 2.5 kW was applied to a metal oxide target containing indium, gallium, and zinc (In:Ga:Zn=4:2:4.1 [atomic ratio]). The oxygen flow rate ratio for fabricating Sample B1 was 30%.
Note that processing into the oxide semiconductor film 108 was performed by a wet etching method.
Next, an insulating film to be the insulating film 110 was formed over the insulating film 104 and the oxide semiconductor film 108. For the insulating film, a 150-nm-thick silicon oxynitride film was formed with a PECVD apparatus.
Next, heat treatment was performed. The heat treatment was performed at 350° C. in a mixed gas atmosphere of nitrogen and oxygen for one hour.
Next, the opening 143 was formed at desired regions in the insulating film 104 and the insulating film that is to be the insulating film 110. The formation method of the opening 143 was a dry etching method.
A 100-nm-thick oxide semiconductor film was formed over the insulating film so as to cover the opening 143, and the oxide semiconductor film was processed into an island shape, so that the conductive film 112 was formed. The insulating film in contact with the bottom surface of the conductive film 112 was processed in succession to the formation of the conductive film 112, whereby the insulating film 110 was formed.
As the conductive film 112, a 100-nm-thick oxide semiconductor film was formed. Note that the oxide semiconductor film had a stacked-layer structure including two layers. A first layer in the oxide semiconductor film was formed to have a thickness of 10 nm under the following conditions: the substrate temperature was 170° C.; an oxygen gas with a flow rate of 200 sccm was introduced into a chamber of the sputtering apparatus; the pressure was set to 0.6 Pa; and an AC power of 2.5 kW was applied to a metal oxide target containing indium, gallium, and zinc (In:Ga:Zn=4:2:4.1 [atomic ratio]). A second layer of the oxide semiconductor film was formed to have thickness of 90 nm under the following conditions: the substrate temperature was 170° C.; an argon gas with a flow rate of 180 sccm and an oxygen gas with a flow rate of 20 sccm were introduced into a chamber of the sputtering apparatus; the pressure was set to 0.6 Pa; and an AC power of 2.5 kW was applied to a metal oxide target containing indium, gallium, and zinc (In:Ga:Zn=4:2:4.1 [atomic ratio]).
Note that processing into the conductive film 112 was performed by a wet etching method, and processing into the insulating film 110 was performed by a dry etching method.
Next, plasma treatment was performed from above the insulating film 104, the oxide semiconductor film 108, the insulating film 110, and the conductive film 112. The plasma treatment was performed with a PECVD apparatus at a substrate temperature of 220° C. in a mixed gas atmosphere containing an argon gas and a nitrogen gas.
Then, the insulating film 116 was formed over the insulating film 104, the oxide semiconductor film 108, the insulating film 110, and the conductive film 112. As the insulating film 116, a 100-nm-thick silicon nitride film was formed with a PECVD apparatus.
Next, the insulating film 118 was formed over the insulating film 116. As the insulating film 118, a 300-nm-thick silicon oxynitride film was formed with a PECVD apparatus.
Next, a mask was formed over the insulating film 118, and the openings 141a and 141b were formed in the insulating films 116 and 118 using the mask. Processing into the openings 141a and 141b was performed with a dry etching apparatus.
Next, a conductive film was formed over the insulating film 118 so as to fill the openings 141a and 141b and was processed into island shapes, whereby the conductive films 120a and 120b were formed.
For the conductive films 120a and 120b, a 10-nm-thick titanium film and a 100-nm-thick copper film were formed with a sputtering apparatus.
The insulating film 122 was formed over the insulating film 118 and the conductive films 120a and 120b. A 1.5-μm-thick acrylic-based photosensitive resin film was used as the insulating film 122.
Through the above-described steps, the transistor corresponding to the transistor 100B illustrated in
In fabrication of Sample B2, the formation conditions of the oxide semiconductor film 108 are different from those in fabrication of Sample B1. Note that other than the formation conditions of the oxide semiconductor film 108, fabrication conditions of Sample B2 are the same as those of Sample B1.
The oxide semiconductor film 108 in Sample B2 was formed under the following conditions: the substrate temperature was 130° C.; an argon gas with a flow rate of 180 sccm and an oxygen gas with a flow rate of 20 sccm were introduced into a chamber of the sputtering apparatus; the pressure was set to 0.6 Pa; and an AC power of 2.5 kW was applied to a metal oxide target containing indium, gallium, and zinc (In:Ga:Zn=4:2:4.1 [atomic ratio]). The oxygen flow rate ratio for fabricating Sample B2 was 10%.
In fabrication of Sample B3, the formation conditions of the oxide semiconductor film 108 are different from those in fabrication of Sample B1. Note that other than the formation conditions of the oxide semiconductor film 108, fabrication conditions of Sample B3 are the same as those of Sample B1.
The oxide semiconductor film 108 in Sample B3 was formed under the following conditions: the substrate temperature was room temperature (R.T.); an argon gas with a flow rate of 180 sccm and an oxygen gas with a flow rate of 20 sccm were introduced into a chamber of the sputtering apparatus; the pressure was set to 0.6 Pa; and an AC power of 2.5 kW was applied to a metal oxide target containing indium, gallium, and zinc (In:Ga:Zn=4:2:4.1 [atomic ratio]). The oxygen flow rate ratio for fabricating Sample B3 was 10%.
<2-4. Drain Current-Gate Voltage (Id-Vg) Characteristics of Transistor>
Next, Id-Vg characteristics of the transistors in Samples B1 to B3 were measured.
As conditions for measuring the Id-Vg characteristics of each transistor, a voltage applied to the conductive film 106 functioning as the first gate electrode of each transistor (hereinafter the voltage is also referred to as gate voltage (Vg)) and a voltage applied to the conductive film 112 functioning as the second gate electrode of each transistor (hereinafter the voltage is also referred to as back gate voltage (Vbg)) changed from −15 V to +20 V in increments of 0.25 V. A voltage (source voltage, referred to as Vs) applied to the conductive film 120a functioning as the source electrode was 0 V (comm), and a voltage (drain voltage, referred to as Vd) applied to the conductive film 120b functioning as the drain electrode was 0.1 V and 20 V.
As shown in
The etching rate of the oxide semiconductor film indicates an etching rate when the oxide semiconductor film was etched using a phosphoric acid aqueous solution that was obtained by diluting 85 vol % phosphoric acid with water 100 times. Measurement points of the etching rate of the oxide semiconductor films were regions in the vicinity of the 5 transistors formed over the substrate 102.
As shown in
According to the results shown in
Thus, when the etching is performed with use of a phosphoric acid aqueous solution obtained by diluting 85 vol % phosphoric acid with water 100 times, the oxide semiconductor film of one embodiment of the present invention has a region which is etched at an etching rate preferably higher than or equal to 10 nm/min and lower than or equal to 45 nm/min, further preferably higher than or equal to 10 nm/min and lower than or equal to 25 nm/min.
Note that the characteristics of the transistor, particularly the threshold voltage of the transistor vary depending on the channel length (L) and channel width (W). Therefore, the optimum etching rate may be selected by a practitioner.
Note that the structure described in this example can be combined as appropriate with any of the structures described in the embodiments or the other examples.
In this example, the sheet resistance of the oxide semiconductor film of one embodiment of the present invention was examined. In this example, samples (Samples C1 to C4) corresponding to a sample 650 for evaluation illustrated in
First, the sample 650 for evaluation illustrated in
The sample 650 for evaluation includes a conductive film 604a over the substrate 602, a conductive film 604b over the substrate 602, an insulating film 606 covering the substrate 602 and the conductive films 604a and 604b, an insulating film 607 over the insulating film 606, an oxide semiconductor film 609 over the insulating film 607, a conductive film 612d connected to the conductive film 604a through an opening 644a provided in the insulating films 606 and 607, a conductive film 612e connected to the conductive film 604b through an opening 644b provided in the insulating films 606 and 607, and an insulating film 618 covering the insulating film 607, the oxide semiconductor film 609, and the conductive films 612d and 612e.
Note that the conductive films 612d and 612e are connected to the oxide semiconductor film 609. In addition, openings 646a and 646b are provided in the insulating film 618 over the conductive films 612d and 612e, respectively.
Samples in which the oxide semiconductor films 609 have different structures from each other were fabricated as Samples C1 to C4, and the sheet resistance of each oxide semiconductor film 609 was examined. Note that in each of the samples C1 to C4, the size (W/L) of the oxide conductive film 609 was 10 μm/1500 μm.
A method for fabricating Samples C1 and C3 is described below.
First, the conductive films 604a and 604b were formed over the substrate 602. As the substrate 602, a glass substrate was used. As each of the conductive films 604a and 604b, a stacked film including a 10-nm-thick titanium film and a 100-nm-thick copper film was formed with a sputtering apparatus.
Next, the insulating films 606 and 607 were formed over the substrate 602 and the conductive films 604a and 604b. As the insulating film 606, a 400-nm-thick silicon nitride film was formed with a PECVD apparatus. As the insulating film 607, a 50-nm-thick silicon oxynitride film was formed with a PECVD apparatus.
Next, heat treatment was performed. The heat treatment was performed at 350° C. in a nitrogen atmosphere for one hour.
Next, the oxide semiconductor film 609 was formed over the insulating film 607. Note that the oxide semiconductor film 609 in Sample C1 and the oxide semiconductor film 609 in Sample C3 were formed under different conditions.
As the oxide semiconductor film 609 in Sample C1, a 40-nm-thick IGZO film was formed. The IGZO film was formed under the following conditions: the substrate temperature was 170° C.; an argon gas with a flow rate of 100 sccm and an oxygen gas with a flow rate of 100 sccm were introduced into a chamber of the sputtering apparatus; the pressure was set to 0.6 Pa; and an AC power of 2.5 kW was applied to a metal oxide target containing indium, gallium, and zinc (In:Ga:Zn=1:1:1 [atomic ratio]). The oxygen flow rate ratio for fabricating Sample C1 was 50%.
As the oxide semiconductor film 609 in Sample C3, a 40-nm-thick IGZO film was formed. The IGZO film was formed under the following conditions: the substrate temperature was 130° C.; an argon gas with a flow rate of 180 sccm and an oxygen gas with a flow rate of 20 sccm were introduced into a chamber of the sputtering apparatus; the pressure was set to 0.6 Pa; and an AC power of 2.5 kW was applied to a metal oxide target containing indium, gallium, and zinc (In:Ga:Zn=4:2:4.1 [atomic ratio]). The oxygen flow rate ratio for fabricating Sample C3 was 10%.
Next, a resist mask was formed over the insulating film 607 and the oxide semiconductor film 609, and desired regions were etched to form the openings 644a and 644b reaching the conductive films 604a and 604b, respectively. The openings 644a and 644b were formed with a dry etching apparatus. Note that the resist mask was removed after the formation of the openings 644a and 644b.
Next, a conductive film was formed over the insulating film 607, the oxide semiconductor film 609, and the openings 644a and 644b. A resist mask was formed over the conductive film, and a desired region was etched to form the conductive films 612d and 612e. As each of the conductive films 612d and 612e, a stacked film including a 10-nm-thick titanium film and a 100-nm-thick copper film were formed with a sputtering apparatus. The resist mask was removed after the formation of the conductive films 612d and 612e.
Next, the insulating film 618 was formed over the insulating film 607, the oxide semiconductor film 609, and the conductive films 612d and 612e. As the insulating film 618, a 300-nm-thick silicon oxynitride film was formed with a PECVD apparatus.
Next, a resist mask was formed over the insulating film 618, and desired regions were etched to form the openings 646a and 646b reaching the conductive films 612d and 612e, respectively. The openings 646a and 646b were formed with a dry etching apparatus. Note that the resist mask was removed after the formation of the openings 646a and 646b.
Through the above steps, Samples C1 and C3 were fabricated.
In fabrication of Samples C2 and C4, the formation conditions of the insulating film 618 were different from those in fabrication of Samples C1 and C3.
As the insulating film 618 in each of Samples C2 and C4, a stacked film including a 100-nm-thick silicon nitride film and a 300-nm-thick silicon oxynitride film was formed with a PECVD apparatus.
Note that Sample C2 was fabricated under the same formation conditions as those of Sample C1, other than the formation condition of the insulating film 618. Sample C4 was fabricated under the same formation conditions as those of Sample C3, other than the formation condition of the insulating film 618.
Through the above steps, Samples C2 and C4 in this example were fabricated.
Next, Samples C1 to C4 were subjected to sheet resistance measurement.
As shown in
It was found that the sheet resistance of the oxide semiconductor film can be controlled by varying the formation condition of the oxide semiconductor film and the structure of the insulating film formed over the oxide semiconductor film as described above.
Note that the structure described in this example can be combined as appropriate with any of the structures described in the embodiments and the other examples.
In this example, transistors in each of which the oxide semiconductor film of one embodiment of the present invention is used for a channel region were fabricated, and Id-Vg characteristics of the transistors were examined.
In this example, Samples D1 to D4 were fabricated.
Note that Samples D1 to D4 are each a sample in which 4 transistors each corresponding to the transistor 100B illustrated in
The formation condition of the oxide semiconductor film was different between the fabrication of Samples D1 and D2 and the fabrication of Samples D3 and D4.
In the description below, the same reference numerals are used for components having functions similar to those in the components of the transistor 100B illustrated in
First, the substrate 102 was prepared. As the substrate 102, a glass substrate was used. Next, the conductive film 106 was formed over the substrate 102. For the conductive film 106, a 10-nm-thick titanium film and a 100-nm-thick copper film were formed with a sputtering apparatus.
Next, the insulating film 104 was formed over the substrate 102 and the conductive film 106. Note that in this example, as the insulating film 104, the insulating films 104_1, 104_2, 104_3, and 104_4 were successively formed in this order with a PECVD apparatus in a vacuum. A 50-nm-thick silicon nitride film was formed as the insulating film 104_1. A 300-nm-thick silicon nitride film was formed as the insulating film 104_2. A 50-nm-thick silicon nitride film was formed as the insulating film 104_3. A 50-nm-thick silicon oxynitride film was formed as the insulating film 104_4.
Next, an oxide semiconductor film was formed over the insulating film 104 and was processed into an island shape, whereby the oxide semiconductor film 108 was formed. A 40-nm-thick oxide semiconductor film was formed as the oxide semiconductor film 108.
Each of the oxide semiconductor films 108 in Samples D1 and D2 was formed under the following conditions: the substrate temperature was 170° C.; an argon gas with a flow rate of 100 sccm and an oxygen gas with a flow rate of 100 sccm were introduced into a chamber of the sputtering apparatus; the pressure was set to 0.6 Pa; and an AC power of 2.5 kW was applied to a metal oxide target containing indium, gallium, and zinc (In:Ga:Zn=1:1:1 [atomic ratio]). The oxygen flow rate ratio for fabricating Samples D1 and D2 was 50%.
Note that processing into the oxide semiconductor film 108 was performed by a wet etching method.
Next, an insulating film to be the insulating film 110 was formed over the insulating film 104 and the oxide semiconductor film 108. As the insulating film, a 150-nm-thick silicon oxynitride film was formed with a PECVD apparatus.
Next, heat treatment was performed. The heat treatment was performed at 350° C. in a mixed gas atmosphere of nitrogen and oxygen for one hour.
Next, the opening 143 was formed at desired regions in the insulating film 104 and the insulating film to be the insulating film 110. A formation method of the opening 143 was a dry etching method.
Next, a 100-nm-thick oxide semiconductor film was formed over the insulating film so as to cover the opening 143, and the oxide semiconductor film was processed into an island shape, whereby the conductive film 112 was formed. The insulating film in contact with the bottom surface of the conductive film 112 was processed in succession to the formation of the conductive film 112, whereby the insulating film 110 was formed.
As the conductive film 112, a 100-nm-thick oxide semiconductor film was formed. The oxide semiconductor film had a stacked-layer structure including two layers. A first layer of the oxide semiconductor film was formed to have a thickness of 10 nm under the following conditions: the substrate temperature was 170° C.; an oxygen gas with a flow rate of 200 sccm was introduced into a chamber of the sputtering apparatus; the pressure was set to 0.6 Pa; and an AC power of 2.5 kW was applied to a metal oxide target containing indium, gallium, and zinc (In:Ga:Zn=4:2:4.1 [atomic ratio]). A second layer of the oxide semiconductor film was formed to have a thickness of 90 nm under the following conditions: the substrate temperature was 170° C.; an argon gas with a flow rate of 180 sccm and an oxygen gas with a flow rate of 20 sccm introduced into a chamber of the sputtering apparatus; the pressure was set to 0.6 Pa; and an AC power of 2.5 kW was applied to a metal oxide target containing indium, gallium, and zinc (In:Ga:Zn=4:2:4.1 [atomic ratio]).
Note that processing into the conductive film 112 was performed by a wet etching method, and processing into the insulating film 110 was performed by a dry etching method.
Next, plasma treatment was performed from above the insulating film 104, the oxide semiconductor film 108, the insulating film 110, and the conductive film 112. The plasma treatment was performed with a PECVD apparatus at a substrate temperature of 220° C. in a mixed gas atmosphere containing an argon gas and a nitrogen gas.
Then, the insulating film 116 was formed over the insulating film 104, the oxide semiconductor film 108, the insulating film 110, and the conductive film 112. As the insulating film 116, a 100-nm-thick silicon nitride film was formed with a PECVD apparatus.
Next, the insulating film 118 was formed over the insulating film 116. As the insulating film 118, a 300-nm-thick silicon oxynitride film was formed with a PECVD apparatus.
Next, a mask was formed over the insulating film 118, and the openings 141a and 141b were formed in the insulating films 116 and 118 using the mask. Processing into the openings 141a and 141b was performed with a dry etching apparatus.
Next, a conductive film was formed over the insulating film 118 so as to fill the openings 141a and 141b and was processed into island shapes, whereby the conductive films 120a and 120b were formed.
For the conductive films 120a and 120b, a 10-nm-thick titanium film and a 100-nm-thick copper film were formed, respectively, with a sputtering apparatus.
Next, the insulating film 122 was formed over the insulating film 118 and the conductive films 120a and 120b. A 1.5-μm-thick acrylic-based photosensitive resin film was used as the insulating film 122.
Through the above steps, Samples D1 and D2 were fabricated.
In fabrications of Samples D3 and D4, a difference from the fabrication in Samples D1 and D2 is only the formation conduction of the oxide semiconductor film 108. Other than the formation condition of the oxide semiconductor film 108, the conditions were the same as those of Samples D1 and D2.
Each of the oxide semiconductor films 108 in Samples D3 and D4 was formed under the following conditions: the substrate temperature was 130° C.; an argon gas with a flow rate of 180 sccm and an oxygen gas with a flow rate of 20 sccm were introduced into a chamber of the sputtering apparatus; the pressure was set to 0.6 Pa; and an AC power of 2.5 kW was applied to a metal oxide target containing indium, gallium, and zinc (In:Ga:Zn=4:2:4.1 [atomic ratio]). The oxygen flow rate ratio for fabricating Samples D3 and D4 was 10%.
Through the above steps, Samples D3 and D4 were fabricated.
<4-3. Id-Vg Characteristics of Transistor>
Next, Id-Vg characteristics of Samples D1 to D4 were measured.
The measurement conditions of Id-Vg characteristics of the transistors were the same as those in Example 2. Note that in Samples D1 and D3, the range of voltage applied to Vg and Vbg was from −10 V to +10 V.
As shown in
Next, the on-state currents (Id) of the transistors in Samples D1 to D4 were compared.
As shown in
Next, a display device including transistors corresponding to those in Samples D3 and D4 was formed, and the display quality of the display device was evaluated. Table 2 shows specifications of the display device formed in this example.
Note that the structure described in this example can be combined as appropriate with any of the structures described in the embodiments and the other examples.
In this example, samples (Samples E1 to E3) each including an oxide semiconductor film were fabricated, and the resistivity in each sample was measured.
First, a structure and a fabrication method of each sample are described with reference to
As illustrated in
First, the oxide semiconductor film 1108 was formed over the substrate 1102 (see
A glass substrate was used as the substrate 1102, and a 40-nm-thick In—Ga—Zn oxide was formed as the oxide semiconductor film 1108 with a sputtering apparatus. The In—Ga—Zn oxide was formed under the following conditions: the substrate temperature was 170° C., an argon gas with a flow rate of 35 sccm and an oxygen gas with a flow rate of 15 sccm were introduced into a chamber, the pressure was 0.2 Pa, and AC power of 1500 W was supplied to a metal oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]) placed in the sputtering apparatus.
Next, the insulating film 1110 was formed over the oxide semiconductor film 1108 (see
For the insulating film 1110, a 150-nm-thick silicon oxynitride film was formed with a PECVD apparatus.
Next, heat treatment was performed at a substrate temperature of 350° C. in a nitrogen atmosphere for one hour.
Then, the oxide semiconductor film 1112 was formed over the insulating film 1110 (
The oxide semiconductor film 1112 had a stacked-layer structure including two layers. A first layer in the oxide semiconductor film was formed to have thickness of 10 nm under the following conditions: the substrate temperature was 170° C.; an oxygen gas with a flow rate of 200 sccm was introduced into a chamber of the sputtering apparatus; the pressure was set to 0.6 Pa; and an AC power of 2500 W was applied to a metal oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]) placed in the sputtering apparatus. A second layer in the oxide semiconductor film was formed to have a thickness of 90 nm under the following conditions: the substrate temperature was 170° C.; an argon gas with a flow rate of 180 sccm was introduced into a chamber of the sputtering apparatus; the pressure was set to 0.6 Pa; and an AC power of 2500 W was applied to a metal oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]) placed in the sputtering apparatus.
Next, the oxide semiconductor film 1112 and the insulating film 1110 were removed, whereby a surface of the oxide semiconductor film 1108 was exposed.
Through the above steps, Sample E1 of this example was fabricated.
[Method for fabricating Sample E2]
The fabrication process of Sample E2 is the same as that of Sample E1, except for a step described below.
In fabricating Sample E2, plasma treatment was performed before the insulating film 1110 was formed over the oxide semiconductor film 1108. In the plasma treatment, a PECVD apparatus was used, the substrate temperature was 350° C., an argon gas with a flow rate of 100 sccm was introduced into a chamber, the pressure was set to 40 Pa, and an RF power of 1000 W was applied.
The fabrication process of Sample E3 is the same as that of Sample E1, except for a step described below.
In fabricating Sample E3, plasma treatment was performed before the insulating film 1110 was formed over the oxide semiconductor film 1108. In the plasma treatment, a PECVD apparatus was used, the substrate temperature was 350° C., an argon gas with a flow rate of 100 sccm and a nitrogen gas with a flow rate of 100 sccm were introduced into a chamber, the pressure was set to 40 Pa, and an RF power of 1000 W was applied.
Next, the resistivity of the oxide semiconductor film in each of Samples E1 to E3 was measured.
According to the results shown in
Thus, it was found that the resistivity of the oxide semiconductor film was able to be reduced when the plasma treatment was performed after formation of the oxide semiconductor film.
The structure described in this example can be combined as appropriate with any of the structures described in other examples and the above embodiments.
In this example, a transistor in which the oxide semiconductor film of one embodiment of the present invention was used for a channel region was fabricated, and electrical characteristics of the transistor were measured. Note that Samples F1 to F4 were fabricated in this example.
Samples F1 and F3 each include a transistor with a channel length L of 2.0 μm and a channel width W of 50 μm, and Samples F2 and F4 each include a transistor with a channel length L of 3.0 μm and a channel width W of 50 μm.
Each of Samples F1 to F4 is a sample in which 20 transistors each corresponding to the transistor 100B illustrated in
First, the substrate 102 was prepared. As the substrate 102, a glass substrate was used. Next, the conductive film 106 was formed over the substrate 102. For the conductive film 106, a 10-nm-thick titanium film and a 100-nm-thick copper film were formed with a sputtering apparatus.
Next, the insulating film 104 was formed over the substrate 102 and the conductive film 106. Note that in this example, as the insulating film 104, the insulating films 104_1, 104_2, 104_3, and 104_4 were successively formed in this order with a PECVD apparatus in a vacuum. A 50-nm-thick silicon nitride film was formed as the insulating film 104_1. A 300-nm-thick silicon nitride film was formed as the insulating film 104_2. A 50-nm-thick silicon nitride film was formed as the insulating film 104_3. A 50-nm-thick silicon oxynitride film was formed as the insulating film 104_4.
Next, an oxide semiconductor film was formed over the insulating film 104 and was processed into an island shape, whereby the oxide semiconductor film 108 was formed. A 40-nm-thick oxide semiconductor film was formed as the oxide semiconductor film 108.
The oxide semiconductor film 108 was formed under the following conditions: the substrate temperature was 170° C.; an argon gas with a flow rate of 140 sccm and an oxygen gas with a flow rate of 60 sccm were introduced into a chamber of the sputtering apparatus; the pressure was set to 0.6 Pa; and an AC power of 2.5 kW was applied to a metal oxide target containing indium, gallium, and zinc (In:Ga:Zn=4:2:4.1 [atomic ratio]). The oxygen flow rate ratio for fabricating Sample F1 was 30%.
Note that processing into the oxide semiconductor film 108 was performed by a wet etching method.
Next, an insulating film to be the insulating film 110 was formed over the insulating film 104 and the oxide semiconductor film 108. As the insulating film, a 150-nm-thick silicon oxynitride film was formed with a PECVD apparatus.
Next, heat treatment was performed. The heat treatment was performed at 350° C. in a mixed gas atmosphere of nitrogen and oxygen for one hour.
Next, the opening 143 was formed at desired regions in the insulating film 104 and the insulating film to be the insulating film 110. A formation method of the opening 143 was a dry etching method.
Next, a 100-nm-thick oxide semiconductor film was formed over the insulating film so as to cover the opening 143, and the oxide semiconductor film was processed into an island shape, whereby the conductive film 112 was formed. The insulating film in contact with the bottom surface of the conductive film 112 was processed in succession to the formation of the conductive film 112, whereby the insulating film 110 was formed.
As the conductive film 112, a 100-nm-thick oxide semiconductor film was formed. The oxide semiconductor film had a stacked-layer structure including two layers. A first layer in the oxide semiconductor film was formed to have thickness of 10 nm under the following conditions: the substrate temperature was 170° C.; an oxygen gas with a flow rate of 200 sccm was introduced into a chamber of the sputtering apparatus; the pressure was set to 0.6 Pa; and an AC power of 2.5 kW was applied to a metal oxide target containing indium, gallium, and zinc (In:Ga:Zn=4:2:4.1 [atomic ratio]). A second layer in the oxide semiconductor film was formed to have a thickness of 90 nm under the following conditions: the substrate temperature was 170° C.; an argon gas with a flow rate of 180 sccm and an oxygen gas with a flow rate of 20 sccm were introduced into a chamber of the sputtering apparatus; the pressure was set to 0.6 Pa; and an AC power of 2.5 kW was applied to a metal oxide target containing indium, gallium, and zinc (In:Ga:Zn=4:2:4.1 [atomic ratio]).
Note that processing into the conductive film 112 was performed by a wet etching method, and processing into the insulating film 110 was performed by a dry etching method.
Then, the insulating film 116 was formed over the insulating film 104, the oxide semiconductor film 108, the insulating film 110, and the conductive film 112. As the insulating film 116, a 100-nm-thick silicon nitride film was formed with a PECVD apparatus.
Next, the insulating film 118 was formed over the insulating film 116. As the insulating film 118, a 300-nm-thick silicon oxynitride film was formed with a PECVD apparatus.
Next, a mask was formed over the insulating film 118, and the openings 141a and 141b were formed in the insulating films 116 and 118 using the mask. Processing into the openings 141a and 141b was performed with a dry etching apparatus.
Next, a conductive film was formed over the insulating film 118 so as to fill the openings 141a and 141b and was processed into island shapes, whereby the conductive films 120a and 120b were formed.
For the conductive films 120a and 120b, a 10-nm-thick titanium film and a 100-nm-thick copper film were formed, respectively, with a sputtering apparatus.
Next, the insulating film 122 was formed over the insulating film 118 and the conductive films 120a and 120b. A 1.5-μm-thick acrylic-based photosensitive resin film was used as the insulating film 122.
Through the above-described steps, the transistor corresponding to the transistor 100B illustrated in
Note that although the transistor size is different between Samples F1 and F2, the fabrication methods of Samples F1 and F2 are the same as each other.
The fabrication processes of Samples F3 and F4 are the same as those of Samples F1 and F2, except for a step described below.
In fabricating Samples F3 and F4, plasma treatment was performed on the insulating film 104, the oxide semiconductor film 108, the insulating film 110, and the conductive film 112 before the insulating film 116 was formed. In the plasma treatment, a PECVD apparatus was used, the substrate temperature was 220° C., an argon gas with a flow rate of 100 sccm was introduced into a chamber, the pressure was set to 40 Pa, and an RF power of 1000 W was applied.
Note that although the transistor size is different between Samples F3 and F4, the fabrication methods of Samples F3 and F4 are the same as each other.
<6-3. Id-Vg Characteristics of Transistor>
Next, Id-Vg characteristics of Samples F1 to F4 were measured.
The measurement conditions of Id-Vg characteristics of the transistors were the same as those in Example 2.
As shown in
Note that the structure described in this example can be combined as appropriate with any of the structures described in the embodiments or the other examples.
In this example, a transistor in which the oxide semiconductor film of one embodiment of the present invention is used for a channel region was fabricated, and electrical characteristics of the transistor were measured. Samples G1 and G2 were fabricated in this example.
Sample G1 includes a transistor with a channel length L of 2.0 μm and a channel width W of 50 μm, and Sample G2 includes a transistor with a channel length L of 3.0 μm and a channel width W of 50 μm.
Each of Samples G1 and G2 is a sample in which 20 transistors each corresponding to the transistor 100B illustrated in
First, the substrate 102 was prepared. As the substrate 102, a glass substrate was used. Next, the conductive film 106 was formed over the substrate 102. For the conductive film 106, a 10-nm-thick titanium film and a 100-nm-thick copper film were formed with a sputtering apparatus.
Next, the insulating film 104 was formed over the substrate 102 and the conductive film 106. Note that in this example, as the insulating film 104, the insulating films 104_1, 104_2, 104_3, and 104_4 were successively formed in this order with a PECVD apparatus in a vacuum. A 50-nm-thick silicon nitride film was formed as the insulating film 104_1. A 300-nm-thick silicon nitride film was formed as the insulating film 104_2. A 50-nm-thick silicon nitride film was formed as the insulating film 104_3. A 50-nm-thick silicon oxynitride film was formed as the insulating film 104_4.
Next, an oxide semiconductor film was formed over the insulating film 104 and was processed into an island shape, whereby the oxide semiconductor film 108 was formed. A 40-nm-thick oxide semiconductor film was formed as the oxide semiconductor film 108.
The oxide semiconductor film 108 was formed under the following conditions: the substrate temperature was 170° C.; an argon gas with a flow rate of 140 sccm and an oxygen gas with a flow rate of 60 sccm were introduced into a chamber of the sputtering apparatus; the pressure was set to 0.6 Pa; and an AC power of 2.5 kW was applied to a metal oxide target containing indium, gallium, and zinc (In:Ga:Zn=4:2:4.1 [atomic ratio]). The oxygen flow rate ratio for fabricating Samples G1 and G2 was 30%.
Note that processing into the oxide semiconductor film 108 was performed by a wet etching method.
Next, an insulating film to be the insulating film 110 was formed over the insulating film 104 and the oxide semiconductor film 108. As the insulating film, a 50-nm-thick silicon oxynitride film was formed with a PECVD apparatus.
Next, heat treatment was performed at 350° C. in a nitrogen gas atmosphere for one hour.
Next, the opening 143 was formed at desired regions in the insulating film 104 and the insulating film to be the insulating film 110. A formation method of the opening 143 was a dry etching method.
Next, a 100-nm-thick oxide semiconductor film was formed over the insulating film to cover the opening 143, and the oxide semiconductor film was processed into an island shape, whereby the conductive film 112 was formed. The insulating film in contact with the bottom surface of the conductive film 112 was processed in succession to the formation of the conductive film 112, whereby the insulating film 110 was formed.
As the conductive film 112, a 100-nm-thick oxide semiconductor film was formed. The oxide semiconductor film had a stacked-layer structure including two layers. A first layer in the oxide semiconductor film was formed to have thickness of 10 nm under the following conditions: the substrate temperature was 170° C.; an oxygen gas with a flow rate of 200 sccm was introduced into a chamber of the sputtering apparatus; the pressure was set to 0.6 Pa; and an AC power of 2.5 kW was applied to a metal oxide target containing indium, gallium, and zinc (In:Ga:Zn=4:2:4.1 [atomic ratio]). A second layer in the oxide semiconductor film was formed to have a thickness of 90 nm under the following conditions: the substrate temperature was 170° C.; an argon gas with a flow rate of 180 sccm and an oxygen gas with a flow rate of 20 sccm were introduced into a chamber of the sputtering apparatus; the pressure was set to 0.6 Pa; and an AC power of 2.5 kW was applied to a metal oxide target containing indium, gallium, and zinc (In:Ga:Zn=4:2:4.1 [atomic ratio]).
Note that processing into the conductive film 112 was performed by a wet etching method, and processing into the insulating film 110 was performed by a dry etching method.
Next, plasma treatment was performed on the insulating film 104, the oxide semiconductor film 108, the insulating film 110, and the conductive film 112. In the plasma treatment, a PECVD apparatus was used, the substrate temperature was 220° C., an argon gas with a flow rate of 100 sccm and a nitrogen gas with a flow rate of 1000 sccm were introduced into a chamber, the pressure was set to 40 Pa, and an RF power of 1000 W was applied.
Then, the insulating film 116 was formed over the insulating film 104, the oxide semiconductor film 108, the insulating film 110, and the conductive film 112. As the insulating film 116, a 100-nm-thick silicon nitride film was formed with a PECVD apparatus. The above plasma treatment and the formation of the insulating film 116 were successively performed in this order with a PECVD apparatus in a vacuum.
Next, the insulating film 118 was formed over the insulating film 116. As the insulating film 118, a 300-nm-thick silicon oxynitride film was formed with a PECVD apparatus.
Next, a mask was formed over the insulating film 118, and the openings 141a and 141b were formed in the insulating films 116 and 118 using the mask. Processing into the openings 141a and 141b was performed with a dry etching apparatus.
Next, a conductive film was formed over the insulating film 118 so as to fill the openings 141a and 141b and was processed into island shapes, whereby the conductive films 120a and 120b were formed.
For the conductive films 120a and 120b, a 10-nm-thick titanium film and a 100-nm-thick copper film were formed, respectively, with a sputtering apparatus.
Next, the insulating film 122 was formed over the insulating film 118 and the conductive films 120a and 120b. A 1.5-μm-thick acrylic-based photosensitive resin film was used as the insulating film 122.
Through the above-described steps, the transistor corresponding to the transistor 100B illustrated in
Note that although the transistor size is different between Samples G1 and G2, the fabrication methods of Samples G1 and G2 are the same as each other
<7-2. Id-Vg Characteristics of Transistor>
Next, Id-Vg characteristics of Samples G1 and G2 were measured.
The measurement conditions of Id-Vg characteristics of the transistors were the same as those in Example 2.
As shown in
<7-3. Id/W−Vd Characteristics>
Next, Id/W−Vd characteristics of the transistors in Samples G1 and G2 were measured. Note that one transistor was randomly selected in each of Samples G1 and G2, and Id/W−Vd characteristics of the transistors were measured.
As the conditions for measuring the Id/W−Vd characteristics of the transistor in Sample G1, Vg and Vbg were each 4.5 V, Vs was 0 V (comm), and Vd was applied from 0 V to 12 V at intervals of 0.25 V. As the conditions for measuring the Id/W−Vd characteristics of the transistor in Sample G2, Vg and Vbg were each 4.05 V, Vs was 0 V (comm), and Vd was applied from 0 V to 12 V at intervals of 0.25 V.
As shown in
Next, a cross section at an end of a gate, in the channel length direction, of one transistor in Sample G1 was observed. Note that the cross-sectional observation was performed with a scanning transmission electron microscope (STEM).
In
Note that the structure described in this example can be combined as appropriate with any of the structures described in the embodiments or the other examples.
In this example, a transistor in which the oxide semiconductor film of one embodiment of the present invention is used for a channel region was fabricated, and electrical characteristics of the transistor were measured. Sample H1 was fabricated in this example.
Note that Sample H1 was a transistor with a channel length L of 0.75 μm and a channel width W of 3 μm.
Note that Sample H1 is a sample in which transistors each corresponding to the transistor 100B illustrated in
First, the substrate 102 was prepared. As the substrate 102, a glass substrate was used. Next, the conductive film 106 was formed over the substrate 102. For the conductive film 106, a 10-nm-thick titanium film and a 100-nm-thick copper film were formed with a sputtering apparatus.
Next, the insulating film 104 was formed over the substrate 102 and the conductive film 106. Note that in this example, as the insulating film 104, the insulating films 104_1, 104_2, 104_3, and 104_4 were successively formed in this order with a PECVD apparatus in a vacuum. A 50-nm-thick silicon nitride film was formed as the insulating film 104_1. A 300-nm-thick silicon nitride film was formed as the insulating film 104_2. A 50-nm-thick silicon nitride film was formed as the insulating film 104_3. A 50-nm-thick silicon oxynitride film was formed as the insulating film 104_4.
Next, an oxide semiconductor film was formed over the insulating film 104 and was processed into an island shape, whereby the oxide semiconductor film 108 was formed. A 40-nm-thick oxide semiconductor film was formed as the oxide semiconductor film 108.
The oxide semiconductor film 108 was formed under the following conditions: the substrate temperature was 170° C.; an argon gas with a flow rate of 140 sccm and an oxygen gas with a flow rate of 60 sccm were introduced into a chamber of the sputtering apparatus; the pressure was set to 0.6 Pa; and an AC power of 2.5 kW was applied to a metal oxide target containing indium, gallium, and zinc (In:Ga:Zn=4:2:4.1 [atomic ratio]). The oxygen flow rate ratio for fabricating Sample H1 was 30%.
Note that processing into the oxide semiconductor film 108 was performed by a wet etching method.
Next, an insulating film to be the insulating film 110 was formed over the insulating film 104 and the oxide semiconductor film 108. As the insulating film, a 50-nm-thick silicon oxynitride film was formed with a PECVD apparatus.
Next, heat treatment was performed at 350° C. in a nitrogen gas atmosphere for one hour.
Next, the opening 143 was formed at desired regions in the insulating film 104 and the insulating film to be the insulating film 110. A formation method of the opening 143 was a dry etching method.
Next, a 100-nm-thick oxide semiconductor film was formed over the insulating film so as to cover the opening 143, and the oxide semiconductor film was processed into an island shape, whereby the conductive film 112 was formed. The insulating film in contact with the bottom surface of the conductive film 112 was processed in succession to the formation of the conductive film 112, whereby the insulating film 110 was formed.
As the conductive film 112, a 100-nm-thick oxide semiconductor film was formed. The oxide semiconductor film had a stacked-layer structure including two layers. A first layer in the oxide semiconductor film was formed to have thickness of 10 nm under the following conditions: the substrate temperature was 170° C.; an oxygen gas with a flow rate of 200 sccm was introduced into a chamber of the sputtering apparatus; the pressure was set to 0.6 Pa; and an AC power of 2.5 kW was applied to a metal oxide target containing indium, gallium, and zinc (In:Ga:Zn=4:2:4.1 [atomic ratio]). A second layer in the oxide semiconductor film was formed to have a thickness of 90 nm under the following conditions: the substrate temperature was 170° C.; an argon gas with a flow rate of 180 sccm and an oxygen gas with a flow rate of 20 sccm were introduced into a chamber of the sputtering apparatus; the pressure was set to 0.6 Pa; and an AC power of 2.5 kW was applied to a metal oxide target containing indium, gallium, and zinc (In:Ga:Zn=4:2:4.1 [atomic ratio]).
Note that processing into the conductive film 112 was performed by a wet etching method, and processing into the insulating film 110 was performed by a dry etching method.
Next, plasma treatment was performed on the insulating film 104, the oxide semiconductor film 108, the insulating film 110, and the conductive film 112. In the plasma treatment, a PECVD apparatus was used, the substrate temperature was 220° C., an argon gas with a flow rate of 100 sccm and a nitrogen gas with a flow rate of 1000 sccm were introduced into a chamber, the pressure was set to 40 Pa, and an RF power of 1000 W was applied.
Then, the insulating film 116 was formed over the insulating film 104, the oxide semiconductor film 108, the insulating film 110, and the conductive film 112. As the insulating film 116, a 100-nm-thick silicon nitride film was formed with a PECVD apparatus. The above plasma treatment and the formation of the insulating film 116 were successively performed in this order with a PECVD apparatus in a vacuum.
Next, the insulating film 118 was formed over the insulating film 116. As the insulating film 118, a 300-nm-thick silicon oxynitride film was formed with a PECVD apparatus.
Next, a mask was formed over the insulating film 118, and the openings 141a and 141b were formed in the insulating films 116 and 118 using the mask. Processing into the openings 141a and 141b was performed with a dry etching apparatus.
Next, a conductive film was formed over the insulating film 118 so as to fill the openings 141a and 141b and was processed into island shapes, whereby the conductive films 120a and 120b were formed.
For the conductive films 120a and 120b, a 10-nm-thick titanium film and a 100-nm-thick copper film were formed, respectively, with a sputtering apparatus.
Next, the insulating film 122 was formed over the insulating film 118 and the conductive films 120a and 120b. A 1.5-μm-thick acrylic-based photosensitive resin film was used as the insulating film 122.
Through the above-described steps, the transistor corresponding to the transistor 100B illustrated in
<8-2. Id-Vg Characteristics of Transistor>
Next, Id-Vg characteristics of Sample H1 were measured.
The measurement conditions of Id-Vg characteristics of the transistor were the same as those in Example 2. Note that the range of voltage applied to Vg and Vbg was from −10 V to +10 V.
As shown in
Next, a cross section of the transistor, in the channel length direction, of Sample H1 was observed. The cross-sectional observation was performed with an STEM.
As shown in
Note that the structure described in this example can be combined as appropriate with any of the structures described in the embodiments or the other examples.
100: transistor, 100A: transistor, 100B: transistor, 100C: transistor, 100D: transistor, 100E: transistor, 100F: transistor, 100G: transistor, 100H: transistor, 100J: transistor, 100K: transistor, 102: substrate, 104: insulating film, 104_1: insulating film, 104_2: insulating film, 104_3: insulating film, 104_4: insulating film, 106: conductive film, 108: oxide semiconductor film, 108_1: oxide semiconductor film, 108_2: oxide semiconductor film, 108_3: oxide semiconductor film, 108d: drain region, 108f: region, 108i: channel region, 108s: source region, 110: insulating film, 112: conductive film, 112_1: conductive film, 112_2: conductive film, 114: insulating film, 116: insulating film, 118: insulating film, 120a: conductive film, 120b: conductive film, 122: insulating film, 141a: opening, 141b: opening, 143: opening, 300A: transistor, 300B: transistor, 300C: transistor, 300D: transistor, 300E: transistor, 300F: transistor, 300G: transistor, 302: substrate, 304: conductive film, 306: insulating film, 307: insulating film, 308: oxide semiconductor film, 308_1: oxide semiconductor film, 308_2: oxide semiconductor film, 308_3: oxide semiconductor film, 312a: conductive film, 312b: conductive film, 312c: conductive film, 314: insulating film, 316: insulating film, 318: insulating film, 320a: conductive film, 320b: conductive film, 341a: opening, 341b: opening, 342a: opening, 342b: opening, 342c: opening, 351: opening, 352a: opening, 352b: opening, 501: pixel circuit, 502: pixel portion, 504: driver circuit portion, 504a: gate driver, 504b: source driver, 506: protection circuit, 507: terminal portion, 550: transistor, 552: transistor, 554: transistor, 560: capacitor, 562: capacitor, 570: liquid crystal element, 572: light-emitting element, 602: substrate, 604a: conductive film, 604b: conductive film, 606: insulating film, 607: insulating film, 609: oxide semiconductor film, 612d: conductive film, 612e: conductive film, 618: insulating film, 642a: opening, 644a: opening, 644b: opening, 646a: opening, 646b: opening, 650: sample for evaluation, 664: electrode, 665: electrode, 667: electrode, 700: display device, 701: substrate, 702: pixel portion, 704: source driver circuit portion, 705: substrate, 706: gate driver circuit portion, 708: FPC terminal portion, 710: signal line, 711: wiring portion, 712: sealant, 716: FPC, 730: insulating film, 732: sealing film, 734: insulating film, 736: coloring film, 738: light-blocking film, 750: transistor, 752: transistor, 760: connection electrode, 770: planarization insulating film, 772: conductive film, 773: insulating film, 774: conductive film, 775: liquid crystal element, 776: liquid crystal layer, 778: structure body, 780: anisotropic conductive film, 782: light-emitting element, 786: EL layer, 788: conductive film, 790: capacitor, 791: touch panel, 792: insulating film, 793: electrode, 794: electrode, 795: insulating film, 796: electrode, 797: insulating film, 800: inverter, 810: OS transistor, 820: OS transistor, 831: signal waveform, 832: signal waveform, 840: dashed line, 841: solid line, 850: OS transistor, 860: CMOS inverter, 900: semiconductor device, 901: power supply circuit, 902: circuit, 903: voltage generation circuit, 903A: voltage generation circuit, 903B: voltage generation circuit, 903C: voltage generation circuit, 904: circuit, 905: voltage generation circuit, 906: circuit, 911: transistor, 912: transistor, 912A: transistor, 912B: transistor, 921: control circuit, 922: transistor, 1102: substrate, 1108: oxide semiconductor film, 1110: insulating film, 1112: oxide semiconductor film, 7000: display module, 7001: upper cover, 7002: lower cover, 7003: FPC, 7004: touch panel, 7005: FPC, 7006: display panel, 7007: backlight, 7008: light source, 7009: frame, 7010: printed board, 7011: battery, 8000: camera, 8001: housing, 8002: display portion, 8003: operation button, 8004: shutter button, 8006: lens, 8100: finder, 8101: housing, 8102: display portion, 8103: button, 8200: head-mounted display, 8201: mounting portion, 8202: lens, 8203: main body, 8204: display portion, 8205: cable, 8206: battery, 8300: head-mounted display, 8301: housing, 8302: display portion, 8304: fixing band, 8305: lens, 9000: housing, 9001: display portion, 9003: speaker, 9005: operation key, 9006: connection terminal, 9007: sensor, 9008: microphone, 9050: operation button, 9051: information, 9052: information, 9053: information, 9054: information, 9055: hinge, 9100: television device, 9101: portable information terminal, 9102: portable information terminal, 9200: portable information terminal, 9201: portable information terminal, 9500: display device, 9501: display panel, 9502: display region, 9503: region, 9511: hinge, 9512: bearing
This application is based on Japanese Patent Application serial no. 2015-241798 filed with Japan Patent Office on Dec. 11, 2015, the entire contents of which are hereby incorporated by reference.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2015-241798 | Dec 2015 | JP | national |
