Patent Application
20050139984
The present invention relates to the packaging of microelectronic elements, e.g., chips, and micro-electromechanical (MEMs) devices.
In fabricating integrated circuits, also referred to herein as “chips”, protecting the delicate structures that make up the chips are a monumental concern. This is particularly true for chips that are vulnerable to certain environments. For example, chips which include electrical, micro-electromechanical (MEMs) devices or optical components have delicate structures which need to be protected from contamination and other damage.
The functionality of many types of electronic systems, for example, radio transmitters and receivers that are operated at a radio frequency (RF), is improved if the circuit contains filters at particular locations to help resolve wanted signals from unwanted signals and noise. There are many methods of realizing filters for electronic signals, including resistor-capacitor-inductor networks, micro-electromechanical devices, also known as “MEMs” devices, and active circuits. Such circuits and corresponding components are quite delicate. Of particular interest to mobile telephone applications are micro-electromechanical filters or “MEMs filters”. These offer an attractive trade-off in terms of performance, size and manufacturing cost. The two principal types of MEMs filters are Surface Acoustic Wave (SAW) filters or devices and Thin Film Bulk Acoustic Resonators (FBAR).
At a simplistic level, a MEMs filter can be considered as a miniaturized tuning fork. The incoming electrical signals are converted to a mechanical motion and then back to an electrical signal. The mechanical structure is designed to have a narrow passband characterized by a resonant frequency so that electrical signals which match the resonant frequency pass through the component largely un-attenuated, while signals other than the resonant frequency are rejected, i.e., greatly diminished in amplitude.
A SAW filter is realized by forming two or more electrode structures on the surface of a piezo-electrically active material, such as lithium tantalate, quartz, aluminum nitride or diamond. A piezoelectric material changes its physical dimension in response to an applied electric field and thereby provides electrical-to-mechanical conversion and vice versa. The speed at which pressure waves propagate through the piezoelectric material and the spacing between the set of electrodes sets the operational frequency of the device.
Some types of integrated circuits, i.e., chips, are especially delicate, being sensitive to heat, jarring material strain, and other factors that stress their components. For such circuits, it is not only desirable, but may be essential to take special precautions during the manufacture of such chips to prevent catastrophic failure. An example of a sensitive device that requires extraordinary care during the packaging process is a SAW device. A SAW device typically comprises a very fine electrode structure on the surface of a piezoelectric material such as lithium tantalate. The structure usually has very closely spaced fingers of electrodes, which may be interdigitated. Due to such structure, the breakdown voltage between adjacent fingers of a SAW device is small. Sensitive circuits like SAW devices are typically fabricated in piezoelectric materials, which exhibit an external electric field when a mechanical stress is applied to the material. A charge flow may be observed when a closed circuit is attached to electrodes on the surface of the material when stress is applied. Piezoelectric materials further possess pyroelectric properties. Pyroelectric properties cause thermal excursions in a SAW device when the device is stressed during wafer processing. These thermal excursions generate charges that can destroy SAW devices. SAW devices must undergo a number of thermal excursions during processing and packaging, SAW devices are at risk of catastrophic failure from electrostatic discharge (ESD) during such processing and packaging. There are several conventional attempts to mitigate this problem, but they each have shortcomings.
One approach to mitigating this problem is to invoke process restrictions. The magnitude of the charge developed depends, to a certain extent, on the rate of heating or cooling as the charge slowly dissipates due to leakage through the substrate and across its surface. Restricting the maximum rate of temperature change during processing helps prevent excessive charge being developed. Unfortunately, such restrictions limit equipment throughput and may compromise the effectiveness of other processes, such as soldering, that function best when the temperature excursion is rapid.
Another approach is to limit substrate leakage by using a substrate material having low resistivity. This allows the charge developed by the pyroelectric effect to be limited for a given rate of temperature change. This is typically achieved by incorporating a dopant into the substrate. However, because the resistivity of the substrate material affects the efficiency of conversion of electrical charge to mechanical displacement, doped substrates have lower piezoelectric coefficients. This makes them less useful for SAW device and other sensitive circuit applications.
Still another approach is illustrated in a plan view of a SAW device chip shown in
As further shown in
However, in conventional processes, the stubs of the tie-bar connections between the bond pads and the common guard ring have an undesirable influence upon the behavior of the chip in the RF domain that adversely affects the performance of the filter employing a SAW device.
Accordingly, there exists a need for an improved package element, packaged chip and method for packaging a chip which addresses the special vulnerabilities of SAW devices and other sensitive chips.
In addition, there exists a need for a cap or package element, capped chip and method for packaging a chip which facilitates the simultaneous assembly of a cap wafer having a large area to a device wafer or other multiple chip-containing substrate, which cap wafer addresses the special vulnerabilities of SAW devices and other sensitive chips.
According to one aspect of the invention, a capped chip is provided which includes a chip having a front surface, a back surface opposite the front surface and a plurality of bond pads exposed at at least one of the front and back surfaces. A cap is joined to the chip, the cap overlying one of the front and back surfaces of the chip. The cap includes a plurality of contacts which are conductively interconnected to the bond pads, and one or more temporary ties which conductively connect two or more of the contacts. The temporary ties are severable after the contacts are conductively interconnected to the bond pads.
According to another aspect of the invention, a cap is provided which is adapted to at least partially cover and provide conductive interconnection to the chip. Such cap includes a plurality of contacts adapted to be conductively interconnected to bond pads of the chip, and one or more temporary ties which conductively connect two or more of the contacts. The temporary ties are severable after the contacts are conductively interconnected to the bond pads.
According to yet another aspect of the invention, a capped chip is provided which includes a chip having a front surface, a back surface opposite the front surface and a plurality of bond pads exposed at the front surface. A cap overlies and is joined to the front surface of the chip, the cap having a plurality of contacts conductively interconnected to the bond pads. The cap further includes one or more temporary ties which conductively connect two or more of the contacts, the temporary ties being severable after the contacts are conductively interconnected to the bond pads.
According to another aspect of the invention, a method is provided for fabricating capped chips. Such method includes aligning a cap element to a substrate including a plurality of chips attached to each other at dicing lanes defining boundaries between the chips, the chips having an outer surface between the dicing lanes and bond pads exposed at the outer surface, the cap element including a plurality of contacts and one or more temporary ties conductively interconnecting the contacts. The cap element is joined to the substrate and conductive interconnects are formed between the bond pads and the contacts to form capped chips. The one or more temporary ties of each chip are severed after forming the conductive interconnects.
In the embodiments of the invention described herein, a way is provided for protecting SAW devices or other chips against electrostatic discharge (ESD) during steps of the packaging process by which protective caps are joined to the chips. As described in the background, in wafer form, SAW devices are susceptible to damage due to the pyroelectric properties of common substrate materials. The propensity for ESD within the interdigitated electrodes of a SAW device is decreased by providing conductive ties on the SAW device which tie all of the bond pads to a guard ring. When the joined structure of the cap wafer and SAW device wafer are singulated into individual units, the conductive ties are severed from the guard ring. However, the placement of such ties on the SAW device make them impossible to fully remove, such that the ties remain on the SAW device as undesirable stubs which are sources of electromagnetic interference.
The embodiments of the invention address this concern by placing temporary conductive ties and a guard ring structure on a cap wafer rather than on the SAW device chip. After the cap wafer is joined to the SAW device wafer, the temporary ties remain accessible. For that reason, the temporary ties and/or guard ring structure can then be removed, even completely removed in an appropriate case, by ways other than sawing a joined wafer assembly into individual capped chips. With the more thorough removal of the conductive ties, improved RF performance is achieved than in chips packaged in accordance with conventional methods. A guard ring provided on a cap of such cap wafer element may also be placed within the area defined by the peripheral edges of an individual singulated chip, effectively saving space on the wafer.
In a particular embodiment, the temporary ties used to make the conductive ties are soluble in a fusible conductive material such as a solder. In a particular form of this embodiment, the temporary ties are soluble in a solder used either to seal the package or attach the package to a substrate by a surface mount method, and the temporary ties are designed to be severed by dissolving into the solder during a solder bonding process.
The embodiments of the invention will now be described with reference to
The cap wafer 100 shown in
After such SAW device chip-containing wafer has been aligned and joined to the cap wafer, and suitable interconnections and processing have been performed, the two joined wafers are severed by sawing through dicing lanes 110. When the cap 102 remains attached to other caps in form of a cap wafer, the temporary conductive ties 104 are conductively connected together through the metallic guard ring 108, having low impedance at frequencies in which pyroelectric effects during manufacturing are most likely to be observed. This property allows the guard ring and temporary ties 108 for each cap 102 of the cap wafer 100 to protect the SAW device from damaging electrostatic discharges, as the contacts 106 of cap 102 are connected to corresponding bond pads of a SAW device chip.
By the herein described processes, the temporary ties and the guard ring can be formed on the cap portion of a capped chip in a number of different configurations and by a number of different processes, without concern for leaving residual tie bars behind as is the case when the tie bars are provided on the SAW device chip (
A particular embodiment of a singulated capped chip is shown in the sectional view of
With specific reference to
Alternatively, when the protrusion 444 conductively contacts the bond pad 208, a nonconductive adhesive can be used in place of the conductive adhesive 446. Alternatively, a fusible conductive medium such as solder is used in place of the conductive adhesive. In such case, a mass of fusible material such as solder is preferably applied as a bump to the protrusion 444 or the corresponding location of the trace 440, if the protrusion is not present, before the cap wafer is bonded to the chip wafer. The cap wafer and the chip wafer are then heated to cause the solder to reflow, thus forming a solder mass bonding the two wafers in the place where the conductive adhesive 446 is shown.
In one embodiment, the cap wafer is formed by patterning a layer of metal on the cap wafer to form the redistribution traces 440, after which the through holes are formed by an etching process or other removal process which is endpointed upon reaching the redistribution traces 440. Bonding layers 107 are then formed on walls of the through holes, as needed, and the through holes are then are then filled with the conductive material, that material preferably being a fusible conductive material such as solder.
Further, each chip 202 is preferably sealed to the cap 102 by way of a seal 111 which is formed as a “picture frame ring seal” to extend along the peripheral edges 452 of the cap and the peripheral edges 453 of the chip, so as to seal the cap 102 to the chip 202 while enclosing a central void 454 occupied by a gas or a vacuum. When the chip is a SAW device chip, the seal 111 is required to be a hermetic seal to prevent ingress of moisture or other material which could alter or contaminate the SAW device, causing it to malfunction. As there is no such thing as an absolutely leak free enclosure, “hermeticity” is defined as the degree to which an enclosure protects against the leaking of material, e.g., gas or other fluid to or from the enclosure, in terms of a maximum permissible leak rate for the application. In a particular example, for many silicon semiconductor devices, a package is considered to be hermetic if is has a leak rate of helium below 1×10−8 Pa m3/sec. The hermetic package needs to provide protection during exposure to a diversity of external environments. These include normal service conditions, shipping and storage, accelerated life tests conducted for quality assurance purposes and other steps of the manufacturing and assembly process.
As shown in the top plan view of
However, the sawing process is not able to sever the temporary ties 449 which connect adjacent ones of the contacts 442 on the outer surface 105 of the cap. Accordingly, a method other than the sawing process must be used to sever the temporary ties 449. For example, the temporary ties 449 can be severed through ablation caused by laser illumination, for example.
According to one embodiment, laser illumination is available for use in ablating portions of the temporary ties which are disposed on the outer surface 105 of the cap. However, in a particular embodiment, when the cap is provided of a material which is at least partially optically transmissive to the wavelength of the laser illumination, the temporary ties can be disposed on the inner surface, rather than the outer surface of the cap. In such case, the laser illumination can be directed through the cap of the capped chip to the temporary ties disposed along the inner surface of the cap to cause ablation of the ties, and, therefore, disconnect such ties from the contacts.
Another way of severing temporary ties disposed on the outer surface of the cap is through localized heating. For example, the temporary ties can be contacted with a heated tool, e.g. probing tool, causing the ties to melt and to pull back from the location of the heated tool, for example, due to surface tension. Alternatively or in addition thereto, some of the metal may be drawn onto the probe. In one example, the heated tool contains multiple metallic prongs which are simultaneously contacted to multiple temporary ties in order to sever them all at once.
Another way that the temporary ties can be severed is through etching. After the chip wafer is joined to the cap wafer and sealed thereto to prevent ingress of moisture, an etchant can be applied to the outer surface of the cap and allowed to etch the material of the conductive ties until the conductive tie has been disconnected from the contacts. When the conductive ties are made thin in relation to the structure of the contacts, the etchant will remove the conductive ties without removing too much of the material of the contacts. Etching is an advantageous method to be used for this purpose because when the etchant is allowed to contact the whole outer surface of the cap, the etchant will not only disconnect the temporary ties, but can clean the surface of the cap sufficiently to prevent stubs from remaining after the etching operation.
Another way that the temporary ties can be severed is by mechanical abrasion. For example, polishing equipment can be used to abrade the outer surface of the capped chip such that thin temporary ties are removed from the outer surface, while leaving the contacts thereon substantially undisturbed.
A particular embodiment of a cap having ties which are severed by a process other than sawing will now be described with reference to
The contact 504 is such as typically provided as a solder-bondable contact, having an under bump metallization (UBM) which includes three conductive layers: a bonding layer 506 overlying a barrier layer 508, which in turn overlies a base layer 510. As specifically shown in
In one embodiment, cap 500 includes a dielectric or semiconducting element, consisting essentially of glass, ceramic or semiconductor material, for example. In another embodiment, the cap can be formed as a conductive, e.g., metallic element on which an insulating layer (not shown) is provided for insulating the contacts, UBM, and temporary conductive ties from the metallic element.
As particularly shown in
The results obtained after the molten solder contacts the contact 504 and the temporary tie are illustrated in
Referring again to
In the embodiment shown in
As in the above-described embodiment, the cap 702 is sealed to the chip 202 through a sealing medium 711, which can be hermetic for the purposes required by the device 204, e.g., such as when the chip includes a SAW device.
As further shown in the plan view of
In a further embodiment shown in
Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims.
This application claims the benefit of the filing date of U.S. Provisional Application No. 60/531,030 filed Dec. 19, 2003, the disclosure of which is hereby incorporated by reference herein.
| Number | Date | Country | |
|---|---|---|---|
| 60531030 | Dec 2003 | US |
