Claims
- 1. A printer controller, implemented as a single chip superscalar microprocessor, comprising:
- (1) a printer video processor for generating a plurality of control signals for a printer engine, for generating memory addresses of data to be fetched, for serializing fetched data, and for providing serialized data to said printer engine;
- (2) an instruction processor comprising:
- a plurality of graphical functional units, interconnected in said instruction processor as internal functional units to support operation of said printer video processor, comprising
- an orthogonal rotator unit for assembling blocks of orthogonally rotated bit map data,
- a bit/byte mirror unit for outputting received data in reverse order, and
- a pixel modification unit for modifying pixels in response to graphics instructions;
- a plurality of register files and multiplexers interconnecting said register files with said graphical functional units; and
- an instruction scheduler for issuing instructions in parallel to said graphical functional units; and
- (3) a memory controller, coupled to said printer video processor, for receiving and processing memory transaction requests from said printer video processor.
- 2. The printer controller of claim 1, wherein said printer video processor includes a register file interconnected to said memory controller, an adder for performing arithmetic operations with data received from said register file to generate addresses and printer control signals, and a video serializer for receiving data from memory and serializing said data for transfer to said primer engine.
- 3. The printer controller of claim 1, wherein said primer video processor cooperatively functions with said instruction processor in generating timing signals, performing scan data fetches and serialization, printer contact, and printer synchronization.
- 4. A data processing system, comprising:
- a printer engine; and
- a printer controller, implemented as a single chip superscalar microprocessor, comprising:
- (1) a printer video processor for generating a plurality of control signals for a printer engine, for generating memory addresses of data to be fetched, for serializing fetched data, and for providing serialized data to said printer engine;
- (2) an instruction processor comprising:
- a plurality of graphical functional units, interconnected in said instruction processor as internal functional units to support operation of said printer video processor, comprising
- an orthogonal rotator unit for assembling blocks of orthogonally rotated bit map data,
- a bit/byte mirror unit for outputting received data in reverse order, and
- a pixel modification unit for modifying pixels in response to graphics instructions;
- a plurality of register files and multiplexers interconnecting said register files with said graphical functional units; and
- an instruction scheduler for issuing instructions in parallel to said graphical functional units; and
- (3) a memory controller, coupled to said printer video processor, for receiving and processing memory transaction requests from said printer video processor.
Parent Case Info
This is a continuation of application Ser. No. 08/267,646 filed Jun. 28, 1994, now U.S. Pat. No. 5,394,515, which was a continuation of application Ser. No. 07/817,813 filed Jan. 8, 1992, abandoned which was a continuation of application Ser. No. 07/726,929 filed Jul. 8, 1991 abandoned.
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Continuations (3)
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Number |
Date |
Country |
Parent |
267646 |
Jun 1994 |
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Parent |
817813 |
Jan 1992 |
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Parent |
726929 |
Jul 1991 |
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