Patent Grant
11869583
Flash memory is seeing increased popularity in storage memory technology, with the availability of solid-state drives (SSDs) and solid state storages with storage arrays and storage clusters. Flash memory is written to in pages, and erased in blocks. Initially offered as a single level cell (SLC, one bit per cell), flash memory is now produced with multilevel cell (MLC, two bits per cell or some versions with more bits per cell), triple level cell (TLC, three bits per cell) and soon quad level cell (QLC, four bits per cell). Higher numbers of bits per cell flash memory (i.e., higher level flash memory) types are predicted. Various vendors and types of flash memory have various page sizes and various page write requirements. All of this variety poses challenges to solid-state drives and solid state storages, which are usually designed for a single vendor and single type of flash memory and which may face redesign or obsolescence if that type of flash memory becomes unavailable or a different vendor or different type of flash memory is to be used. It is within this context that the embodiments arise.
In some embodiments, a method for page writes for triple level cell or higher level cell flash memory is provided. The method includes receiving data in a storage system, from a client that is agnostic of page write requirements for triple level cell, or higher level cell, flash memory, wherein the page write requirements specify an amount of data and a sequence of writing data for a set of pages to assure read data coherency for the set of pages. The method includes accumulating the received data, in random-access memory (RAM) in the storage system to satisfy the page write requirements for the triple level cell, or higher level cell, flash memory in the storage system. The method includes writing at least a portion of the accumulated data in accordance with the page write requirements, from the RAM to the triple level cell, or the higher level cell, flash memory in the storage system as an atomic write. The method may be embodied as executable instructions on a computer readable medium.
In some embodiments, a storage system is provided. The storage system includes a plurality of portions of flash memory, including a portion of triple level cell, or higher level cell, flash memory. The system includes a write sequencer, configurable to write pages to the plurality of portions of flash memory and at least one processor. The at least one processor is configurable to receive data from a client that is isolated from page write requirements for flash memory, wherein the page write requirements specify an amount of data and a sequence of writing data for a set of pages to assure read data coherency for the set of pages. The at least one processor is further configurable to accrue data to satisfy the page write requirements of the triple level cell, or the higher level cell, flash memory and send at least a portion of the accrued data to the write sequencer for writing in accordance with the page write requirements to the portion of triple level cell, or the higher level cell, flash memory as an atomic write.
Other aspects and advantages of the embodiments will become apparent from the following detailed description taken in conjunction with the accompanying drawings which illustrate, by way of example, the principles of the described embodiments.
The present disclosure is illustrated by way of example, and not by way of limitation, and can be more fully understood with reference to the following detailed description when considered in connection with the figures as described below.
A storage cluster described herein performs atomic writes to various types of flash memory in accordance with various write requirements and page sizes of flash memories. Single level cell, multilevel cell, triple level cell and higher level cell flash memories are supported in various embodiments. Although disclosed with examples of solid-state storage clusters, the mechanisms and method herein are usable in other types of storage systems such as storage arrays and solid-state drives. Storage systems with solid-state memory are described with reference to
System 100 includes a number of computing devices 164. Computing devices (also referred to as “client devices” herein) may be for example, a server in a data center, a workstation, a personal computer, a notebook, or the like. Computing devices 164 are coupled for data communications to one or more storage arrays 102 through a storage area network (SAN) 158 or a local area network (LAN) 160.
The SAN 158 may be implemented with a variety of data communications fabrics, devices, and protocols. For example, the fabrics for SAN 158 may include Fibre Channel, Ethernet, Infiniband, Serial Attached Small Computer System Interface (SAS), or the like. Data communications protocols for use with SAN 158 may include Advanced Technology Attachment (ATA), Fibre Channel Protocol, Small Computer System Interface (SCSI), Internet Small Computer System Interface (iSCSI), HyperSCSI, Non-Volatile Memory Express (NVMe) over Fabrics, or the like. It may be noted that SAN 158 is provided for illustration, rather than limitation. Other data communication couplings may be implemented between computing devices 164 and storage arrays 102.
The LAN 160 may also be implemented with a variety of fabrics, devices, and protocols. For example, the fabrics for LAN 160 may include Ethernet (802.3), wireless (802.11), or the like. Data communication protocols for use in LAN 160 may include Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Internet Protocol (IP), HyperText Transfer Protocol (HTTP), Wireless Access Protocol (WAP), Handheld Device Transport Protocol (HDTP), Session Initiation Protocol (SIP), Real Time Protocol (RTP), or the like.
Storage arrays 102 may provide persistent data storage for the computing devices 164. Storage array 102A may be contained in a chassis (not shown), and storage array 102B may be contained in another chassis (not shown), in implementations. Storage array 102A and 102B may include one or more storage array controllers 110 (also referred to as “controller” herein). A storage array controller 110 may be embodied as a module of automated computing machinery comprising computer hardware, computer software, or a combination of computer hardware and software. In some implementations, the storage array controllers 110 may be configured to carry out various storage tasks. Storage tasks may include writing data received from the computing devices 164 to storage array 102, erasing data from storage array 102, retrieving data from storage array 102 and providing data to computing devices 164, monitoring and reporting of disk utilization and performance, performing redundancy operations, such as Redundant Array of Independent Drives (RAID) or RAID-like data redundancy operations, compressing data, encrypting data, and so forth.
Storage array controller 110 may be implemented in a variety of ways, including as a Field Programmable Gate Array (FPGA), a Programmable Logic Chip (PLC), an Application Specific Integrated Circuit (ASIC), System-on-Chip (SOC), or any computing device that includes discrete components such as a processing device, central processing unit, computer memory, or various adapters. Storage array controller 110 may include, for example, a data communications adapter configured to support communications via the SAN 158 or LAN 160. In some implementations, storage array controller 110 may be independently coupled to the LAN 160. In implementations, storage array controller 110 may include an I/O controller or the like that couples the storage array controller 110 for data communications, through a midplane (not shown), to a persistent storage resource 170 (also referred to as a “storage resource” herein). The persistent storage resource 170 main include any number of storage drives 171 (also referred to as “storage devices” herein) and any number of non-volatile Random Access Memory (NVRAM) devices (not shown).
In some implementations, the NVRAM devices of a persistent storage resource 170 may be configured to receive, from the storage array controller 110, data to be stored in the storage drives 171. In some examples, the data may originate from computing devices 164. In some examples, writing data to the NVRAM device may be carried out more quickly than directly writing data to the storage drive 171. In implementations, the storage array controller 110 may be configured to utilize the NVRAM devices as a quickly accessible buffer for data destined to be written to the storage drives 171. Latency for write requests using NVRAM devices as a buffer may be improved relative to a system in which a storage array controller 110 writes data directly to the storage drives 171. In some implementations, the NVRAM devices may be implemented with computer memory in the form of high bandwidth, low latency RAM. The NVRAM device is referred to as “non-volatile” because the NVRAM device may receive or include a unique power source that maintains the state of the RAM after main power loss to the NVRAM device. Such a power source may be a battery, one or more capacitors, or the like. In response to a power loss, the NVRAM device may be configured to write the contents of the RAM to a persistent storage, such as the storage drives 171.
In implementations, storage drive 171 may refer to any device configured to record data persistently, where “persistently” or “persistent” refers as to a device's ability to maintain recorded data after loss of power. In some implementations, storage drive 171 may correspond to non-disk storage media. For example, the storage drive 171 may be one or more solid-state drives (SSDs), flash memory based storage, any type of solid-state non-volatile memory, or any other type of non-mechanical storage device. In other implementations, storage drive 171 may include may include mechanical or spinning hard disk, such as hard-disk drives (HDD).
In some implementations, the storage array controllers 110 may be configured for offloading device management responsibilities from storage drive 171 in storage array 102. For example, storage array controllers 110 may manage control information that may describe the state of one or more memory blocks in the storage drives 171. The control information may indicate, for example, that a particular memory block has failed and should no longer be written to, that a particular memory block contains boot code for a storage array controller 110, the number of program-erase (P/E) cycles that have been performed on a particular memory block, the age of data stored in a particular memory block, the type of data that is stored in a particular memory block, and so forth. In some implementations, the control information may be stored with an associated memory block as metadata. In other implementations, the control information for the storage drives 171 may be stored in one or more particular memory blocks of the storage drives 171 that are selected by the storage array controller 110. The selected memory blocks may be tagged with an identifier indicating that the selected memory block contains control information. The identifier may be utilized by the storage array controllers 110 in conjunction with storage drives 171 to quickly identify the memory blocks that contain control information. For example, the storage controllers 110 may issue a command to locate memory blocks that contain control information. It may be noted that control information may be so large that parts of the control information may be stored in multiple locations, that the control information may be stored in multiple locations for purposes of redundancy, for example, or that the control information may otherwise be distributed across multiple memory blocks in the storage drive 171.
In implementations, storage array controllers 110 may offload device management responsibilities from storage drives 171 of storage array 102 by retrieving, from the storage drives 171, control information describing the state of one or more memory blocks in the storage drives 171. Retrieving the control information from the storage drives 171 may be carried out, for example, by the storage array controller 110 querying the storage drives 171 for the location of control information for a particular storage drive 171. The storage drives 171 may be configured to execute instructions that enable the storage drive 171 to identify the location of the control information. The instructions may be executed by a controller (not shown) associated with or otherwise located on the storage drive 171 and may cause the storage drive 171 to scan a portion of each memory block to identify the memory blocks that store control information for the storage drives 171. The storage drives 171 may respond by sending a response message to the storage array controller 110 that includes the location of control information for the storage drive 171. Responsive to receiving the response message, storage array controllers 110 may issue a request to read data stored at the address associated with the location of control information for the storage drives 171.
In other implementations, the storage array controllers 110 may further offload device management responsibilities from storage drives 171 by performing, in response to receiving the control information, a storage drive management operation. A storage drive management operation may include, for example, an operation that is typically performed by the storage drive 171 (e.g., the controller (not shown) associated with a particular storage drive 171). A storage drive management operation may include, for example, ensuring that data is not written to failed memory blocks within the storage drive 171, ensuring that data is written to memory blocks within the storage drive 171 in such a way that adequate wear leveling is achieved, and so forth.
In implementations, storage array 102 may implement two or more storage array controllers 110. For example, storage array 102A may include storage array controllers 110A and storage array controllers 110B. At a given instance, a single storage array controller 110 (e.g., storage array controller 110A) of a storage system 100 may be designated with primary status (also referred to as “primary controller” herein), and other storage array controllers 110 (e.g., storage array controller 110A) may be designated with secondary status (also referred to as “secondary controller” herein). The primary controller may have particular rights, such as permission to alter data in persistent storage resource 170 (e.g., writing data to persistent storage resource 170). At least some of the rights of the primary controller may supersede the rights of the secondary controller. For instance, the secondary controller may not have permission to alter data in persistent storage resource 170 when the primary controller has the right. The status of storage array controllers 110 may change. For example, storage array controller 110A may be designated with secondary status, and storage array controller 110B may be designated with primary status.
In some implementations, a primary controller, such as storage array controller 110A, may serve as the primary controller for one or more storage arrays 102, and a second controller, such as storage array controller 110B, may serve as the secondary controller for the one or more storage arrays 102. For example, storage array controller 110A may be the primary controller for storage array 102A and storage array 102B, and storage array controller 110B may be the secondary controller for storage array 102A and 102B. In some implementations, storage array controllers 110C and 110D (also referred to as “storage processing modules”) may neither have primary or secondary status. Storage array controllers 110C and 110D, implemented as storage processing modules, may act as a communication interface between the primary and secondary controllers (e.g., storage array controllers 110A and 110B, respectively) and storage array 102B. For example, storage array controller 110A of storage array 102A may send a write request, via SAN 158, to storage array 102B. The write request may be received by both storage array controllers 110C and 110D of storage array 102B. Storage array controllers 110C and 110D facilitate the communication, e.g., send the write request to the appropriate storage drive 171. It may be noted that in some implementations storage processing modules may be used to increase the number of storage drives controlled by the primary and secondary controllers.
In implementations, storage array controllers 110 are communicatively coupled, via a midplane (not shown), to one or more storage drives 171 and to one or more NVRAM devices (not shown) that are included as part of a storage array 102. The storage array controllers 110 may be coupled to the midplane via one or more data communication links and the midplane may be coupled to the storage drives 171 and the NVRAM devices via one or more data communications links. The data communications links described herein are collectively illustrated by data communications links 108 and may include a Peripheral Component Interconnect Express (PCIe) bus, for example.
Storage array controller 101 may include one or more processing devices 104 and random access memory (RAM) 111. Processing device 104 (or controller 101) represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like. More particularly, the processing device 104 (or controller 101) may be a complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets or processors implementing a combination of instruction sets. The processing device 104 (or controller 101) may also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like.
The processing device 104 may be connected to the RAM 111 via a data communications link 106, which may be embodied as a high speed memory bus such as a Double-Data Rate 4 (DDR4) bus. Stored in RAM 111 is an operating system 112. In some implementations, instructions 113 are stored in RAM 111. Instructions 113 may include computer program instructions for performing operations in in a direct-mapped flash storage system. In one embodiment, a direct-mapped flash storage system is one that that addresses data blocks within flash drives directly and without an address translation performed by the storage controllers of the flash drives.
In implementations, storage array controller 101 includes one or more host bus adapters 103 that are coupled to the processing device 104 via a data communications link 105. In implementations, host bus adapters 103 may be computer hardware that connects a host system (e.g., the storage array controller) to other network and storage arrays. In some examples, host bus adapters 103 may be a Fibre Channel adapter that enables the storage array controller 101 to connect to a SAN, an Ethernet adapter that enables the storage array controller 101 to connect to a LAN, or the like. Host bus adapters 103 may be coupled to the processing device 104 via a data communications link 105 such as, for example, a PCIe bus.
In implementations, storage array controller 101 may include a host bus adapter 114 that is coupled to an expander 115. The expander 115 may be used to attach a host system to a larger number of storage drives. The expander 115 may, for example, be a SAS expander utilized to enable the host bus adapter 114 to attach to storage drives in an implementation where the host bus adapter 114 is embodied as a SAS controller.
In implementations, storage array controller 101 may include a switch 116 coupled to the processing device 104 via a data communications link 109. The switch 116 may be a computer hardware device that can create multiple endpoints out of a single endpoint, thereby enabling multiple devices to share a single endpoint. The switch 116 may, for example, be a PCIe switch that is coupled to a PCIe bus (e.g., data communications link 109) and presents multiple PCIe connection points to the midplane.
In implementations, storage array controller 101 includes a data communications link 107 for coupling the storage array controller 101 to other storage array controllers. In some examples, data communications link 107 may be a QuickPath Interconnect (QPI) interconnect.
A traditional storage system that uses traditional flash drives may implement a process across the flash drives that are part of the traditional storage system. For example, a higher level process of the storage system may initiate and control a process across the flash drives. However, a flash drive of the traditional storage system may include its own storage controller that also performs the process. Thus, for the traditional storage system, a higher level process (e.g., initiated by the storage system) and a lower level process (e.g., initiated by a storage controller of the storage system) may both be performed.
To resolve various deficiencies of a traditional storage system, operations may be performed by higher level processes and not by the lower level processes. For example, the flash storage system may include flash drives that do not include storage controllers that provide the process. Thus, the operating system of the flash storage system itself may initiate and control the process. This may be accomplished by a direct-mapped flash storage system that addresses data blocks within the flash drives directly and without an address translation performed by the storage controllers of the flash drives.
The operating system of the flash storage system may identify and maintain a list of allocation units across multiple flash drives of the flash storage system. The allocation units may be entire erase blocks or multiple erase blocks. The operating system may maintain a map or address range that directly maps addresses to erase blocks of the flash drives of the flash storage system.
Direct mapping to the erase blocks of the flash drives may be used to rewrite data and erase data. For example, the operations may be performed on one or more allocation units that include a first data and a second data where the first data is to be retained and the second data is no longer being used by the flash storage system. The operating system may initiate the process to write the first data to new locations within other allocation units and erasing the second data and marking the allocation units as being available for use for subsequent data. Thus, the process may only be performed by the higher level operating system of the flash storage system without an additional lower level process being performed by controllers of the flash drives.
Advantages of the process being performed only by the operating system of the flash storage system include increased reliability of the flash drives of the flash storage system as unnecessary or redundant write operations are not being performed during the process. One possible point of novelty here is the concept of initiating and controlling the process at the operating system of the flash storage system. In addition, the process can be controlled by the operating system across multiple flash drives. This is contrast to the process being performed by a storage controller of a flash drive.
A storage system can consist of two storage array controllers that share a set of drives for failover purposes, or it could consist of a single storage array controller that provides a storage service that utilizes multiple drives, or it could consist of a distributed network of storage array controllers each with some number of drives or some amount of Flash storage where the storage array controllers in the network collaborate to provide a complete storage service and collaborate on various aspects of a storage service including storage allocation and garbage collection.
In one embodiment, system 117 includes a dual Peripheral Component Interconnect (PCI) flash storage device 118 with separately addressable fast write storage. System 117 may include a storage controller 119. In one embodiment, storage controller 119 may be a CPU, ASIC, FPGA, or any other circuitry that may implement control structures necessary according to the present disclosure. In one embodiment, system 117 includes flash memory devices (e.g., including flash memory devices 120a-n), operatively coupled to various channels of the storage device controller 119. Flash memory devices 120a-n, may be presented to the controller 119 as an addressable collection of Flash pages, erase blocks, and/or control elements sufficient to allow the storage device controller 119 to program and retrieve various aspects of the Flash. In one embodiment, storage device controller 119 may perform operations on flash memory devices 120A-N including storing and retrieving data content of pages, arranging and erasing any blocks, tracking statistics related to the use and reuse of Flash memory pages, erase blocks, and cells, tracking and predicting error codes and faults within the Flash memory, controlling voltage levels associated with programming and retrieving contents of Flash cells, etc.
In one embodiment, system 117 may include random access memory (RAM) 121 to store separately addressable fast-write data. In one embodiment, RAM 121 may be one or more separate discrete devices. In another embodiment, RAM 121 may be integrated into storage device controller 119 or multiple storage device controllers. The RAM 121 may be utilized for other purposes as well, such as temporary program memory for a processing device (E.g., a central processing unit (CPU)) in the storage device controller 119.
In one embodiment, system 119 may include a stored energy device 122, such as a rechargeable battery or a capacitor. Stored energy device 122 may store energy sufficient to power the storage device controller 119, some amount of the RAM (e.g., RAM 121), and some amount of Flash memory (e.g., Flash memory 120a-120n) for sufficient time to write the contents of RAM to Flash memory. In one embodiment, storage device controller 119 may write the contents of RAM to Flash Memory if the storage device controller detects loss of external power.
In one embodiment, system 117 includes two data communications links 123a, 123b. In one embodiment, data communications links 123a, 123b may be PCI interfaces. In another embodiment, data communications links 123a, 123b may be based on other communications standards (e.g., HyperTransport, InfiBand, etc.). Data communications links 123a, 123b may be based on non-volatile memory express (NVMe) or NCMe over fabrics (NVMf) specifications that allow external connection to the storage device controller 119 from other components in the storage system 117. It should be noted that data communications links may be interchangeably referred to herein as PCI buses for convenience.
System 117 may also include an external power source (not shown), which may be provided over one or both data communications links 123a, 123b, or which may be provided separately. An alternative embodiment includes a separate Flash memory (not shown) dedicated for use in storing the content of RAM 121. The storage device controller 119 may present a logical device over a PCI bus which may include an addressable fast-write logical device, or a distinct part of the logical address space of the storage device 118, which may be presented as PCI memory or as persistent storage. In one embodiment, operations to store into the device are directed into the RAM 121. On power failure, the storage device controller 119 may write stored content associated with the addressable fast-write logical storage to Flash memory (e.g., Flash memory 120a-n) for long-term persistent storage.
In one embodiment, the logical device may include some presentation of some or all of the content of the Flash memory devices 120a-n, where that presentation allows a storage system including a storage device 118 (e.g., storage system 117) to directly address Flash memory pages and directly reprogram erase blocks from storage system components that are external to the storage device through the PCI bus. The presentation may also allow one or more of the external components to control and retrieve other aspects of the Flash memory including some or all of: tracking statistics related to use and reuse of Flash memory pages, erase blocks, and cells across all the Flash memory devices; tracking and predicting error codes and faults within and across the Flash memory devices; controlling voltage levels associated with programming and retrieving contents of Flash cells; etc.
In one embodiment, the stored energy device 122 may be sufficient to ensure completion of in-progress operations to the Flash memory devices 107a-120n stored energy device 122 may power storage device controller 119 and associated Flash memory devices (e.g., 120a-n) for those operations, as well as for the storing of fast-write RAM to Flash memory. Stored energy device 122 may be used to store accumulated statistics and other parameters kept and tracked by the Flash memory devices 120a-n and/or the storage device controller 119. Separate capacitors or stored energy devices (such as smaller capacitors near or embedded within the Flash memory devices themselves) may be used for some or all of the operations described herein.
Various schemes may be used to track and optimize the life span of the stored energy component, such as adjusting voltage levels over time, partially discharging the storage energy device 122 to measure corresponding discharge characteristics, etc. If the available energy decreases over time, the effective available capacity of the addressable fast-write storage may be decreased to ensure that it can be written safely based on the currently available stored energy.
In one embodiment, two storage controllers (e.g., 125a and 125b) provide storage services, such as a small computer system interface (SCSI) block storage array, a file server, an object server, a database or data analytics service, etc. The storage controllers 125a, 125b may provide services through some number of network interfaces (e.g., 126a-d) to host computers 127a-n outside of the storage system 124. Storage controllers 125a, 125b may provide integrated services or an application entirely within the storage system 124, forming a converged storage and compute system. The storage controllers 125a, 125b may utilize the fast write memory within or across storage devices 119a-d to journal in progress operations to ensure the operations are not lost on a power failure, storage controller removal, storage controller or storage system shutdown, or some fault of one or more software or hardware components within the storage system 124.
In one embodiment, controllers 125a, 125b operate as PCI masters to one or the other PCI buses 128a, 128b. In another embodiment, 128a and 128b may be based on other communications standards (e.g., HyperTransport, InfiBand, etc.). Other storage system embodiments may operate storage controllers 125a, 125b as multi-masters for both PCI buses 128a, 128b. Alternately, a PCI/NVMe/NVMf switching infrastructure or fabric may connect multiple storage controllers. Some storage system embodiments may allow storage devices to communicate with each other directly rather than communicating only with storage controllers. In one embodiment, a storage device controller 119a may be operable under direction from a storage controller 125a to synthesize and transfer data to be stored into Flash memory devices from data that has been stored in RAM (e.g., RAM 121 of
In one embodiment, under direction from a storage controller 125a, 125b, a storage device controller 119a, 119b may be operable to calculate and transfer data to other storage devices from data stored in RAM (e.g., RAM 121 of
A storage device controller 119 may include mechanisms for implementing high availability primitives for use by other parts of a storage system external to the Dual PCI storage device 118. For example, reservation or exclusion primitives may be provided so that, in a storage system with two storage controllers providing a highly available storage service, one storage controller may prevent the other storage controller from accessing or continuing to access the storage device. This could be used, for example, in cases where one controller detects that the other controller is not functioning properly or where the interconnect between the two storage controllers may itself not be functioning properly.
In one embodiment, a storage system for use with Dual PCI direct mapped storage devices with separately addressable fast write storage includes systems that manage erase blocks or groups of erase blocks as allocation units for storing data on behalf of the storage service, or for storing metadata (e.g., indexes, logs, etc.) associated with the storage service, or for proper management of the storage system itself. Flash pages, which may be a few kilobytes in size, may be written as data arrives or as the storage system is to persist data for long intervals of time (e.g., above a defined threshold of time). To commit data more quickly, or to reduce the number of writes to the Flash memory devices, the storage controllers may first write data into the separately addressable fast write storage on one more storage devices.
In one embodiment, the storage controllers 125a, 125b may initiate the use of erase blocks within and across storage devices (e.g., 118) in accordance with an age and expected remaining lifespan of the storage devices, or based on other statistics. The storage controllers 125a, 125b may initiate garbage collection and data migration data between storage devices in accordance with pages that are no longer needed as well as to manage Flash page and erase block lifespans and to manage overall system performance.
In one embodiment, the storage system 124 may utilize mirroring and/or erasure coding schemes as part of storing data into addressable fast write storage and/or as part of writing data into allocation units associated with erase blocks. Erasure codes may be used across storage devices, as well as within erase blocks or allocation units, or within and across Flash memory devices on a single storage device, to provide redundancy against single or multiple storage device failures or to protect against internal corruptions of Flash memory pages resulting from Flash memory operations or from degradation of Flash memory cells. Mirroring and erasure coding at various levels may be used to recover from multiple types of failures that occur separately or in combination.
The embodiments depicted with reference to
The storage cluster may be contained within a chassis, i.e., an enclosure housing one or more storage nodes. A mechanism to provide power to each storage node, such as a power distribution bus, and a communication mechanism, such as a communication bus that enables communication between the storage nodes are included within the chassis. The storage cluster can run as an independent system in one location according to some embodiments. In one embodiment, a chassis contains at least two instances of both the power distribution and the communication bus which may be enabled or disabled independently. The internal communication bus may be an Ethernet bus, however, other technologies such as Peripheral Component Interconnect (PCI) Express, InfiniBand, and others, are equally suitable. The chassis provides a port for an external communication bus for enabling communication between multiple chassis, directly or through a switch, and with client systems. The external communication may use a technology such as Ethernet, InfiniBand, Fibre Channel, etc. In some embodiments, the external communication bus uses different communication bus technologies for inter-chassis and client communication. If a switch is deployed within or between chassis, the switch may act as a translation between multiple protocols or technologies. When multiple chassis are connected to define a storage cluster, the storage cluster may be accessed by a client using either proprietary interfaces or standard interfaces such as network file system (NFS), common internet file system (CIFS), small computer system interface (SCSI) or hypertext transfer protocol (HTTP). Translation from the client protocol may occur at the switch, chassis external communication bus or within each storage node. In some embodiments, multiple chassis may be coupled or connected to each other through an aggregator switch. A portion and/or all of the coupled or connected chassis may be designated as a storage cluster. As discussed above, each chassis can have multiple blades, each blade has a MAC (media access control) address, but the storage cluster is presented to an external network as having a single cluster IP (Internet Protocol) address and a single MAC address in some embodiments.
Each storage node may be one or more storage servers and each storage server is connected to one or more non-volatile solid state memory units, which may be referred to as storage units or storage devices. One embodiment includes a single storage server in each storage node and between one to eight non-volatile solid state memory units, however this one example is not meant to be limiting. The storage server may include a processor, dynamic random access memory (DRAM) and interfaces for the internal communication bus and power distribution for each of the power buses. Inside the storage node, the interfaces and storage unit share a communication bus, e.g., PCI Express, in some embodiments. The non-volatile solid state memory units may directly access the internal communication bus interface through a storage node communication bus, or request the storage node to access the bus interface. The non-volatile solid state memory unit contains an embedded central processing unit (CPU), solid state storage controller, and a quantity of solid state mass storage, e.g., between 2-32 terabytes (TB) in some embodiments. An embedded volatile storage medium, such as DRAM, and an energy reserve apparatus are included in the non-volatile solid state memory unit. In some embodiments, the energy reserve apparatus is a capacitor, super-capacitor, or battery that enables transferring a subset of DRAM contents to a stable storage medium in the case of power loss. In some embodiments, the non-volatile solid state memory unit is constructed with a storage class memory, such as phase change or magnetoresistive random access memory (MRAM) that substitutes for DRAM and enables a reduced power hold-up apparatus.
One of many features of the storage nodes and non-volatile solid state storage is the ability to proactively rebuild data in a storage cluster. The storage nodes and non-volatile solid state storage can determine when a storage node or non-volatile solid state storage in the storage cluster is unreachable, independent of whether there is an attempt to read data involving that storage node or non-volatile solid state storage. The storage nodes and non-volatile solid state storage then cooperate to recover and rebuild the data in at least partially new locations. This constitutes a proactive rebuild, in that the system rebuilds data without waiting until the data is needed for a read access initiated from a client system employing the storage cluster. These and further details of the storage memory and operation thereof are discussed below.
Each storage node 150 can have multiple components. In the embodiment shown here, the storage node 150 includes a printed circuit board 159 populated by a CPU 156, i.e., processor, a memory 154 coupled to the CPU 156, and a non-volatile solid state storage 152 coupled to the CPU 156, although other mountings and/or components could be used in further embodiments. The memory 154 has instructions which are executed by the CPU 156 and/or data operated on by the CPU 156. As further explained below, the non-volatile solid state storage 152 includes flash or, in further embodiments, other types of solid-state memory.
Referring to
Every piece of data, and every piece of metadata, has redundancy in the system in some embodiments. In addition, every piece of data and every piece of metadata has an owner, which may be referred to as an authority. If that authority is unreachable, for example through failure of a storage node, there is a plan of succession for how to find that data or that metadata. In various embodiments, there are redundant copies of authorities 168. Authorities 168 have a relationship to storage nodes 150 and non-volatile solid state storage 152 in some embodiments. Each authority 168, covering a range of data segment numbers or other identifiers of the data, may be assigned to a specific non-volatile solid state storage 152. In some embodiments the authorities 168 for all of such ranges are distributed over the non-volatile solid state storages 152 of a storage cluster. Each storage node 150 has a network port that provides access to the non-volatile solid state storage(s) 152 of that storage node 150. Data can be stored in a segment, which is associated with a segment number and that segment number is an indirection for a configuration of a RAID (redundant array of independent disks) stripe in some embodiments. The assignment and use of the authorities 168 thus establishes an indirection to data. Indirection may be referred to as the ability to reference data indirectly, in this case via an authority 168, in accordance with some embodiments. A segment identifies a set of non-volatile solid state storage 152 and a local identifier into the set of non-volatile solid state storage 152 that may contain data. In some embodiments, the local identifier is an offset into the device and may be reused sequentially by multiple segments. In other embodiments the local identifier is unique for a specific segment and never reused. The offsets in the non-volatile solid state storage 152 are applied to locating data for writing to or reading from the non-volatile solid state storage 152 (in the form of a RAID stripe). Data is striped across multiple units of non-volatile solid state storage 152, which may include or be different from the non-volatile solid state storage 152 having the authority 168 for a particular data segment.
If there is a change in where a particular segment of data is located, e.g., during a data move or a data reconstruction, the authority 168 for that data segment should be consulted, at that non-volatile solid state storage 152 or storage node 150 having that authority 168. In order to locate a particular piece of data, embodiments calculate a hash value for a data segment or apply an inode number or a data segment number. The output of this operation points to a non-volatile solid state storage 152 having the authority 168 for that particular piece of data. In some embodiments there are two stages to this operation. The first stage maps an entity identifier (ID), e.g., a segment number, inode number, or directory number to an authority identifier. This mapping may include a calculation such as a hash or a bit mask. The second stage is mapping the authority identifier to a particular non-volatile solid state storage 152, which may be done through an explicit mapping. The operation is repeatable, so that when the calculation is performed, the result of the calculation repeatably and reliably points to a particular non-volatile solid state storage 152 having that authority 168. The operation may include the set of reachable storage nodes as input. If the set of reachable non-volatile solid state storage units changes the optimal set changes. In some embodiments, the persisted value is the current assignment (which is always true) and the calculated value is the target assignment the cluster will attempt to reconfigure towards. This calculation may be used to determine the optimal non-volatile solid state storage 152 for an authority in the presence of a set of non-volatile solid state storage 152 that are reachable and constitute the same cluster. The calculation also determines an ordered set of peer non-volatile solid state storage 152 that will also record the authority to non-volatile solid state storage mapping so that the authority may be determined even if the assigned non-volatile solid state storage is unreachable. A duplicate or substitute authority 168 may be consulted if a specific authority 168 is unavailable in some embodiments.
With reference to
In some systems, for example in UNIX-style file systems, data is handled with an index node or inode, which specifies a data structure that represents an object in a file system. The object could be a file or a directory, for example. Metadata may accompany the object, as attributes such as permission data and a creation timestamp, among other attributes. A segment number could be assigned to all or a portion of such an object in a file system. In other systems, data segments are handled with a segment number assigned elsewhere. For purposes of discussion, the unit of distribution is an entity, and an entity can be a file, a directory or a segment. That is, entities are units of data or metadata stored by a storage system. Entities are grouped into sets called authorities. Each authority has an authority owner, which is a storage node that has the exclusive right to update the entities in the authority. In other words, a storage node contains the authority, and that the authority, in turn, contains entities.
A segment is a logical container of data in accordance with some embodiments. A segment is an address space between medium address space and physical flash locations, i.e., the data segment number, are in this address space. Segments may also contain meta-data, which enable data redundancy to be restored (rewritten to different flash locations or devices) without the involvement of higher level software. In one embodiment, an internal format of a segment contains client data and medium mappings to determine the position of that data. Each data segment is protected, e.g., from memory and other failures, by breaking the segment into a number of data and parity shards, where applicable. The data and parity shards are distributed, i.e., striped, across non-volatile solid state storage 152 coupled to the host CPUs 156 (See
A series of address-space transformations takes place across an entire storage system. At the top are the directory entries (file names) which link to an inode. Modes point into medium address space, where data is logically stored. Medium addresses may be mapped through a series of indirect mediums to spread the load of large files, or implement data services like deduplication or snapshots. Medium addresses may be mapped through a series of indirect mediums to spread the load of large files, or implement data services like deduplication or snapshots. Segment addresses are then translated into physical flash locations. Physical flash locations have an address range bounded by the amount of flash in the system in accordance with some embodiments. Medium addresses and segment addresses are logical containers, and in some embodiments use a 128 bit or larger identifier so as to be practically infinite, with a likelihood of reuse calculated as longer than the expected life of the system. Addresses from logical containers are allocated in a hierarchical fashion in some embodiments. Initially, each non-volatile solid state storage unit 152 may be assigned a range of address space. Within this assigned range, the non-volatile solid state storage 152 is able to allocate addresses without synchronization with other non-volatile solid state storage 152.
Data and metadata is stored by a set of underlying storage layouts that are optimized for varying workload patterns and storage devices. These layouts incorporate multiple redundancy schemes, compression formats and index algorithms. Some of these layouts store information about authorities and authority masters, while others store file metadata and file data. The redundancy schemes include error correction codes that tolerate corrupted bits within a single storage device (such as a NAND flash chip), erasure codes that tolerate the failure of multiple storage nodes, and replication schemes that tolerate data center or regional failures. In some embodiments, low density parity check (LDPC) code is used within a single storage unit. Reed-Solomon encoding is used within a storage cluster, and mirroring is used within a storage grid in some embodiments. Metadata may be stored using an ordered log structured index (such as a Log Structured Merge Tree), and large data may not be stored in a log structured layout.
In order to maintain consistency across multiple copies of an entity, the storage nodes agree implicitly on two things through calculations: (1) the authority that contains the entity, and (2) the storage node that contains the authority. The assignment of entities to authorities can be done by pseudo randomly assigning entities to authorities, by splitting entities into ranges based upon an externally produced key, or by placing a single entity into each authority. Examples of pseudorandom schemes are linear hashing and the Replication Under Scalable Hashing (RUSH) family of hashes, including Controlled Replication Under Scalable Hashing (CRUSH). In some embodiments, pseudo-random assignment is utilized only for assigning authorities to nodes because the set of nodes can change. The set of authorities cannot change so any subjective function may be applied in these embodiments. Some placement schemes automatically place authorities on storage nodes, while other placement schemes rely on an explicit mapping of authorities to storage nodes. In some embodiments, a pseudorandom scheme is utilized to map from each authority to a set of candidate authority owners. A pseudorandom data distribution function related to CRUSH may assign authorities to storage nodes and create a list of where the authorities are assigned. Each storage node has a copy of the pseudorandom data distribution function, and can arrive at the same calculation for distributing, and later finding or locating an authority. Each of the pseudorandom schemes requires the reachable set of storage nodes as input in some embodiments in order to conclude the same target nodes. Once an entity has been placed in an authority, the entity may be stored on physical devices so that no expected failure will lead to unexpected data loss. In some embodiments, rebalancing algorithms attempt to store the copies of all entities within an authority in the same layout and on the same set of machines.
Examples of expected failures include device failures, stolen machines, datacenter fires, and regional disasters, such as nuclear or geological events. Different failures lead to different levels of acceptable data loss. In some embodiments, a stolen storage node impacts neither the security nor the reliability of the system, while depending on system configuration, a regional event could lead to no loss of data, a few seconds or minutes of lost updates, or even complete data loss.
In the embodiments, the placement of data for storage redundancy is independent of the placement of authorities for data consistency. In some embodiments, storage nodes that contain authorities do not contain any persistent storage. Instead, the storage nodes are connected to non-volatile solid state storage units that do not contain authorities. The communications interconnect between storage nodes and non-volatile solid state storage units consists of multiple communication technologies and has non-uniform performance and fault tolerance characteristics. In some embodiments, as mentioned above, non-volatile solid state storage units are connected to storage nodes via PCI express, storage nodes are connected together within a single chassis using Ethernet backplane, and chassis are connected together to form a storage cluster. Storage clusters are connected to clients using Ethernet or fiber channel in some embodiments. If multiple storage clusters are configured into a storage grid, the multiple storage clusters are connected using the Internet or other long-distance networking links, such as a “metro scale” link or private link that does not traverse the internet.
Authority owners have the exclusive right to modify entities, to migrate entities from one non-volatile solid state storage unit to another non-volatile solid state storage unit, and to add and remove copies of entities. This allows for maintaining the redundancy of the underlying data. When an authority owner fails, is going to be decommissioned, or is overloaded, the authority is transferred to a new storage node. Transient failures make it non-trivial to ensure that all non-faulty machines agree upon the new authority location. The ambiguity that arises due to transient failures can be achieved automatically by a consensus protocol such as Paxos, hot-warm failover schemes, via manual intervention by a remote system administrator, or by a local hardware administrator (such as by physically removing the failed machine from the cluster, or pressing a button on the failed machine). In some embodiments, a consensus protocol is used, and failover is automatic. If too many failures or replication events occur in too short a time period, the system goes into a self-preservation mode and halts replication and data movement activities until an administrator intervenes in accordance with some embodiments.
As authorities are transferred between storage nodes and authority owners update entities in their authorities, the system transfers messages between the storage nodes and non-volatile solid state storage units. With regard to persistent messages, messages that have different purposes are of different types. Depending on the type of the message, the system maintains different ordering and durability guarantees. As the persistent messages are being processed, the messages are temporarily stored in multiple durable and non-durable storage hardware technologies. In some embodiments, messages are stored in RAM, NVRAM and on NAND flash devices, and a variety of protocols are used in order to make efficient use of each storage medium. Latency-sensitive client requests may be persisted in replicated NVRAM, and then later NAND, while background rebalancing operations are persisted directly to NAND.
Persistent messages are persistently stored prior to being transmitted. This allows the system to continue to serve client requests despite failures and component replacement. Although many hardware components contain unique identifiers that are visible to system administrators, manufacturer, hardware supply chain and ongoing monitoring quality control infrastructure, applications running on top of the infrastructure address virtualize addresses. These virtualized addresses do not change over the lifetime of the storage system, regardless of component failures and replacements. This allows each component of the storage system to be replaced over time without reconfiguration or disruptions of client request processing, i.e., the system supports non-disruptive upgrades.
In some embodiments, the virtualized addresses are stored with sufficient redundancy. A continuous monitoring system correlates hardware and software status and the hardware identifiers. This allows detection and prediction of failures due to faulty components and manufacturing details. The monitoring system also enables the proactive transfer of authorities and entities away from impacted devices before failure occurs by removing the component from the critical path in some embodiments.
Storage clusters 161, in various embodiments as disclosed herein, can be contrasted with storage arrays in general. The storage nodes 150 are part of a collection that creates the storage cluster 161. Each storage node 150 owns a slice of data and computing required to provide the data. Multiple storage nodes 150 cooperate to store and retrieve the data. Storage memory or storage devices, as used in storage arrays in general, are less involved with processing and manipulating the data. Storage memory or storage devices in a storage array receive commands to read, write, or erase data. The storage memory or storage devices in a storage array are not aware of a larger system in which they are embedded, or what the data means. Storage memory or storage devices in storage arrays can include various types of storage memory, such as RAM, solid state drives, hard disk drives, etc. The storage units 152 described herein have multiple interfaces active simultaneously and serving multiple purposes. In some embodiments, some of the functionality of a storage node 150 is shifted into a storage unit 152, transforming the storage unit 152 into a combination of storage unit 152 and storage node 150. Placing computing (relative to storage data) into the storage unit 152 places this computing closer to the data itself. The various system embodiments have a hierarchy of storage node layers with different capabilities. By contrast, in a storage array, a controller owns and knows everything about all of the data that the controller manages in a shelf or storage devices. In a storage cluster 161, as described herein, multiple controllers in multiple storage units 152 and/or storage nodes 150 cooperate in various ways (e.g., for erasure coding, data sharding, metadata communication and redundancy, storage capacity expansion or contraction, data recovery, and so on).
The physical storage is divided into named regions based on application usage in some embodiments. The NVRAM 204 is a contiguous block of reserved memory in the storage unit 152 DRAM 216, and is backed by NAND flash. NVRAM 204 is logically divided into multiple memory regions written for two as spool (e.g., spool region). Space within the NVRAM 204 spools is managed by each authority 168 independently. Each device provides an amount of storage space to each authority 168. That authority 168 further manages lifetimes and allocations within that space. Examples of a spool include distributed transactions or notions. When the primary power to a storage unit 152 fails, onboard super-capacitors provide a short duration of power hold up. During this holdup interval, the contents of the NVRAM 204 are flushed to flash memory 206. On the next power-on, the contents of the NVRAM 204 are recovered from the flash memory 206.
As for the storage unit controller, the responsibility of the logical “controller” is distributed across each of the blades containing authorities 168. This distribution of logical control is shown in
In the compute and storage planes 256, 258 of
Still referring to
Because authorities 168 are stateless, they can migrate between blades 252. Each authority 168 has a unique identifier. NVRAM 204 and flash 206 partitions are associated with authorities' 168 identifiers, not with the blades 252 on which they are running in some. Thus, when an authority 168 migrates, the authority 168 continues to manage the same storage partitions from its new location. When a new blade 252 is installed in an embodiment of the storage cluster 161, the system automatically rebalances load by:
From their new locations, migrated authorities 168 persist the contents of their NVRAM 204 partitions on flash 206, process read and write requests from other authorities 168, and fulfill the client requests that endpoints 272 direct to them. Similarly, if a blade 252 fails or is removed, the system redistributes its authorities 168 among the system's remaining blades 252. The redistributed authorities 168 continue to perform their original functions from their new locations.
The embodiments described herein may utilize various software, communication and/or networking protocols. In addition, the configuration of the hardware and/or software may be adjusted to accommodate various protocols. For example, the embodiments may utilize Active Directory, which is a database based system that provides authentication, directory, policy, and other services in a WINDOWS' environment. In these embodiments, LDAP (Lightweight Directory Access Protocol) is one example application protocol for querying and modifying items in directory service providers such as Active Directory. In some embodiments, a network lock manager (NLM) is utilized as a facility that works in cooperation with the Network File System (NFS) to provide a System V style of advisory file and record locking over a network. The Server Message Block (SMB) protocol, one version of which is also known as Common Internet File System (CIFS), may be integrated with the storage systems discussed herein. SMP operates as an application-layer network protocol typically used for providing shared access to files, printers, and serial ports and miscellaneous communications between nodes on a network. SMB also provides an authenticated inter-process communication mechanism. AMAZON™ S3 (Simple Storage Service) is a web service offered by Amazon Web Services, and the systems described herein may interface with Amazon S3 through web services interfaces (REST (representational state transfer), SOAP (simple object access protocol), and BitTorrent). A RESTful API (application programming interface) breaks down a transaction to create a series of small modules. Each module addresses a particular underlying part of the transaction. The control or permissions provided with these embodiments, especially for object data, may include utilization of an access control list (ACL). The ACL is a list of permissions attached to an object and the ACL specifies which users or system processes are granted access to objects, as well as what operations are allowed on given objects. The systems may utilize Internet Protocol version 6 (IPv6), as well as IPv4, for the communications protocol that provides an identification and location system for computers on networks and routes traffic across the Internet. The routing of packets between networked systems may include Equal-cost multi-path routing (ECMP), which is a routing strategy where next-hop packet forwarding to a single destination can occur over multiple “best paths” which tie for top place in routing metric calculations. Multi-path routing can be used in conjunction with most routing protocols, because it is a per-hop decision limited to a single router. The software may support Multi-tenancy, which is an architecture in which a single instance of a software application serves multiple customers. Each customer may be referred to as a tenant. Tenants may be given the ability to customize some parts of the application, but may not customize the application's code, in some embodiments. The embodiments may maintain audit logs. An audit log is a document that records an event in a computing system. In addition to documenting what resources were accessed, audit log entries typically include destination and source addresses, a timestamp, and user login information for compliance with various regulations. The embodiments may support various key management policies, such as encryption key rotation. In addition, the system may support dynamic root passwords or some variation dynamically changing passwords.
In the example depicted in
The cloud services provider 302 depicted in
In the example depicted in
In the example depicted in
Although not explicitly depicted in
In order to enable the storage system 306 and users of the storage system 306 to make use of the services provided by the cloud services provider 302, a cloud migration process may take place during which data, applications, or other elements from an organization's local systems (or even from another cloud environment) are moved to the cloud services provider 302. In order to successfully migrate data, applications, or other elements to the cloud services provider's 302 environment, middleware such as a cloud migration tool may be utilized to bridge gaps between the cloud services provider's 302 environment and an organization's environment. Such cloud migration tools may also be configured to address potentially high network costs and long transfer times associated with migrating large volumes of data to the cloud services provider 302, as well as addressing security concerns associated with sensitive data to the cloud services provider 302 over data communications networks. In order to further enable the storage system 306 and users of the storage system 306 to make use of the services provided by the cloud services provider 302, a cloud orchestrator may also be used to arrange and coordinate automated tasks in pursuit of creating a consolidated process or workflow. Such a cloud orchestrator may perform tasks such as configuring various components, whether those components are cloud components or on-premises components, as well as managing the interconnections between such components. The cloud orchestrator can simplify the inter-component communication and connections to ensure that links are correctly configured and maintained.
In the example depicted in
The cloud services provider 302 may also be configured to provide access to virtualized computing environments to the storage system 306 and users of the storage system 306. Such virtualized computing environments may be embodied, for example, as a virtual machine or other virtualized computer hardware platforms, virtual storage devices, virtualized computer network resources, and so on. Examples of such virtualized environments can include virtual machines that are created to emulate an actual computer, virtualized desktop environments that separate a logical desktop from a physical machine, virtualized file systems that allow uniform access to different types of concrete file systems, and many others.
For further explanation,
The storage system 306 depicted in
The example storage system 306 depicted in
The example storage system 306 depicted in
The storage system 306 depicted in
The storage system 306 depicted in
The storage system 306 depicted in
The software resources 314 may also include software that is useful in implementing software-defined storage (‘SDS’). In such an example, the software resources 314 may include one or more modules of computer program instructions that, when executed, are useful in policy-based provisioning and management of data storage that is independent of the underlying hardware. Such software resources 314 may be useful in implementing storage virtualization to separate the storage hardware from the software that manages the storage hardware.
The software resources 314 may also include software that is useful in facilitating and optimizing I/O operations that are directed to the storage resources 308 in the storage system 306. For example, the software resources 314 may include software modules that perform carry out various data reduction techniques such as, for example, data compression, data deduplication, and others. The software resources 314 may include software modules that intelligently group together I/O operations to facilitate better usage of the underlying storage resource 308, software modules that perform data migration operations to migrate from within a storage system, as well as software modules that perform other functions. Such software resources 314 may be embodied as one or more software containers or in many other ways.
Readers will appreciate that the various components depicted in
Readers will appreciate that the storage system 306 depicted in
Still referring to
As can be seen in the graphs 804, 806, 808 of
Referring to
It should be appreciated that yet another vendor 902, “vendor 3” (not shown in
Further vendors and further types 904 of triple level cell flash memory or higher level cell flash memory (e.g., quad level cell or higher) may have other page write requirements, with specific pages written in specific groups in specific sequence, with or without repetition of one or more pages, etc. In addition, vendors 902 and flash memory types 904 can have various page sizes. One vendor could have 8K (8 kilobytes) page sizes, another vendor could have 16K page sizes or 12K page sizes. These variations in page write requirements and page size are supported in the embodiments of a storage cluster shown in
With reference to
Referring back to
In various embodiments, the write sequencer 1104 of
Still referring to
It should be appreciated that the methods described herein may be performed with a digital processing system, such as a conventional, general-purpose computer system. Special purpose computers, which are designed or programmed to perform only one function may be used in the alternative.
Display 1311 is in communication with CPU 1301, memory 1303, and mass storage device 1307, through bus 1305. Display 1311 is configured to display any visualization tools or reports associated with the system described herein. Input/output device 1309 is coupled to bus 1305 in order to communicate information in command selections to CPU 1301. It should be appreciated that data to and from external devices may be communicated through the input/output device 1309. CPU 1301 can be defined to execute the functionality described herein to enable the functionality described with reference to
It should be understood that although the terms first, second, etc. may be used herein to describe various steps or calculations, these steps or calculations should not be limited by these terms. These terms are only used to distinguish one step or calculation from another. For example, a first calculation could be termed a second calculation, and, similarly, a second step could be termed a first step, without departing from the scope of this disclosure. As used herein, the term “and/or” and the “/” symbol includes any and all combinations of one or more of the associated listed items.
As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises”, “comprising”, “includes”, and/or “including”, when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Therefore, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting.
It should also be noted that in some alternative implementations, the functions/acts noted may occur out of the order noted in the figures. For example, two figures shown in succession may in fact be executed substantially concurrently or may sometimes be executed in the reverse order, depending upon the functionality/acts involved.
With the above embodiments in mind, it should be understood that the embodiments might employ various computer-implemented operations involving data stored in computer systems. These operations are those requiring physical manipulation of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. Further, the manipulations performed are often referred to in terms, such as producing, identifying, determining, or comparing. Any of the operations described herein that form part of the embodiments are useful machine operations. The embodiments also relate to a device or an apparatus for performing these operations. The apparatus can be specially constructed for the required purpose, or the apparatus can be a general-purpose computer selectively activated or configured by a computer program stored in the computer. In particular, various general-purpose machines can be used with computer programs written in accordance with the teachings herein, or it may be more convenient to construct a more specialized apparatus to perform the required operations.
A module, an application, a layer, an agent or other method-operable entity could be implemented as hardware, firmware, or a processor executing software, or combinations thereof. It should be appreciated that, where a software-based embodiment is disclosed herein, the software can be embodied in a physical machine such as a controller. For example, a controller could include a first module and a second module. A controller could be configured to perform various actions, e.g., of a method, an application, a layer or an agent.
The embodiments can also be embodied as computer readable code on a non-transitory computer readable medium. The computer readable medium is any data storage device that can store data, which can be thereafter read by a computer system. Examples of the computer readable medium include hard drives, network attached storage (NAS), read-only memory, random-access memory, CD-ROMs, CD-Rs, CD-RWs, magnetic tapes, and other optical and non-optical data storage devices. The computer readable medium can also be distributed over a network coupled computer system so that the computer readable code is stored and executed in a distributed fashion. Embodiments described herein may be practiced with various computer system configurations including hand-held devices, tablets, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers and the like. The embodiments can also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a wire-based or wireless network.
Although the method operations were described in a specific order, it should be understood that other operations may be performed in between described operations, described operations may be adjusted so that they occur at slightly different times or the described operations may be distributed in a system which allows the occurrence of the processing operations at various intervals associated with the processing.
In various embodiments, one or more portions of the methods and mechanisms described herein may form part of a cloud-computing environment. In such embodiments, resources may be provided over the Internet as services according to one or more various models. Such models may include Infrastructure as a Service (IaaS), Platform as a Service (PaaS), and Software as a Service (SaaS). In IaaS, computer infrastructure is delivered as a service. In such a case, the computing equipment is generally owned and operated by the service provider. In the PaaS model, software tools and underlying equipment used by developers to develop software solutions may be provided as a service and hosted by the service provider. SaaS typically includes a service provider licensing software as a service on demand. The service provider may host the software, or may deploy the software to a customer for a given period of time. Numerous combinations of the above models are possible and are contemplated.
The type of storage systems described above are not limited to file or block systems as the embodiments may be extended to object storage, where data is managed as objects. Each object may include the data itself, a variable amount of metadata, and a globally unique identifier, where object storage can be implemented at multiple levels (e.g., device level, system level, interface level). In addition, the storage systems may be configured for file storage in which data is stored in a hierarchical structure or block based systems. Such data may be saved in files and folders, and presented to both the system storing it and the system retrieving it in the same format. Such data may be accessed using the Network File System (‘NFS’) protocol for Unix or Linux, Server Message Block (‘SMB’) protocol for MICROSOFT WINDOWS™, or in some other manner.
Various units, circuits, or other components may be described or claimed as “configured to” or “configurable to” perform a task or tasks. In such contexts, the phrase “configured to” or “configurable to” is used to connote structure by indicating that the units/circuits/components include structure (e.g., circuitry) that performs the task or tasks during operation. As such, the unit/circuit/component can be said to be configured to perform the task, or configurable to perform the task, even when the specified unit/circuit/component is not currently operational (e.g., is not on). The units/circuits/components used with the “configured to” or “configurable to” language include hardware—for example, circuits, memory storing program instructions executable to implement the operation, etc. Reciting that a unit/circuit/component is “configured to” perform one or more tasks, or is “configurable to” perform one or more tasks, is expressly intended not to invoke 35 U.S.C. 112, sixth paragraph, for that unit/circuit/component. Additionally, “configured to” or “configurable to” can include generic structure (e.g., generic circuitry) that is manipulated by software and/or firmware (e.g., an FPGA or a general-purpose processor executing software) to operate in manner that is capable of performing the task(s) at issue. “Configured to” may also include adapting a manufacturing process (e.g., a semiconductor fabrication facility) to fabricate devices (e.g., integrated circuits) that are adapted to implement or perform one or more tasks. “Configurable to” is expressly intended not to apply to blank media, an unprogrammed processor or unprogrammed generic computer, or an unprogrammed programmable logic device, programmable gate array, or other unprogrammed device, unless accompanied by programmed media that confers the ability to the unprogrammed device to be configured to perform the disclosed function(s).
The foregoing description, for the purpose of explanation, has been described with reference to specific embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The embodiments were chosen and described in order to best explain the principles of the embodiments and its practical applications, to thereby enable others skilled in the art to best utilize the embodiments and various modifications as may be suited to the particular use contemplated. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.
| Number | Name | Date | Kind |
|---|---|---|---|
| 5390327 | Lubbers et al. | Feb 1995 | A |
| 5450581 | Bergen et al. | Sep 1995 | A |
| 5479653 | Jones | Dec 1995 | A |
| 5488731 | Mendelsohn | Jan 1996 | A |
| 5504858 | Ellis et al. | Apr 1996 | A |
| 5564113 | Bergen et al. | Oct 1996 | A |
| 5574882 | Menon et al. | Nov 1996 | A |
| 5649093 | Hanko et al. | Jul 1997 | A |
| 5883909 | Dekoning et al. | Mar 1999 | A |
| 6000010 | Legg | Dec 1999 | A |
| 6260156 | Garvin et al. | Jul 2001 | B1 |
| 6269453 | Krantz | Jul 2001 | B1 |
| 6275898 | DeKoning | Aug 2001 | B1 |
| 6453428 | Stephenson | Sep 2002 | B1 |
| 6523087 | Busser | Feb 2003 | B2 |
| 6535417 | Tsuda | Mar 2003 | B2 |
| 6643748 | Wieland | Nov 2003 | B1 |
| 6725392 | Frey et al. | Apr 2004 | B1 |
| 6763455 | Hall | Jul 2004 | B2 |
| 6836816 | Kendall | Dec 2004 | B2 |
| 6985995 | Holland et al. | Jan 2006 | B2 |
| 7032125 | Holt et al. | Apr 2006 | B2 |
| 7047358 | Lee et al. | May 2006 | B2 |
| 7051155 | Talagala et al. | May 2006 | B2 |
| 7055058 | Lee et al. | May 2006 | B2 |
| 7065617 | Wang | Jun 2006 | B2 |
| 7069383 | Yamamoto et al. | Jun 2006 | B2 |
| 7076606 | Orsley | Jul 2006 | B2 |
| 7107480 | Moshayedi et al. | Sep 2006 | B1 |
| 7159150 | Kenchammana-Hosekote et al. | Jan 2007 | B2 |
| 7162575 | Dalal et al. | Jan 2007 | B2 |
| 7164608 | Lee | Jan 2007 | B2 |
| 7188270 | Nanda et al. | Mar 2007 | B1 |
| 7334156 | Land et al. | Feb 2008 | B2 |
| 7370220 | Nguyen et al. | May 2008 | B1 |
| 7386666 | Beauchamp et al. | Jun 2008 | B1 |
| 7398285 | Kisley | Jul 2008 | B2 |
| 7424498 | Patterson | Sep 2008 | B1 |
| 7424592 | Karr | Sep 2008 | B1 |
| 7444532 | Masuyama et al. | Oct 2008 | B2 |
| 7480658 | Heinla et al. | Jan 2009 | B2 |
| 7484056 | Madnani et al. | Jan 2009 | B2 |
| 7484057 | Madnani et al. | Jan 2009 | B1 |
| 7484059 | Ofer et al. | Jan 2009 | B1 |
| 7536506 | Ashmore et al. | May 2009 | B2 |
| 7558859 | Kasiolas | Jul 2009 | B2 |
| 7565446 | Talagala et al. | Jul 2009 | B2 |
| 7613947 | Coatney | Nov 2009 | B1 |
| 7634617 | Misra | Dec 2009 | B2 |
| 7634618 | Misra | Dec 2009 | B2 |
| 7681104 | Sim-Tang et al. | Mar 2010 | B1 |
| 7681105 | Sim-Tang et al. | Mar 2010 | B1 |
| 7681109 | Yang et al. | Mar 2010 | B2 |
| 7730257 | Franklin | Jun 2010 | B2 |
| 7730258 | Smith | Jun 2010 | B1 |
| 7730274 | Usgaonkar | Jun 2010 | B1 |
| 7743276 | Jacobsen et al. | Jun 2010 | B2 |
| 7752489 | Deenadhayalan et al. | Jul 2010 | B2 |
| 7757038 | Kitahara | Jul 2010 | B2 |
| 7757059 | Ofer et al. | Jul 2010 | B1 |
| 7778960 | Chatterjee et al. | Aug 2010 | B1 |
| 7783955 | Haratsch et al. | Aug 2010 | B2 |
| 7814272 | Barrall et al. | Oct 2010 | B2 |
| 7814273 | Barrall | Oct 2010 | B2 |
| 7818531 | Barrall | Oct 2010 | B2 |
| 7827351 | Suetsugu et al. | Nov 2010 | B2 |
| 7827439 | Matthew et al. | Nov 2010 | B2 |
| 7831768 | Ananthamurthy et al. | Nov 2010 | B2 |
| 7856583 | Smith | Dec 2010 | B1 |
| 7870105 | Arakawa et al. | Jan 2011 | B2 |
| 7873878 | Belluomini et al. | Jan 2011 | B2 |
| 7885938 | Greene et al. | Feb 2011 | B1 |
| 7886111 | Klemm et al. | Feb 2011 | B2 |
| 7908448 | Chatterjee et al. | Mar 2011 | B1 |
| 7916538 | Jeon et al. | Mar 2011 | B2 |
| 7921268 | Jakob | Apr 2011 | B2 |
| 7930499 | Duchesne | Apr 2011 | B2 |
| 7941697 | Mathew et al. | May 2011 | B2 |
| 7958303 | Shuster | Jun 2011 | B2 |
| 7971129 | Watson | Jun 2011 | B2 |
| 7984016 | Kisley | Jul 2011 | B2 |
| 7991822 | Bish et al. | Aug 2011 | B2 |
| 8006126 | Deenadhayalan et al. | Aug 2011 | B2 |
| 8010485 | Chatterjee et al. | Aug 2011 | B1 |
| 8010829 | Chatterjee et al. | Aug 2011 | B1 |
| 8020047 | Courtney | Sep 2011 | B2 |
| 8046548 | Chatterjee et al. | Oct 2011 | B1 |
| 8051361 | Sim-Tang et al. | Nov 2011 | B2 |
| 8051362 | Li et al. | Nov 2011 | B2 |
| 8074038 | Lionetti et al. | Dec 2011 | B2 |
| 8082393 | Galloway et al. | Dec 2011 | B2 |
| 8086603 | Nasre et al. | Dec 2011 | B2 |
| 8086634 | Mimatsu | Dec 2011 | B2 |
| 8086911 | Taylor | Dec 2011 | B1 |
| 8090837 | Shin et al. | Jan 2012 | B2 |
| 8108502 | Tabbara et al. | Jan 2012 | B2 |
| 8117388 | Jernigan, IV | Feb 2012 | B2 |
| 8117521 | Yang et al. | Feb 2012 | B2 |
| 8140821 | Raizen et al. | Mar 2012 | B1 |
| 8145838 | Miller et al. | Mar 2012 | B1 |
| 8145840 | Koul et al. | Mar 2012 | B2 |
| 8175012 | Haratsch et al. | May 2012 | B2 |
| 8176360 | Frost et al. | May 2012 | B2 |
| 8176405 | Hafner et al. | May 2012 | B2 |
| 8180855 | Aiello et al. | May 2012 | B2 |
| 8200922 | McKean et al. | Jun 2012 | B2 |
| 8209469 | Carpenter et al. | Jun 2012 | B2 |
| 8225006 | Karamcheti | Jul 2012 | B1 |
| 8239618 | Kotzur et al. | Aug 2012 | B2 |
| 8244999 | Chatterjee et al. | Aug 2012 | B1 |
| 8261016 | Goel | Sep 2012 | B1 |
| 8271455 | Kesselman | Sep 2012 | B2 |
| 8285686 | Kesselman | Oct 2012 | B2 |
| 8305811 | Jeon | Nov 2012 | B2 |
| 8315999 | Chatley et al. | Nov 2012 | B2 |
| 8327080 | Der | Dec 2012 | B1 |
| 8335769 | Kesselman | Dec 2012 | B2 |
| 8341118 | Drobychev et al. | Dec 2012 | B2 |
| 8351290 | Huang et al. | Jan 2013 | B1 |
| 8364920 | Parkison et al. | Jan 2013 | B1 |
| 8365041 | Chu et al. | Jan 2013 | B2 |
| 8375146 | Sinclair | Feb 2013 | B2 |
| 8397016 | Talagala et al. | Mar 2013 | B2 |
| 8402152 | Duran | Mar 2013 | B2 |
| 8412880 | Leibowitz et al. | Apr 2013 | B2 |
| 8423739 | Ash et al. | Apr 2013 | B2 |
| 8429436 | Filingim et al. | Apr 2013 | B2 |
| 8452928 | Ofer et al. | May 2013 | B1 |
| 8473698 | Lionetti et al. | Jun 2013 | B2 |
| 8473778 | Simitci | Jun 2013 | B2 |
| 8473815 | Yu et al. | Jun 2013 | B2 |
| 8479037 | Chatterjee et al. | Jul 2013 | B1 |
| 8484414 | Sugimoto et al. | Jul 2013 | B2 |
| 8498967 | Chatterjee et al. | Jul 2013 | B1 |
| 8522073 | Cohen | Aug 2013 | B2 |
| 8533408 | Madnani et al. | Sep 2013 | B1 |
| 8533527 | Daikokuya et al. | Sep 2013 | B2 |
| 8539177 | Ofer et al. | Sep 2013 | B1 |
| 8544029 | Bakke et al. | Sep 2013 | B2 |
| 8549224 | Zeryck et al. | Oct 2013 | B1 |
| 8583861 | Ofer et al. | Nov 2013 | B1 |
| 8589625 | Colgrove et al. | Nov 2013 | B2 |
| 8595455 | Chatterjee et al. | Nov 2013 | B2 |
| 8615599 | Takefman et al. | Dec 2013 | B1 |
| 8627136 | Shankar et al. | Jan 2014 | B2 |
| 8627138 | Clark | Jan 2014 | B1 |
| 8639669 | Douglis et al. | Jan 2014 | B1 |
| 8639863 | Kanapathippillai et al. | Jan 2014 | B1 |
| 8640000 | Cypher | Jan 2014 | B1 |
| 8650343 | Kanapathippillai et al. | Feb 2014 | B1 |
| 8660131 | Vermunt et al. | Feb 2014 | B2 |
| 8661218 | Piszczek et al. | Feb 2014 | B1 |
| 8671072 | Shah et al. | Mar 2014 | B1 |
| 8689042 | Kanapathippillai et al. | Apr 2014 | B1 |
| 8700875 | Barron et al. | Apr 2014 | B1 |
| 8706694 | Chatterjee et al. | Apr 2014 | B2 |
| 8706914 | Duchesneau | Apr 2014 | B2 |
| 8706932 | Kanapathippillai et al. | Apr 2014 | B1 |
| 8712963 | Douglis et al. | Apr 2014 | B1 |
| 8713405 | Healey et al. | Apr 2014 | B2 |
| 8719621 | Karmarkar | May 2014 | B1 |
| 8725730 | Keeton et al. | May 2014 | B2 |
| 8751859 | Becker-szendy et al. | Jun 2014 | B2 |
| 8756387 | Frost et al. | Jun 2014 | B2 |
| 8762793 | Grube et al. | Jun 2014 | B2 |
| 8838541 | Camble et al. | Jun 2014 | B2 |
| 8769232 | Suryabudi et al. | Jul 2014 | B2 |
| 8775858 | Gower et al. | Jul 2014 | B2 |
| 8775868 | Colgrove et al. | Jul 2014 | B2 |
| 8788913 | Xin et al. | Jul 2014 | B1 |
| 8793447 | Usgaonkar et al. | Jul 2014 | B2 |
| 8799746 | Baker et al. | Aug 2014 | B2 |
| 8819311 | Liao | Aug 2014 | B2 |
| 8819383 | Jobanputra et al. | Aug 2014 | B1 |
| 8824261 | Miller et al. | Sep 2014 | B1 |
| 8832528 | Thatcher et al. | Sep 2014 | B2 |
| 8838892 | Li | Sep 2014 | B2 |
| 8843700 | Salessi et al. | Sep 2014 | B1 |
| 8850108 | Hayes et al. | Sep 2014 | B1 |
| 8850288 | Lazier et al. | Sep 2014 | B1 |
| 8856593 | Eckhardt et al. | Oct 2014 | B2 |
| 8856619 | Cypher | Oct 2014 | B1 |
| 8862617 | Kesselman | Oct 2014 | B2 |
| 8862847 | Feng et al. | Oct 2014 | B2 |
| 8862928 | Xavier et al. | Oct 2014 | B2 |
| 8868825 | Hayes | Oct 2014 | B1 |
| 8874836 | Hayes | Oct 2014 | B1 |
| 8880793 | Nagineni | Nov 2014 | B2 |
| 8880825 | Lionetti et al. | Nov 2014 | B2 |
| 8886778 | Nedved et al. | Nov 2014 | B2 |
| 8898383 | Yamamoto et al. | Nov 2014 | B2 |
| 8898388 | Kimmel | Nov 2014 | B1 |
| 8904231 | Coatney et al. | Dec 2014 | B2 |
| 8918478 | Ozzie et al. | Dec 2014 | B2 |
| 8930307 | Colgrove et al. | Jan 2015 | B2 |
| 8930633 | Amit et al. | Jan 2015 | B2 |
| 8943357 | Atzmony | Jan 2015 | B2 |
| 8949502 | McKnight et al. | Feb 2015 | B2 |
| 8959110 | Smith et al. | Feb 2015 | B2 |
| 8959388 | Kuang et al. | Feb 2015 | B1 |
| 8972478 | Storer et al. | Mar 2015 | B1 |
| 8972779 | Lee et al. | Mar 2015 | B2 |
| 8977597 | Ganesh et al. | Mar 2015 | B2 |
| 8996828 | Kalos et al. | Mar 2015 | B2 |
| 9003144 | Hayes et al. | Apr 2015 | B1 |
| 9009724 | Gold et al. | Apr 2015 | B2 |
| 9021053 | Bernbo et al. | Apr 2015 | B2 |
| 9021215 | Meir et al. | Apr 2015 | B2 |
| 9025393 | Wu | May 2015 | B2 |
| 9043372 | Makkar et al. | May 2015 | B2 |
| 9047214 | Sharon et al. | Jun 2015 | B1 |
| 9053808 | Sprouse | Jun 2015 | B2 |
| 9058155 | Cepulis et al. | Jun 2015 | B2 |
| 9063895 | Madnani et al. | Jun 2015 | B1 |
| 9063896 | Madnani et al. | Jun 2015 | B1 |
| 9098211 | Madnani et al. | Aug 2015 | B1 |
| 9110898 | Chamness et al. | Aug 2015 | B1 |
| 9110964 | Shilane et al. | Aug 2015 | B1 |
| 9116819 | Cope et al. | Aug 2015 | B2 |
| 9117536 | Yoon | Aug 2015 | B2 |
| 9122401 | Zaltsman et al. | Sep 2015 | B2 |
| 9123422 | Sharon et al. | Sep 2015 | B2 |
| 9124300 | Olbrich et al. | Sep 2015 | B2 |
| 9134908 | Horn et al. | Sep 2015 | B2 |
| 9153337 | Sutardja | Oct 2015 | B2 |
| 9158472 | Kesselman et al. | Oct 2015 | B2 |
| 9159422 | Lee et al. | Oct 2015 | B1 |
| 9164891 | Karamcheti et al. | Oct 2015 | B2 |
| 9183136 | Kawamura et al. | Nov 2015 | B2 |
| 9189650 | Jaye et al. | Nov 2015 | B2 |
| 9201733 | Verma | Dec 2015 | B2 |
| 9207876 | Shu et al. | Dec 2015 | B2 |
| 9229656 | Contreras et al. | Jan 2016 | B1 |
| 9229810 | He et al. | Jan 2016 | B2 |
| 9235475 | Shilane et al. | Jan 2016 | B1 |
| 9244626 | Shah et al. | Jan 2016 | B2 |
| 9250999 | Barroso | Feb 2016 | B1 |
| 9251066 | Colgrove et al. | Feb 2016 | B2 |
| 9268648 | Barash et al. | Feb 2016 | B1 |
| 9268806 | Kesselman et al. | Feb 2016 | B1 |
| 9286002 | Karamcheti et al. | Mar 2016 | B1 |
| 9292214 | Kalos et al. | Mar 2016 | B2 |
| 9298760 | Li et al. | Mar 2016 | B1 |
| 9304908 | Karamcheti et al. | Apr 2016 | B1 |
| 9311969 | Murin | Apr 2016 | B2 |
| 9311970 | Sharon et al. | Apr 2016 | B2 |
| 9323663 | Karamcheti et al. | Apr 2016 | B2 |
| 9323667 | Bennett | Apr 2016 | B2 |
| 9323681 | Apostolides et al. | Apr 2016 | B2 |
| 9335942 | Kumar et al. | May 2016 | B2 |
| 9348538 | Mallaiah et al. | May 2016 | B2 |
| 9355022 | Ravimohan et al. | May 2016 | B2 |
| 9384082 | Lee et al. | Jul 2016 | B1 |
| 9384252 | Akirav et al. | Jul 2016 | B2 |
| 9389958 | Sundaram et al. | Jul 2016 | B2 |
| 9390019 | Patterson et al. | Jul 2016 | B2 |
| 9396202 | Drobychev et al. | Jul 2016 | B1 |
| 9400828 | Kesselman et al. | Jul 2016 | B2 |
| 9405478 | Koseki et al. | Aug 2016 | B2 |
| 9411685 | Lee | Aug 2016 | B2 |
| 9417960 | Klein | Aug 2016 | B2 |
| 9417963 | He et al. | Aug 2016 | B2 |
| 9430250 | Hamid et al. | Aug 2016 | B2 |
| 9430542 | Akirav et al. | Aug 2016 | B2 |
| 9432541 | Ishida | Aug 2016 | B2 |
| 9454434 | Sundaram et al. | Sep 2016 | B2 |
| 9471579 | Natanzon | Oct 2016 | B1 |
| 9477554 | Chamness et al. | Oct 2016 | B2 |
| 9477632 | Du | Oct 2016 | B2 |
| 9501398 | George et al. | Nov 2016 | B2 |
| 9525737 | Friedman | Dec 2016 | B2 |
| 9529542 | Friedman et al. | Dec 2016 | B2 |
| 9535631 | Fu et al. | Jan 2017 | B2 |
| 9552248 | Miller et al. | Jan 2017 | B2 |
| 9552291 | Munetoh et al. | Jan 2017 | B2 |
| 9552299 | Stalzer | Jan 2017 | B2 |
| 9563517 | Natanzon et al. | Feb 2017 | B1 |
| 9588698 | Karamcheti et al. | Mar 2017 | B1 |
| 9588712 | Kalos et al. | Mar 2017 | B2 |
| 9594652 | Sathiamoorthy et al. | Mar 2017 | B1 |
| 9600193 | Ahrens et al. | Mar 2017 | B2 |
| 9619321 | Sharon et al. | Apr 2017 | B1 |
| 9619430 | Kannan et al. | Apr 2017 | B2 |
| 9645754 | Li et al. | May 2017 | B2 |
| 9667720 | Bent et al. | May 2017 | B1 |
| 9710535 | Aizman et al. | Jul 2017 | B2 |
| 9733840 | Karamcheti et al. | Aug 2017 | B2 |
| 9734225 | Akirav et al. | Aug 2017 | B2 |
| 9740403 | Storer et al. | Aug 2017 | B2 |
| 9740700 | Chopra et al. | Aug 2017 | B1 |
| 9740762 | Horowitz et al. | Aug 2017 | B2 |
| 9747319 | Bestler et al. | Aug 2017 | B2 |
| 9747320 | Kesselman | Aug 2017 | B2 |
| 9767130 | Bestler et al. | Sep 2017 | B2 |
| 9781227 | Friedman et al. | Oct 2017 | B2 |
| 9785498 | Misra et al. | Oct 2017 | B2 |
| 9798486 | Singh | Oct 2017 | B1 |
| 9804925 | Carmi et al. | Oct 2017 | B1 |
| 9811285 | Karamcheti et al. | Nov 2017 | B1 |
| 9811546 | Bent et al. | Nov 2017 | B1 |
| 9818478 | Chung | Nov 2017 | B2 |
| 9829066 | Thomas et al. | Nov 2017 | B2 |
| 9836245 | Hayes et al. | Dec 2017 | B2 |
| 9891854 | Munetoh et al. | Feb 2018 | B2 |
| 9891860 | Delgado et al. | Feb 2018 | B1 |
| 9892005 | Kedem et al. | Feb 2018 | B2 |
| 9892186 | Akirav et al. | Feb 2018 | B2 |
| 9904589 | Donlan et al. | Feb 2018 | B1 |
| 9904717 | Anglin et al. | Feb 2018 | B2 |
| 9952809 | Shah | Feb 2018 | B2 |
| 9910748 | Pan | Mar 2018 | B2 |
| 9910904 | Anglin et al. | Mar 2018 | B2 |
| 9934237 | Shilane et al. | Apr 2018 | B1 |
| 9940065 | Kalos et al. | Apr 2018 | B2 |
| 9946604 | Glass | Apr 2018 | B1 |
| 9959167 | Donlan et al. | May 2018 | B1 |
| 9965539 | D'halluin et al. | May 2018 | B2 |
| 9998539 | Brock et al. | Jun 2018 | B1 |
| 10007457 | Hayes et al. | Jun 2018 | B2 |
| 10013177 | Liu et al. | Jul 2018 | B2 |
| 10013311 | Sundaram et al. | Jul 2018 | B2 |
| 10019314 | Litsyn et al. | Jul 2018 | B2 |
| 10019317 | Usvyatsky et al. | Jul 2018 | B2 |
| 10031703 | Natanzon et al. | Jul 2018 | B1 |
| 10061512 | Chu et al. | Aug 2018 | B2 |
| 10073626 | Karamcheti et al. | Sep 2018 | B2 |
| 10082985 | Hayes et al. | Sep 2018 | B2 |
| 10089012 | Chen et al. | Oct 2018 | B1 |
| 10089174 | Lin | Oct 2018 | B2 |
| 10089176 | Donlan et al. | Oct 2018 | B1 |
| 10108819 | Donlan et al. | Oct 2018 | B1 |
| 10146787 | Bashyam et al. | Dec 2018 | B2 |
| 10152268 | Chakraborty et al. | Dec 2018 | B1 |
| 10157098 | Chung et al. | Dec 2018 | B2 |
| 10162704 | Kirschner et al. | Dec 2018 | B1 |
| 10180875 | Northcott | Jan 2019 | B2 |
| 10185730 | Bestler et al. | Jan 2019 | B2 |
| 10235065 | Miller et al. | Mar 2019 | B1 |
| 20020144059 | Kendall | Oct 2002 | A1 |
| 20030105984 | Masuyama et al. | Jun 2003 | A1 |
| 20030110205 | Johnson | Jun 2003 | A1 |
| 20040161086 | Buntin et al. | Aug 2004 | A1 |
| 20050001652 | Malik et al. | Jan 2005 | A1 |
| 20050076228 | Davis et al. | Apr 2005 | A1 |
| 20050235132 | Karr et al. | Oct 2005 | A1 |
| 20050278460 | Shin et al. | Dec 2005 | A1 |
| 20050283649 | Turner et al. | Dec 2005 | A1 |
| 20060015683 | Ashmore et al. | Jan 2006 | A1 |
| 20060114930 | Lucas et al. | Jun 2006 | A1 |
| 20060174157 | Barrall et al. | Aug 2006 | A1 |
| 20060248294 | Nedved et al. | Nov 2006 | A1 |
| 20070079068 | Draggon | Apr 2007 | A1 |
| 20070214194 | Reuter | Sep 2007 | A1 |
| 20070214314 | Reuter | Sep 2007 | A1 |
| 20070234016 | Davis et al. | Oct 2007 | A1 |
| 20070268905 | Baker et al. | Nov 2007 | A1 |
| 20080080709 | Michtchenko et al. | Apr 2008 | A1 |
| 20080107274 | Worthy | May 2008 | A1 |
| 20080155191 | Anderson et al. | Jun 2008 | A1 |
| 20080295118 | Liao | Nov 2008 | A1 |
| 20090077208 | Nguyen et al. | Mar 2009 | A1 |
| 20090138654 | Sutardja | May 2009 | A1 |
| 20090216910 | Duchesneau | Aug 2009 | A1 |
| 20090216920 | Lauterbach et al. | Aug 2009 | A1 |
| 20100017444 | Chatterjee et al. | Jan 2010 | A1 |
| 20100042636 | Lu | Feb 2010 | A1 |
| 20100094806 | Apostolides et al. | Apr 2010 | A1 |
| 20100115070 | Missimilly | May 2010 | A1 |
| 20100125695 | Wu et al. | May 2010 | A1 |
| 20100162076 | Sim-Tang et al. | Jun 2010 | A1 |
| 20100169707 | Mathew et al. | Jul 2010 | A1 |
| 20100174576 | Naylor | Jul 2010 | A1 |
| 20100268908 | Ouyang et al. | Oct 2010 | A1 |
| 20110040925 | Frost et al. | Feb 2011 | A1 |
| 20110060927 | Fillingim et al. | Mar 2011 | A1 |
| 20110119462 | Leach et al. | May 2011 | A1 |
| 20110219170 | Frost et al. | Sep 2011 | A1 |
| 20110238625 | Hamaguchi et al. | Sep 2011 | A1 |
| 20110264843 | Haines et al. | Oct 2011 | A1 |
| 20110302369 | Goto et al. | Dec 2011 | A1 |
| 20120011398 | Eckhardt | Jan 2012 | A1 |
| 20120079318 | Colgrove et al. | Mar 2012 | A1 |
| 20120089567 | Takahashi et al. | Apr 2012 | A1 |
| 20120110249 | Jeong et al. | May 2012 | A1 |
| 20120131253 | McKnight | May 2012 | A1 |
| 20120158923 | Mohamed et al. | Jun 2012 | A1 |
| 20120191900 | Kunimatsu et al. | Jul 2012 | A1 |
| 20120198152 | Terry et al. | Aug 2012 | A1 |
| 20120198261 | Brown et al. | Aug 2012 | A1 |
| 20120209943 | Jung | Aug 2012 | A1 |
| 20120226934 | Rao | Sep 2012 | A1 |
| 20120246435 | Meir et al. | Sep 2012 | A1 |
| 20120260055 | Murase | Oct 2012 | A1 |
| 20120311557 | Resch | Dec 2012 | A1 |
| 20130022201 | Glew et al. | Jan 2013 | A1 |
| 20130036314 | Glew et al. | Feb 2013 | A1 |
| 20130042056 | Shats | Feb 2013 | A1 |
| 20130060884 | Bernbo et al. | Mar 2013 | A1 |
| 20130067188 | Mehra et al. | Mar 2013 | A1 |
| 20130073894 | Xavier et al. | Mar 2013 | A1 |
| 20130124776 | Hallak et al. | May 2013 | A1 |
| 20130132800 | Healy et al. | May 2013 | A1 |
| 20130151653 | Sawiki | Jun 2013 | A1 |
| 20130151771 | Tsukahara et al. | Jun 2013 | A1 |
| 20130173853 | Ungureanu et al. | Jul 2013 | A1 |
| 20130238554 | Yucel et al. | Sep 2013 | A1 |
| 20130339314 | Carpenter et al. | Dec 2013 | A1 |
| 20130339635 | Amit et al. | Dec 2013 | A1 |
| 20130339818 | Baker et al. | Dec 2013 | A1 |
| 20140040535 | Lee | Feb 2014 | A1 |
| 20140040702 | He et al. | Feb 2014 | A1 |
| 20140047263 | Coatney et al. | Feb 2014 | A1 |
| 20140047269 | Kim | Feb 2014 | A1 |
| 20140059406 | Hyun | Feb 2014 | A1 |
| 20140063721 | Herman et al. | Mar 2014 | A1 |
| 20140064048 | Cohen et al. | Mar 2014 | A1 |
| 20140068224 | Fan et al. | Mar 2014 | A1 |
| 20140075252 | Luo et al. | Mar 2014 | A1 |
| 20140122510 | Namkoong et al. | May 2014 | A1 |
| 20140136880 | Shankar et al. | May 2014 | A1 |
| 20140181402 | White | Jun 2014 | A1 |
| 20140237164 | Le et al. | Aug 2014 | A1 |
| 20140279936 | Bernbo et al. | Sep 2014 | A1 |
| 20140280025 | Eidson et al. | Sep 2014 | A1 |
| 20140289588 | Nagadomi et al. | Sep 2014 | A1 |
| 20140330785 | Isherwood et al. | Nov 2014 | A1 |
| 20140372838 | Lou et al. | Dec 2014 | A1 |
| 20140380125 | Calder et al. | Dec 2014 | A1 |
| 20140380126 | Yekhanin et al. | Dec 2014 | A1 |
| 20150032720 | James | Jan 2015 | A1 |
| 20150039645 | Lewis | Feb 2015 | A1 |
| 20150039849 | Lewis | Feb 2015 | A1 |
| 20150089283 | Kermarrec et al. | Mar 2015 | A1 |
| 20150100746 | Rychlik | Apr 2015 | A1 |
| 20150134824 | Mickens | May 2015 | A1 |
| 20150153800 | Lucas et al. | Jun 2015 | A1 |
| 20150180714 | Chunn | Jun 2015 | A1 |
| 20150186262 | Lin | Jul 2015 | A1 |
| 20150280959 | Vincent | Oct 2015 | A1 |
| 20160246537 | Kim | Feb 2016 | A1 |
| 20160191508 | Bestler et al. | Jun 2016 | A1 |
| 20160378612 | Hipsh et al. | Dec 2016 | A1 |
| 20170091236 | Hayes et al. | Mar 2017 | A1 |
| 20170103092 | Hu et al. | Apr 2017 | A1 |
| 20170103094 | Hu et al. | Apr 2017 | A1 |
| 20170103098 | Hu et al. | Apr 2017 | A1 |
| 20170103116 | Hu et al. | Apr 2017 | A1 |
| 20170177236 | Haratsch et al. | Jun 2017 | A1 |
| 20180039442 | Shadrin et al. | Feb 2018 | A1 |
| 20180081958 | Akirav et al. | Mar 2018 | A1 |
| 20180101441 | Hyun et al. | Apr 2018 | A1 |
| 20180101587 | Anglin et al. | Apr 2018 | A1 |
| 20180101588 | Anglin et al. | Apr 2018 | A1 |
| 20180217756 | Liu et al. | Aug 2018 | A1 |
| 20180307560 | Vishnumolakala et al. | Oct 2018 | A1 |
| 20180321874 | Li et al. | Nov 2018 | A1 |
| 20190036703 | Bestler | Jan 2019 | A1 |
| Number | Date | Country |
|---|---|---|
| 2164006 | Mar 2010 | EP |
| 2256621 | Dec 2010 | EP |
| WO 02-13033 | Feb 2002 | WO |
| WO 2008103569 | Aug 2008 | WO |
| WO 2008157081 | Dec 2008 | WO |
| WO 2013032825 | Jul 2013 | WO |
| Entry |
|---|
| Hwang, Kai, et al. “RAID-x: A New Distributed Disk Array for I/O-Centric Cluster Computing,” HPDC '00 Proceedings of the 9th IEEE International Symposium on High Performance Distributed Computing, IEEE, 2000, pp. 279-286. |
| Schmid, Patrick: “RAID Scaling Charts, Part 3:4-128 kB Stripes Compared”, Tom's Hardware, Nov. 27, 2007 (http://www.tomshardware.com/reviews/RAID-SCALING-CHARTS.1735-4.html), See pp. 1-2. |
| Storer, Mark W. et al., “Pergamum: Replacing Tape with Energy Efficient, Reliable, Disk-Based Archival Storage,” Fast '08: 6th USENIX Conference on File and Storage Technologies, San Jose, CA, Feb. 26-29, 2008 pp. 1-16. |
| Ju-Kyeong Kim et al., “Data Access Frequency based Data Replication Method using Erasure Codes in Cloud Storage System”, Journal of the Institute of Electronics and Information Engineers, Feb. 2014, vol. 51, No. 2, pp. 85-91. |
| International Search Report and the Written Opinion of the International Searching Authority, PCT/US2015/018169, dated May 15, 2015. |
| International Search Report and the Written Opinion of the International Searching Authority, PCT/US2015/034302, dated Sep. 11, 2015. |
| International Search Report and the Written Opinion of the International Searching Authority, PCT/US2015/039135, dated Sep. 18, 2015. |
| International Search Report and the Written Opinion of the International Searching Authority, PCT/US2015/039136, dated Sep. 23, 2015. |
| International Search Report, PCT/US2015/039142, dated Sep. 24, 2015. |
| International Search Report, PCT/US2015/034291, dated Sep. 30, 2015. |
| International Search Report and the Written Opinion of the International Searching Authority, PCT/US2015/039137, dated Oct. 1, 2015. |
| International Search Report, PCT/US2015/044370, dated Dec. 15, 2015. |
| International Search Report amd the Written Opinion of the International Searching Authority, PCT/US2016/031039, dated May 5, 2016. |
| International Search Report, PCT/US2016/014604, dated May 19, 2016. |
| International Search Report, PCT/US2016/014361, dated May 30, 2016. |
| International Search Report, PCT/US2016/014356, dated Jun. 28, 2016. |
| International Search Report, PCT/US2016/014357, dated Jun. 29, 2016. |
| International Seach Report and the Written Opinion of the International Searching Authority, PCT/US2016/016504, dated Jul. 6, 2016. |
| International Seach Report and the Written Opinion of the International Searching Authority, PCT/US2016/024391, dated Jul. 12, 2016. |
| International Seach Report and the Written Opinion of the International Searching Authority, PCT/US2016/026529, dated Jul. 19, 2016. |
| International Seach Report and the Written Opinion of the International Searching Authority, PCT/US2016/023485, dated Jul. 21, 2016. |
| International Seach Report and the Written Opinion of the International Searching Authority, PCT/US2016/033306, dated Aug. 19, 2016. |
| International Seach Report and the Written Opinion of the International Searching Authority, PCT/US2016/047808, dated Nov. 25, 2016. |
| Stalzer, Mark A., “FlashBlades: System Architecture and Applications,” Proceedings of the 2nd Workshop on Architectures and Systems for Big Data, Association for Computing Machinery, New York, NY, 2012, pp. 10-14. |
| International Seach Report and the Written Opinion of the International Searching Authority, PCT/US2016/042147, dated Nov. 30, 2016. |
| Number | Date | Country | |
|---|---|---|---|
| 20220215875 A1 | Jul 2022 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 17085362 | Oct 2020 | US |
| Child | 17704747 | US | |
| Parent | 16200301 | Nov 2018 | US |
| Child | 17085362 | US | |
| Parent | 15498979 | Apr 2017 | US |
| Child | 16200301 | US |
