Patent Application
20160148681
Resistive random-access memory (RRAM or ReRAM) is a non-volatile memory in which a dielectric that is normally insulating, is configured to conduct after application of a sufficiently high voltage. The forming of a conduction path typically requires a relatively high voltage. Once the path is formed in the dielectric, the path may be “reset” (broken, to provide high resistance) or “set” (re-formed, to provide a low resistance) by an appropriately applied voltage.
When RRAM is first manufactured it is in a high resistance state. Each memory cell in an RRAM array is subjected to a forming process once at the beginning of life in order to be put into a lower resistance state. This forming process may be performed in a factory after the memory is manufactured. During the forming process, a relatively high voltage is applied to each of the RRAM memory cells until the memory cells transition from the high resistive state to a low resistive state. Some forming techniques take a long time to complete as every memory cell requires a different time/voltage to be formed. Once a RRAM memory cell is formed the applied forming bias voltage should be switched off immediately.
The forming bias voltage may be applied via bit lines using respective assembly buffers. The number of assembly buffers is limited due to a limited amount of available space. The option of forming parallelism, that is, forming a plurality of cells in parallel, is limited by the number of assembly buffers. This relatively small forming parallelism results in significant forming times, long test times, and high test cost during frontend and backend tests.
The present disclosure is directed to increasing memory cells formed in parallel. This is accomplished by using a multiplexer to apply a forming bias voltage to a plurality of bit lines in parallel, and then disconnecting formed memory cells from the forming bias voltage. If the number of memory cells formed in parallel increases by factor N, then the overall memory array forming time decreases by the factor of 1/N.
The memory 110 has an array of memory cells 112 formed at intersections of word lines WL0-WLn and bit lines BL0-BLm. For the sake of convenience, in the figure only one memory cell 112 is referenced.) A digital data value may be stored as a memory resistance (high or low). The memory state of a memory cell can be read by supplying appropriate voltages to the bit line BLm and word line WLn associated with to the selected memory cell 112. The resistance or memory state can be read as an output voltage or current of the bit line BL0-BLm coupled to the selected memory cell. One resistance state may correspond to a data “0,” for example, while the other resistance state may correspond to a data “1.”
Each of the multiplexers 120 comprises a plurality of outputs coupled to a plurality of bit lines BL. The assembly buffers 130 are not coupled directly to the bit lines BL, but rather each assembly buffer 130 has an output coupled to an input of one of a respective one of the multiplexers 120 to provide a supply voltage. When data is to be written to a memory cell 112, the data represented by a “0” or a “1” is loaded into the assembly buffer 130, and the assembly buffer 130 then applies a voltage level based on the data to the memory cell 112. The assembly buffer 130 may form a portion of a sense amplifier.
The disclosure is not limited to the number of word lines WL, bit lines BL, multiplexers 120 and assembly buffers 130 shown. There may be any number of each of these elements as suitable for the intended purpose.
The process of forming memory cells in accordance with this disclosure comprises three steps: (1) Parallel selection of a plurality of bit lines; (2) Detection of successful formation of memory cells; and (3) Disconnection of formed memory cells from a forming bias voltage. These steps are described in detail below.
Parallel Selection of a Plurality of Bit Lines:
At Step 210, a plurality of bit lines BL for a single assembly buffer 130 is selected in parallel, via a multiplexer 120, by applying a forming bias voltage. The forming bias voltage is output by the assembly buffer 130, and the multiplexer 120 connects the bias forming voltage to the selected bit lines BL. The forming bias voltage may be a continuously ramped voltage, for example, 0.25V per 1 msec.
The multiplexer 120 may select all of its associated bit lines BL in parallel. Alternatively, the multiplexer 120 may select all of its even bit lines BLs, odd bit lines BLs, or any combination of bit lines BL suitable for the intended purpose.
Detection of Successful Formation of Memory Cells:
Next, at Step 220, the formation of one or more memory cells 112 associated with the selected bit lines BL is detected. This detection may occur when a voltage of a respective memory cell 112 is less than a reference voltage, that is, when the resistance of the memory cell 112 changes from insulator to conductor. Similarly, this detection may occur when a current of a bit line BL associated with the memory cell(s) 112 is greater than a threshold current ITh.
The multiplexer 120 comprises a clipping circuit 310, a first switch 320 and a second switch 330. The first and second switches 320, 330 are standard in a multiplexer and determine whether the multiplexer's input is connected to its output. In the positons shown in the figure, the multiplexer's input voltage VIN is connected to its output voltage VOUTi. “OUTi” reflects that the multiplexer 120 has multiple outputs. The circuit 300A shown represents one circuit for each output of the multiplexer 120, that is, for each bit line BL.
The clipping circuit 310 is configured to limit a current supplied to the memory cells 112 associated with the respective bit line BL to a threshold current ITh. If the current were not limited, the current would increase to a value that might destroy the memory cells 112.
The clipping circuit 310 comprises a first PMOS transistor 312, a second PMOS transistor 314, and a current source 316. The first PMOS transistor 312 has a source coupled to an input voltage VIN. The current source 316 has a first terminal coupled between the drain of the first PMOS transistor 312 and a second terminal coupled to ground, and is configured to define the maximum current ITh which can be consumed by the memory cells 112 associated with the bit line BL. The second PMOS transistor 314 has a source coupled to the input voltage VIN and a drain coupled to an output voltage VOUTi. The gates of the first and second transistors 312, 314 are coupled together and to the first terminal of the current source 316. The second PMOS transistor 314 is configured to limit the current supplied to the memory cells 112 associated with the bit line BL to the threshold current ITh.
The clipping circuit 320 is illustrated as being comprised of PMOS transistors, but may be alternatively comprised of NMOS transistors. As is known, a PMOS transistor source is connected to a voltage source. In order to allow current to flow, the gate needs to be pulled to ground, and to turn the current off the gate needs to be pulled to the voltage source.
When the forming is successful at one or more memory cells 112, as shown in
Alternatively, the current clipping could be performed by the assembly buffer 130, and the sensing may be performed by the multiplexer 120 in a manner appreciated by those skilled in the art.
Disconnection of Formed Memory Cells from Forming Bias Voltage:
At Step 230, the one or more formed memory cells is disconnected from the forming bias voltage. More specifically, when one or more of the memory cells 112 is detected as having been successfully formed, a read operation is performed under the control of the processor to determine the specific memory cell(s) 112 that were formed and are disconnected by active addressing.
Finally, Steps 210, 220, and 230 may be repeated on any non-formed memory cells until forming of the memory array 1120 is completed. The criteria for completion could be when all of the memory cells 112 have formed, when a significant enough number of memory cells 112 have formed, a certain time period has elapsed, or any other criteria suitable for the intended purpose.
At Step 410, any of a plurality of word lines WL may be selected in parallel by a word line decoder by applying a forming bias voltage.
Next, at Step 420, formation of one or more memory cells 112 associated with the selected word lines WL may be detected. The current increase cannot be sensed at the word line WL, but must instead be performed at the bit line BL. At any bit line BL current increase detection, the processor interrupts the sequence and actively looks at the different word lines WLs where the current increase occurred to determine which of the memory cells 112 formed. This can be accomplished by the processor using a standard read process. The processor may deselect the word line WL where the current increase occurred and select all of the other word lines WL. This takes more overhead as compared with the parallel selection of bit lines BL, but is another option for increasing parallelism.
At Step 430, the one or more formed memory cells 112 is deselected from the forming bias voltage. The disconnection may be performed by a word line selection device (not shown), or alternatively, by a processor via active addressing.
Finally, Steps 410, 420, and 430 may be repeated on any non-formed memory cells until forming of the memory array 1120 is completed. The criteria for completion could be when all of the memory cells 112 have formed, when a significant enough number of memory cells 112 have formed, a certain time period has elapsed, or any other criteria suitable for the intended purpose.
The memory 110 may be a resistive random access memory (RRAM), though the disclosure is not necessarily limited in this respect.
While the foregoing has been described in conjunction with exemplary embodiment, it is understood that the term “exemplary” is merely meant as an example, rather than the best or optimal. Accordingly, the disclosure is intended to cover alternatives, modifications and equivalents, which may be included within the scope of the disclosure.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present disclosure. This disclosure is intended to cover any adaptations or variations of the specific embodiments discussed herein.
