Claims
- 1. A parallel processing apparatus, comprising:
- a program counter for indicating instructions to be read out from a memory;
- an instruction register for storing a plurality of consecutive instructions read out from an address of said memory indicated by said program counter;
- a plurality of integer units for executing integer-arithmetic operations;
- a floating-point unit for executing floating-point-arithmetic operations; and
- means for controlling said plurality of integer units and said floating point unit to effect either parallel processing of a plurality of consecutive instructions stored in said instruction register in said plurality of integer units and said floating point unit, or successive processing of instructions stored in said instruction register in response to a processing state alteration instruction.
- 2. A parallel processing apparatus, comprising:
- a program counter for indicating instructions to be read out from a memory;
- an instruction register for storing a plurality of consecutive instructions read out from an address of said memory indicated by said program counter;
- a branch arithmetic unit for executing branch arithmetic operations;
- an integer-logic arithmetic unit for executing integer arithmetic operations and logic arithmetic operations;
- a floating-point-arithmetic unit for executing floating-point-arithmetic operations; and
- means for controlling said branch arithmetic unit, said integer-logic arithmetic unit and said floating-point-arithmetic unit to effect either parallel processing of a plurality of consecutive instructions stored in said instruction register in said branch arithmetic unit, said integer-logic arithmetic unit and said floating-point-arithmetic unit, or successive processing of instructions stored in said instruction register in response to a processing state alteration instruction.
- 3. A parallel processing apparatus, comprising:
- a program counter for indicating instructions to be read out from a memory;
- an instruction register for storing a plurality of consecutive instructions read out from an address of said memory indicated by said program counter;
- a branch arithmetic unit for executing branch arithmetic operations;
- a plurality of integer-logic arithmetic units for executing integer arithmetic operations and logic arithmetic operations;
- a plurality of floating-point-arithmetic units for executing floating-point-arithmetic operations;
- means for controlling said branch arithmetic unit, said integer-logic arithmetic units and said floating-point-arithmetic units to effect either parallel processing of a plurality of consecutive instructions stored in said instruction register in said branch arithmetic unit, said plurality of integer-logic arithmetic units and said plurality of floating-point-arithmetic units, or successive processing of instructions stored in said instruction register in response to a processing state alteration instruction.
Priority Claims (1)
Number |
Date |
Country |
Kind |
1-173914 |
Jul 1989 |
JPX |
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Parent Case Info
This is a continuation of application Ser. No. 08/149,932, filed Nov. 10, 1993, now U.S. Pat. No. 5,404,472, which is a continuation of application Ser. No. 07/549,916, filed Jul. 9, 1990, now U.S. Pat. No. 5,287,465 and a Continuation-in-Part of application Ser. No. 07/433,368, filed Nov. 8, 1989, now U.S. Pat. No. 5,233,694.
US Referenced Citations (9)
Foreign Referenced Citations (4)
Number |
Date |
Country |
0042442 |
Dec 1981 |
EPX |
0101596 |
Aug 1983 |
EPX |
0147858 |
Jul 1985 |
EPX |
0239081 |
Sep 1987 |
EPX |
Non-Patent Literature Citations (2)
Entry |
David T. Hilja "Reducing the Branch Penalty in Pipe-line Processors" Computer (Jul. 1988) pp. 47-55. |
Miller et al. "Floating-Duplex Decode and Execution of Instructions", IBM Technical Disclosure Bulletin (vol. 23, No. 1) (Jun. 1980) pp. 409 to 412. |
Continuations (2)
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Number |
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Parent |
149932 |
Nov 1993 |
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Parent |
549916 |
Jul 1990 |
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