Claims
- 1. A parallel processing apparatus, comprising:
- a program counter for indicating instructions to be read out from a memory;
- a plurality of instruction registers for respectively storing instructions therein indicated by said program counter;
- a plurality of arithmetic units for executing arithmetic operations;
- means for controlling said plurality of arithmetic units to effect either parallel processing of a plurality of consecutive instructions read out from an address of said memory indicated by said program counter in said plurality of arithmetic units, or successive processing of n consecutive instructions, read out from an address of said memory indicated by said program counter, in which said n consecutive instructions correspond to said plurality of arithmetic units, respectively, when the instruction is supplied to each of the arithmetic units from the instruction register.
- 2. A parallel processing apparatus according to claim 1, said means for controlling said plurality of arithmetic units in response to either a processing state alteration instruction or control signal through pin which has said parallel processing apparatus from outside.
- 3. A parallel processing apparatus according to claim 1, further comprising means for controlling said program counter to increment either m or 1 according to a value indicated by said processing state flag.
- 4. A parallel processing apparatus according to claim 1, further including a sequencer for controlling said program counter, said sequencer comprising a wired-logic circuit.
- 5. A parallel processing apparatus according to claim 1, further including a sequencer for controlling said program counter, said sequencer being implemented by a microprogram.
Priority Claims (1)
Number |
Date |
Country |
Kind |
1-173914 |
Jul 1989 |
JPX |
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CROSS-REFERENCE TO THE RELATED APPLICATION
This application is a Continuation of application Ser. No. 07/549,916, filed Jul. 9, 1990, now U.S. Pat. No. 5,287,465, which is a Continuation-in-Part of U.S. application Ser. No. 07/433,368, filed Nov. 8, 1989, now U.S. Pat. No. 5,233,694, issued Aug. 3, 1993.
US Referenced Citations (1)
Number |
Name |
Date |
Kind |
4942525 |
Shintani et al. |
Jul 1990 |
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Non-Patent Literature Citations (2)
Entry |
David T. Hilja "Reducing the Branch Penalty in Pipe-line Processors," Computer (Jul. 1988) pp. 47-55. |
Miller et al. "Floating-Duplex Decode and Execution of Instructions", IBM Technical Disclosure Bulletin, vol. 23, No. 1, (Jun. 1980) pp. 409-412. |
Continuations (1)
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Number |
Date |
Country |
Parent |
549916 |
Jul 1990 |
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Continuation in Parts (1)
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Number |
Date |
Country |
Parent |
433368 |
Nov 1989 |
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