Patent Grant
10553353
The present invention relates to a high performance, on-chip inductor typically utilized in RF circuits. In particular, the present invention relates to an improved on-chip inductor, and methods of making the same. Specifically, the inductor is a parallel stacked structure which achieves a higher Q value for the same inductance density and current handling of presently employed on-chip inductors.
Many structures have been proposed for the manufacture of inductors in integrated circuits. These structures comprise a planar, spiral arrangement of conductive track, arranged in a plane parallel to the semiconductor substrate.
Inductors in particular are critical components in oscillators, power amplifiers and other tuned circuits. For low-frequency applications, passive devices can be connected externally, but as the frequency increases, the characteristics of the passive devices would be overwhelmed by parasitic effects.
Basically there are three shapes of on-chip spiral inductors. They are square, octagonal and circular. Although a circular shaped inductor may be more efficient from a Q standpoint, the shape of inductor is often limited to the availability of fabrication processes. Most processes restrict all spiral angles to be 90° or 45°, and octagonal/square patterns are a natural choice. Structural parameters such as the outer dimension, number of turns, the distance between the centers of lines (or pitch), and substrate property are all important factors in determining the performance of on-chip inductors.
While microelectronic inductor structures are thus desirable and often essential within the art of microelectronic fabrication, microelectronic inductor structures are nonetheless not entirely without problems in the art of microelectronic fabrication. In that regard, it is typically desirable in the art of microelectronic fabrication, but nonetheless not always readily achievable, to fabricate microelectronic devices having formed therein microelectronic inductor structures with optimal properties, as characterized by enhanced Q values of the microelectronic inductor structures. (High-Q inductors are utilized in many electronic devices, such as TV turners, RF chokes, low noise amplifiers, voltage controlled oscillators, and power amplifiers, to name a few.)
The quality factor Q is an extremely important figure of merit for an inductor at high frequencies. For an inductor, only the energy stored in the magnetic field is of interest. Basically, it describes how good an inductor can work as an energy-storage element. In the ideal case, inductance is a pure energy storage element (Q approaches infinity), while in reality parasitic resistance and capacitance reduce Q. This is because the parasitic resistance consumes stored energy, and the parasitic capacitance reduces inductivity (the inductor can even become capacitive at high frequencies). Self-resonant frequency fSR marks the point where the inductor turns to capacitive and, obviously, the larger the parasitic capacitance, the lower the fSR.
On-chip inductors are key passive components in radio frequency/millimeter wave integrated circuits. In the design of semiconductor device radio frequency integrated circuits, inductors are very important devices to be considered. It has been shown that along with the miniaturization of devices, the traditional planar type of inductor, which occupies a large area, fails to conform to current demands. Moreover, conflicting requirements exist in on-chip inductor designs. For example, current handling of the inductor increases with width and thickness of the inductor line segments; however, Q decreases with width and thickness due to the increased proximity effect.
On-chip inductors are used in RF microelectronic devices for eliminating impedance mismatching, minimizing reflection and losses, securing required resonance frequencies, and cutting AC currents such as high frequency comparisons in power supply lines, among other uses. RF coils (inductors) are usually wound on a single layer. An RF inductor reduces proximity effects and parasitic capacitance. RF inductors generally have windings that are wound on a single layer, with turns spaced apart.
In U.S. Pat. No. 7,592,891, issued to Hsu, et al. on Sep. 22, 2009 titled “PLANAR SPIRAL INDUCTOR STRUCTURE HAVING ENHANCED Q VALUE,” a planar spiral conductor layer is formed over a substrate, establishing a planar spiral inductor, wherein a successive series of spirals within the planar spiral conductor layer are formed with a variation in: (1) a series of line widths of the successive series of spirals; and, (2) a series of spacings of the successive series of spirals.
It is desirable to design and fabricate on-chip inductors with characteristics of small size, high quality factor (Q factor), large inductance, and high self-resonating frequency that are improved from known devices in the art. It is important to make on-chip inductors consume as little real estate as possible to mitigate large parasitic capacitance between the on-chip inductor and the substrate in order to reduce unwanted noise. It is also desirable to introduce an on-chip inductor that achieves a higher Q value for the inductance density and current handling of present RF on-chip inductors.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a high efficiency inductor for integrated circuit applications that minimizes the footprint associated with the inductor layout on the substrate.
It is another object of the present invention to provide a parallel stacked inductor structure which achieves a higher Q value for typical values of inductance density and current handling.
The above and other objects are achieved in the present invention, which is directed at a parallel stacked inductor for an integrated circuit, the inductor comprising a plurality of metal layers having a plurality conductive spiral winding segments thereon, wherein the width and/or thickness of spiral winding segments on a top metal layer and/or spiral winding segments of a bottom metal layer are increased only at locations where the respective spiral winding segments are broken for overpass or underpass connections, respectively.
The spiral winding segments may comprise multiple layer of parallel stacked conductive path segments. Adjacent spiral winding segments of a top metal layer may be joined using underpass and overpass connections without electrically shorting to respective conductive path segments.
The bottom metal layer may include multiple spiral segment bar vias for higher Q and current carrying.
The underpass and/or overpass connections are configured to have a width wider than the spiral winding segments.
The bottom metal layer may include wider track widths than the top metal layer with overpass configuration and vice versa with underpass configuration to reduce series losses and increase current handling.
Multiple spiral winding segments of top and bottom spirals can be interconnected in such a way that their electrical path lengths are approximately equal.
The outermost spiral winding segments of a given spiral turn may be electrically connected to innermost spiral winding segments of a subsequent spiral turn.
The top or bottom metal layers comprise a continuous conductive path while the other spiral is broken for underpass/overpass connection.
One or more lower metal layers of the plurality of metal layers can be used to selectively connect to the lower spiral of the parallel stacked inductor for further improved current handling, including having an increased thickness and/or width as compared to the top metal layer. The increased thickness and/or width is localized along the at least one lower metal layer of the plurality of metal layers such that a gradual decrease in the thickness and/or width is formed along at least one turn of the spiral winding segments.
A thermal dissipation mechanism may be employed within or adjacent to at least one of the spiral winding segments.
In a second aspect, the present invention is directed to a method of forming a parallel stacked inductor for an integrated circuit, comprising: providing a substrate; forming an upper metal layer on the substrate having a plurality of conductive segments having a width and winding in an approximate spiral-shaped pattern, with outer conductive segments adjacent to inward conductive segments; forming an overpass junction at termination points of the plurality of conductive segments, the overpass junction having a width greater than the conductive segments width; and forming a bottom metal layer parallel to, and underneath, the upper metal layer, the bottom metal layer being a continuous conductive path having a width and winding in an approximate spiral-shaped pattern, and including multiple bar vias traversing the continuous conductive path.
The plurality of conductive segments of the upper metal layer are equidistant from one another. The overpass junction at each segment electrically connects an outermost path of one spiral turn with an innermost path of a next spiral turn, allowing for equal current path length over the course of the spiral winding.
An arbitrary number of spiral turns may be employed, wherein a number of bends at an ith spiral turn is equal to (i−1) if all protrusions are inwards, and equal to (i−2) if an outermost turn protrudes outwards for i>2.
The bottom metal layer may be tailored for high current handling, including increasing a thickness and/or width of the bottom metal layer as compared to the top metal layer.
An increased thickness and/or width along the bottom metal layer may be utilized such that a gradual decrease in the thickness and/or width is formed along at least one of the plurality of conductive segments.
The features of the invention believed to be novel and the elements characteristic of the invention are set forth with particularity in the appended claims. The figures are for illustration purposes only and are not drawn to scale. The invention itself, however, both as to organization and method of operation, may best be understood by reference to the detailed description which follows taken in conjunction with the accompanying drawings in which:
In describing the preferred embodiment of the present invention, reference will be made herein to
A substrate is a solid (usually planar) layer of substance onto which a layer of another substance is applied, and to which that second substance adheres. In some instances, a substrate can be a semi-conductive material, an electrical insulator, or some combination thereof. Different types of substrates can be used for different types of fabrication process. Many integrated circuits (ICs) are fabricated onto multilayered substrates that include at least a layer of semi-conductive material. Individual electronic devices can be fabricated (e.g., etched, deposited, or otherwise formed) onto the wafers (e.g., via a photolithography process), including such on-chip devices as resistors, capacitors, inductors, and transformers.
Inductors are essentially coils which generate a magnetic field that interacts with the coil itself, to induce a back electromagnetic field (EMF) which opposes changes in current through the coil. Inductors are used as circuit elements in electrical circuits to temporarily store energy or resist changes in current. An inductor is characterized by its inductance (L), the ratio of the voltage to the rate of change of current, and which has units of Henries (H). Inductance (L) results from the magnetic field around a current-carrying conductor, insomuch as the electric current through the conductor creates a magnetic flux. Inductance is determined by how much magnetic flux through the circuit is created by a given current.
Current technology improvements and advancements has required the need for inductors to be used on and within substrates, using planar device fabrication techniques.
In another attempt to vary the peak-Q frequency, some designs will also electrically connect the stacked layers with selectively placed metal shunts, such as the selective metal shunting taught in IEEE TCAS-1, September 2005.
High current designs like power amplifiers demand usage of extremely wide spiral tracks to prevent issues like electro-migration. However, wider spiral tracks necessarily lead to higher eddy current loses (which are proportional to the width of the spiral segments). This is detrimental to the resistance and the quality factor. A favored design would be where the Q-value increases as the resistance decreases, thus accommodating increased current capability.
The resistance and critical frequency for spiral inductors are expressed as follows:
where,
=(i−1) if all the protrusions are inwards; and
=(i−2) if the outermost turn protrudes outwards (for i>2).
The metal line octahedral segments are preferably aluminum and/or copper in composition, although other conductive materials may be utilized, combined, or incorporated. As noted in
Junction 76 is designed to extend the width of bottom metal layer 70 at these current cross-over locations. Junction 76 is a wider section of bottom metal layer 70.
Each conductor segment is approximately the same width as the next segment (except at the junction and overpass locations), which promotes consistent inductance and impedance transformation. Furthermore, the cross-over connections may attach segmented portions at different layers of a multiple layered substrate. These segments carry the same current in the same direction, and are configured for parallel stacking.
In preferred instances, in the case of parallel stacking, when one of the spiral segments is broken, an overpass/underpass connection is provided to complete the primary or secondary winding. The overpass/underpass segments enjoy a great width than their adjoining metal line segments.
Independent of the overpass/underpass design, several modifications may be made to the windings to enhance performance. In another embodiment, the top section of the spiral segments may also be designed with gradually decreasing width and increasing spacing from the outermost turn to the innermost turn to mitigate series losses.
Additionally, the bottom section may also have wider track widths than the top section to reduce series losses and increase current handling.
In one embodiment these multiple segments are interconnected in such a way that their path lengths may be equal. For example the outermost segment of a given spiral turn may be connected to the innermost segment of the subsequent spiral turn, etc.
The inductance as a function of frequency was found to be enhanced over a wide frequency spectrum, resulting in approximately an eight percent (8%) improvement.
Another advantage of the present design is the promotion of equal path length for the winding. This is possible because the winding is effectively shared across two current paths, where the outermost segment of one path of the winding is electrically connected to the innermost segment of the adjacent winding segment.
It is also noted that the lower metal layers may be tailored for high current handling by increasing the thickness and/or width as compared to the top metal layer. The increase in thickness and/or width of these lower metal layers may be localized in the bottom spiral(s), and gradually decrease in width of the spiral along each turn from the outermost turns to the innermost turns.
Furthermore, selective use of coolants and other thermal dissipation mechanisms 90 known in the art may be employed within or adjacent to the spiral winding segments that are more vulnerable than the others.
Magnetic materials may also be employed in the fabrication of the parallel stacked inductor.
In addition, a method for generating the spiral turns with an arbitrary number of turns is taught. In a preferred embodiment, the number of bends at the ith spiral turn is equal to (i−1) if all the protrusions are inwards, and equal to (i−2) if the outermost turn protrudes outwards (for i>2).
While the present invention has been particularly described, in conjunction with a specific preferred embodiment, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art in light of the foregoing description. It is therefore contemplated that the appended claims will embrace any such alternatives, modifications and variations as falling within the true scope and spirit of the present invention.
| Number | Name | Date | Kind |
|---|---|---|---|
| 4956626 | Hoppe | Sep 1990 | A |
| 5831331 | Lee | Nov 1998 | A |
| 6002161 | Yamazaki | Dec 1999 | A |
| 6031445 | Marty et al. | Feb 2000 | A |
| 7064411 | Hashizume | Jun 2006 | B2 |
| 7592891 | Hsu et al. | Sep 2009 | B2 |
| 9449753 | Kim | Sep 2016 | B2 |
| 20110133875 | Chiu | Jun 2011 | A1 |
| Number | Date | Country | |
|---|---|---|---|
| 20180144857 A1 | May 2018 | US |
