Claims
- 1. A process for passivating a magneto-resistive bit having a top surface and side walls characterized by encapsulating the top and side wall surfaces of a magneto-resistive bit with a conductive etch stop barrier layer.
- 2. A process for passivating a magneto-resistive bit structure characterized by the steps of:
providing a GMR stack upon a substrate; selectively patterning said GMR stack to form at least one GMR bit having a top surface and side walls; providing an etch stop barrier layer that encapsulates the patterned GMR stack including the top surface and side walls of the GMR bit; and selectively patterning said barrier layer so that the edges of the barrier layer extend out past the edges of the GMR bit.
- 3. A process for passivating a magneto-resistive bit structure characterized by the steps of:
providing a GMR stack upon a substrate; providing an etch stop barrier layer upon said GMR stack; providing a first dielectric layer upon said barrier layer; building an ion mill mask upon said barrier layer by reactive ion etching of said first dielectric layer; patterning said GMR stack and said barrier layer by ion milling to provide a patterned GMR stack having side walls and a patterned barrier layer having side walls, and removing said ion mill mask; providing a second dielectric layer upon the patterned barrier layer; planarizing said second dielectric layer; and etching the planarized second dielectric layer to leave dielectric spacers along the side walls of the patterned GMR stack.
- 4. A process according to claim 3, wherein said dielectric spacers are left along the side walls of the patterned GMR stack and along a portion of the side walls of said barrier layer.
- 5. A process according to claim 3, wherein said dielectric spacers extend from the top of said substrate up to the side walls of said barrier layer.
- 6. A process according to claim 3, wherein said etch stop barrier layer comprises CrSi.
- 7. A process according to claim 3, wherein said first dielectric layer comprises SiN.
- 8. A process according to claim 3, wherein said second dielectric layer comprises SiN.
- 9. A process for passivating a magneto-resistive bit structure characterized by the steps of:
providing a GMR bit on a substrate, the GMR bit having a top surface and exposed side walls; providing dielectric spacers along at least part of the exposed side walls of the GMR bit, the spacers extending laterally away from the GMR bit for a predetermined distance before having side walls; and providing a barrier layer along at least a portion of the top surface of the GMR bit, the barrier layer having side walls.
- 10. A process according to claim 9, further comprising the step of providing a conductive contact layer over at least part of the barrier layer and laterally past the side walls of the spacers.
- 11. A process according to claim 9, wherein the barrier layer is provided before the spacers.
- 12. A process according to claim 9, wherein the spacers are provided before the barrier layer.
- 13. A process according to claim 9, wherein the side walls of the barrier layer substantially coincide with the side walls of the GMR bit.
- 14. A process according to claim 9, wherein the spacers extend up beyond the top surface of the GMR bit and along the side walls of the barrier layer.
CROSS-REFERENCE TO RELATED CO-PENDING APPLICATION
[0001] This application is a divisional of U.S. patent appplication Ser. No. 09/638,419, filed Aug. 14, 2000, entitled “PASSIVATED-MAGNETO-RESISTIVE BIT STRUCTURE AND PASSIVATION METHOD THEREFOR,” which is incorporated herein by reference.
Divisions (1)
|
Number |
Date |
Country |
Parent |
09638419 |
Aug 2000 |
US |
Child |
10057162 |
Jan 2002 |
US |