PATCHABLE AND/OR PROGRAMMABLE PRE-DECODE

Abstract

Mechanisms have been developed for providing great flexibility in processor instruction handling, sequencing and execution. In particular, it has been discovered that a programmable pre-decode mechanism can be employed to alter the behavior of a processor. For example, pre-decode hints for sequencing, synchronization or speculation control may altered or mappings of ISA instructions to native instructions or operation sequences may be altered. Such techniques may be employed to adapt a processor implementation (in the field) to varying memory models, implementations or interfaces or to varying memory latencies or timing characteristics. Similarly, such techniques may be employed to adapt a processor implementation to correspond to an extended/adapted instruction set architecture. In some realizations, instruction pre-decode functionality may be adapted at processor run-time to handle or mitigate a timing, concurrency or speculation issue. In some realizations, operation of pre-decode may be reprogrammed post-manufacture, at (or about) initialization, or at run-time.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

FIG. 1 is a block diagram of an exemplary multicore processor configuration including pre-decode and decode facilities that may be patched and/or updated in accordance with some embodiments of the present invention.

FIG. 2 is a block diagram illustrating a programmable pre-decode facility in accordance with some embodiments of the present invention.

FIG. 3 is a flowchart illustrating update of a programmable pre-decode array in accordance with some embodiments of the present invention.

FIG. 4 is a block diagram illustrating a programmable decode facility in accordance with some embodiments of the present invention in which selection of either a fixed decode path or operation sequences from a helper array is based on information introduced into an instruction stream by a configurable pre-decode facility.

FIG. 5 is a flowchart illustrating update of a programmable helper array in accordance with some embodiments of the present invention and selection, based on a configurable pre-decode block, of selected sequences from the helper array based on an updated pre-decode configuration.

FIG. 6 illustrates block diagram of an exemplary computer system consistent with at least some embodiments of the present invention.

Claims

1. A computing apparatus comprising: an instruction store that includes storage for predecode information in association with instructions; anda predecode block coupled between a memory interface and the instruction store to supply the predecode information for association with the instructions, the predecode block including both a fixed predecode path and a programmable predecode path, wherein the computing apparatus is configurable to selectively employ the programmable predecode path for at least some instruction patterns.

2. The computing apparatus of claim 1, wherein the selective employment of the programmable predecode path is, itself, programmable.

3. The computing apparatus of claim 1, further comprising: a decode block coupled between the instruction store and one or more execution pipes of the computing apparatus.

4. The computing apparatus of claim 1, wherein the programmable predecode path comprises: a programmable multi-entry store, wherein individual entries thereof correspond to respective instruction patterns and are programmable to encode, for at least some of the instruction patterns, at least a portion of the predecode information supplied for association with respective instructions.

5. The computing apparatus of claim 1, further comprising: a decode block coupled between the instruction store and an execution pipe of the computing apparatus, the decode block including a helper store, wherein at least some instruction patterns are associable with helper sequences retrievable from the helper store, andwherein the programmable predecode path comprises:a programmable multi-entry store, wherein individual entries thereof correspond to respective instruction patterns and are programmable to encode, for at least some of the instruction patterns, respective identifiers into the helper store.

6. The computing apparatus of claim 5, wherein at least some of the individual entries of the programmable multi-entry store include a coding selective one or the other of the programmable predecode path and the fixed predecode path.

7. The computing apparatus of claim 5, wherein the helper store is itself programmable.

8. The computing apparatus of claim 1, wherein the programmable predecode path includes a store that is programmable post manufacture.

9. The computing apparatus of claim 1, further comprising: replicated fetch-decode paths,wherein the instruction store includes a fetch buffer of at least one of the fetch-decode paths.

10. The computing apparatus of claim 9, wherein plural of the fetch buffers share an instruction cache that itself associates the instructions with the supplied predecode information.

11. The computing apparatus of claim 1, embodied as a computing system and further comprising: a memory hierarchy coupled to the memory interface.

12. The computing apparatus of claim 1, embodied as either: a processor integrated circuit, ormedia encoding a design file representation of the computing apparatus.

13. A method of operating a processor, the method comprising: generating predecode information corresponding to instructions retrieved from a memory interface; andsupplying the predecode information for association with the instructions, wherein the supplied predecode information includes, for at least some instruction patterns, information retrieved from a programmable multi-entry store.

14. A method as recited in claim 13, further comprising: selectively employing a programmable predecode path that includes the programmable multi-entry store.

15. A method as recited in claim 13, wherein the employment of the programmable predecode path is based, at least in part on information encoded in the programmable multi-entry store.

16. A method as recited in claim 13, further comprising: selectively employing a fixed predecode path for at least some instruction patterns.

17. A method as recited in claim 13, further comprising: predecoding at least some of the instructions retrieved from the memory interface using a fixed predecode path; andpredecoding at least others of the instructions retrieved from the memory interface using information retrieved from the programmable multi-entry store.

18. A method as recited in claim 13, further comprising: storing both instructions predecoded using the fixed predecode path and instructions predecoded using the programmable multi-entry store into an instruction store.

19. A method as recited in claim 13, wherein at least some entries of the programmable multi-entry store include a coding selective one or the other of a programmable predecode path and a fixed predecode path.

20. A method as recited in claim 13, further comprising: programming the programmable store after manufacture of the processor.

21. A method as recited in claim 20, wherein the programming is performed under control of instructions of the processor's instruction set that natively are predecodable using the fixed predecode path.

22. A method of tailoring, post manufacture, instruction set behavior of a processor, the method comprising: defining, post-manufacture, contents of a programmable predecode store such that at least some entries thereof encode override predecode information for at least some instruction patterns; andcausing the processor to thereafter associate the override predecode information with corresponding instructions of an instruction sequence.

23. A method as recited in claim 22, further comprising: after the defining, re-defining the contents of a programmable predecode store and causing the processor to thereafter associate revised override predecode information with corresponding instructions of an instruction sequence.

24. A method as recited in claim 22, further comprising: performing the defining coincident with boot or initialization of a computing system that includes the processor.

25. A method as recited in claim 22, further comprising: performing the defining during a course of a computation executing on a computing system that includes the processor.