Patent Application
20160069977
The invention relates to concepts such as the Internet of Things (IoT), Smart Home and Smart Cities that require the development and deployment of a wide variety of computing devices incorporated into the Internet infrastructure. Unsupervised sensing is the cornerstone capability that these devices must have to perform useful functions, while also having low cost of acquisition and ownership, little energy consumption and a small footprint. Impedimetric sensing systems based on the so-called single-frequency DFT detectors possess many of these desirable attributes and are often introduced in remote monitoring and wearable devices.
Single-frequency (single-point, single-bin) discrete Fourier transform (DFT) detectors are known in the art. Such systems and devices include digital detectors or receivers also known as sine wave correlators, homodyne and synchrodyne detectors and digital synchronous quadrature detectors/demodulators. More specifically, such DFT detectors calculate the inner product of a finite input sequence of digitized samples equally spaced in time (input vector) by a likewise sampled complex-valued exponential function of a given test frequency (analysis or test vector) thereby producing a single complex value comprised of the in-phase and quadrature components of the input at the test frequency.
Such detectors find practical applications across diverse variety of fields: resonator-based measurements in structural health and fluid properties monitoring, non-resonant impedimetric measurements of corrosion, electrochemistry and bioimpedance.
Without limitation, and without being bound by theory not expressly recited in the claims, the following references are representative examples of the applications in which DFT detectors are used or can be used for practical measurements:
While there may be multiple ways of implementing DFT detectors utilizing various hardware designs and digital signal processors (DSPs), of a particular interest for practical applications are the commercially available, single-chip DFT devices designed specifically for impedimetric applications by Analog Devices:
All the art cited above is predominantly focusing on the end applications and lacks specific error analysis in conjunction with operation frequency range and calibration methods, relying heavily on the information from the device datasheet. For example, the operating frequency range with a 16 MHz clock is stated to be from 1 KHz to 100 KHz with the system accuracy of 0.5%. for the impedance dynamic range of 1 kΩ to 10 MΩ, but no experimental data on accuracy given.
The calibration procedure proposed in the AD5933 datasheet and widely replicated in the literature does not take into account the errors caused by discontinuous test phasor: resulting form the DC offset at the detector input and the cross-talk between in-phase and quadrature channels. The calibration procedure described in the art produces a single multiplicative gain factor that leads to rather sizeable systematic errors and undue disappointment in the device performance (see publication (4)), especially at the lower end of the operation frequency range.
Notwithstanding the various advances known in the art in connection with utilization of DFT detectors, there remains a need in the art for improvements, especially improvements which enhance the accuracy and versatility of such detectors in a variety of applications, allowing for reduction in hardware, footprint, power consumption, cost and environmental impact of the resulting electronic products.
As with any kind of digital implementation of a mathematical algorithm the DFT suffers from inaccuracies resulting from limited precision of binary representations of real numbers and functions. These computation errors are typically grossly overshadowed by the quantization errors and sampling artifacts caused by the discrete nature of the DFT, which usually have to be mitigated to achieve accurate results.
While the particularities of the input signal vector do contribute to the detector output value, their presence may be hidden from the practitioner and not taken into account during the device calibration. This may lead the practitioners away from using DFT detectors in their designs and unnecessary settling for much more expensive and redundant technical solutions narrowing the potential market for the final product.
Single-frequency DFT detectors utilized in impedimetric measurements suffer from a particular kind of systematic error that is erroneously attributed to spectral leakage in the literature. DFT is calculated as the inner product of the sampled signal vector being measured and the sampled test phasor. Spectral leakage is the type of error that occurs in DFT when the frequency of the signal being measured differs from the frequency of the test phasor. In impedimentric measurements with DFT detectors one of the phasor components is utilized for generation of excitation stimulus which, therefore, has the same frequency as the test phasor The device under test (DUT) response has the same frequency as the stimulus (if non-linear, may contain higher harmonics of the stimulus) and thus can not cause spectral leakage.
Due to practical hardware limitations in the length of sampled signal vector and phasor, these vectors rarely contain integer number of cycles at a given frequency, which, from the standpoint of Fourier analysis, makes such phasors discontinuous. These discontinuous test phasors do not form a proper orthogonal Fourier basis and that is what is causing gross deviation form the Fourier results predicted by the theory for continuous phasors.
As those errors were historically attributed to spectral leakage, windowing—the well-known method for spectral leakage suppression—is applied to the errors caused by discontinuous test phasors. While helping to a certain degree, windowing further obscures the nature of the systematic errors and still does not allow DFT detectors to operate at full frequency range and accuracy afforded by the hardware. Attributing this specific type of error to spectral leakage not only leads to inefficient error mitigation procedures and algorithms, but also to incorrect calibration procedures.
The present inventions provide apparatus, systems and methods related to operation of DFT detectors.
More specifically this invention discloses a calibration method and a system that eliminates all sources of errors caused by discontinuous test phasors. This method achieves accuracy limited only by the hardware errors resulting from the digital implementation of the DFT: accuracy of the direct digital synthesizer (DDS), signal digitization by sampling ADC and fixed-point arithmetic truncation in DFT core.
More specifically this invention discloses a method and a system that measures both AC and DC signals utilizing the same DFT detector hardware for both types of measurements.
More specifically this invention discloses a method that significantly extends operation frequency range of the DFT detector, especially the lower limit, without using additional hardware.
The present invention discloses that the discontinuous test phasor causes the DC signal present at the DFT detector input to affect the detector in-phase and quadratrure outputs when the test phasor is discontinuous. This DC error is additive in nature and can be considered a “DC leakage” from the detector input to the detector in-phase and quadrature outputs. The error produced by DC offset is proportional to the offset magnitude and can be expressed by in-phase GI and quadrature GQ gain factors. In case of continuous test phasors both gains would be equal zero at any frequency.
The present invention discloses that these DC leakage error gain factors can be explicitly expressed as follows:
where f is a normalized test frequency (test frequency divided by sampling frequency) and N is the total number of samples used to perform DFT.
The present invention discloses that for the AC signals the discontinuous test phasor causes the detector in-phase and quadrature gains to be frequency-dependent (instead of constant) and also causes be frequency-dependent cross-talk between the detector in-phase and quadrature outputs. These frequency-dependent gains and cross-talk can be considered a form of an “AC leakage” of the input signal to the detector outputs and cross-talk a form of “AC leakage” between the detector outputs.
The present invention discloses that said AC gain and cross-talk effects can be expressed in a matrix form as follows:
where SI and SQ are the DFT detector outputs, diagonal matrix elements a and d are the in-phase and quadratrure gains, matrix element b is the cross-talk factor, A and co are the AC signal amplitude and phase.
The present invention discloses that said matrix elements a, b and d can be explicitly expressed as follows:
where f is a normalized test frequency (test frequency divided by sampling frequency) and N is the total number of samples used to perform DFT.
The present invention discloses that with the expressions (2) above, it is possible to calculate all three matrix elements a, b and d for any frequency f and length of the sampled signal vector N and then for any detector output values of SI and SQ to completely eliminate the AC leakage by simply solving the system of linear equations for A Cos(φ) and A Sin(φ):
Detailed derivation of the above expressions is given in (38) Matsiev, L. Improving Performance and Versatility of Systems Based on Single-Frequency DFT Detectors such as AD5933. Electronics 2015, 4, 1-34, incorporated herein by reference in its entirety.
The present invention discloses that calibration procedures for single-frequency DFT detectors known in the art can not eliminate the DC and AC errors related to discontinuous test phasor and are inadequate for the detector to operate in presence of the DC offset in the signal and/or within broad frequency range.
The present invention discloses that prior to attempting conventional calibration, the DFT detector response to DC offset within working frequency range must be recorded and stored in some form of intermediate memory. Matrix elements a, b and d have to be calculated and stored in some form of intermediate memory for the same working frequency range at the same set of frequency points. In presence of AC signal of interest detector outputs SI and SQ have to be recorded within same working frequency range at the same set of frequency points and the DC data stored earlier must be subtracted from SI and SQ at each frequency point. Then thus corrected values and matrix elements a, b and d must be substituted into expressions (3) and the in-phase A Cos(φ) and quadrature A Sin(φ) components of the AC signal of interest calculated. Only at this stage these two values can be used in the conventional calibration procedure to obtain a single multiplicative gain factor.
Those skilled in the art would appreciate that, without loss of generality, multiple variations of this procedure yielding the same result can be implemented. For example, matrix elements a, b and d can be calculated at the instance the detector outputs SI and SQ have been acquired, earlier collected DC responses subtracted and expressions (3) evaluated “on the fly” at a given frequency point using less intermediate storage, etc.
The present invention discloses that application of these methods of error elimination achieves the maximum accuracy possible for a given DFT detector implementation. The remaining systematic accuracy-limiting factors are intrinsic to the detector digital design: truncation of the test phasor amplitude and phase, limited resolution of the digitized input, truncations in the DFT fixed-point arithmetic, etc.
The present invention discloses that the expressions above allows for easy identification and correction of the fixed-point arithmetic overflow that may occur depending on given implementation of the DFT and the magnitude of the input DC and AC signals. As any fixed-point implementation restricts the dynamic range of the operands involved in the DFT calculations due to the hardware-limited bitlength, the summations may result in overflow. With the developed knowledge of the DC and AC leakage as a function of normalized frequency it is straightforward to anticipate the overflow near the extrema of the in-phase and quadrature gains GI, GQ, a and d and correct for it once it occurs.
Various further aspects, embodiments and features of the invention are described herein throughout the specification and drawings. Various features of the invention, including features defining each of the various aspects of the invention, including general and preferred embodiments thereof, can be used in various combinations and permutations with other features of the invention. Features and advantages are described herein, and will be apparent from the Drawings and the following Modes for Carrying out the Invention and examples further describing the invention.
Various aspects of the figures are described in further detail below, in connection with the Modes for Carrying out the Invention.
The present inventions provide apparatus, systems and methods related to impedimetric measurements utilizing single-frequency DFT detectors. The apparatus, systems and methods of the invention are more specifically aimed at detector errors elimination to achieve the maximum accuracy possible for a given DFT detector implementation.
The examples of impedimetic systems on a chip based on DTF detector are the AD5933, AD5934 and ADuCM350 by Analog devices. According to the AD5933 datasheet, the AD5933 is an impedance converter system solution that combines a programmable direct digital synthesizer (DDS) with a sampling ADC, Hanning window, and a DFT detector that returns real and imaginary data-words at a fixed sampling frequency and pre-programmed test frequency. The AD5933 device is a nearly ideal platform for implementation of the invented methods as it dramatically exhibits all the effects of the single-frequency DFT detector-based system described in the Disclosure of Invention above.
Applications based on AD5933 can greatly benefit from the invented methods as the calibration techniques described in the datasheet and widely replicated in the literature are often inadequate. Also, there is an interest in low-frequency applications of this integrated circuit for measuring bio-impedance, corrosion, fluid monitoring, structural health, water quality, and properties of loudspeakers, manifested in a number of publications listed above. The known solution to AD5933 low-frequency operation is based on dividing down the external clock frequency, which requires additional hardware. The invented methods allow for significant expansion of the low end of the frequency range without any additional hardware.
The only hardware necessary to demonstrate the invention is the commercially available AD5933 evaluation board by Analog Devices. To demonstrate the performance of the invented methods high-accuracy, calibrated resistors and capacitors were utilized. The evaluation board is supplied with the software that allows the user to communicate with the AD5933 over the USB interface, setup and perform frequency sweeps and store the data from “Real” and “Imaginary” registers of the AD5933 as text files. “Real” and “Imaginary” data registers correspond to in-phase and quadratrure outputs of the DFT detector discussed earlier.
The AD5933 is a complete single-chip network analyzer: it synthesizes its own excitation voltage, performs current defection, sampling, A-to-D conversion and DFT processing. As such, it is a closed system (a “black box”) that can be best characterized by using known calibrated impedances as DUTs and observing whether the digital output conforms to the response predicted by theory for a given DUT.
To bridge the gap between the expressions provided in previous sections and practical application, it is necessary to provide values for the variables. From the AD5933 datasheet, the length of the sampled signal vector is 1024, so N=1024. From the block overview diagram of the AD5933 in the datasheet [
The DDS is based on a 27-bit phase accumulator, which increments by the Frequency Code at every tick of the system clock; therefore, the frequency of the accumulator overflows is Frequency Code/227. Although not stated explicitly, from the text in the datasheet it follows that the sampling of the input (and also the test phasor) takes place every 4 accumulator increments. Then the current phase of the test phasor at a given summation index k is 2π·(4·Frequency Code/227)·k plus some residual value from the accumulator previous overflow. Therefore, the normalized frequency f=4·Frequency Code/227 or f=Frequency Code/225.
As is typical for the digital systems such as DDS and DFT, all the considerations above are independent of the physical frequency. According to the datasheet, the accumulator increments every fourth cycle of the clock oscillator (internal or external) and thus the system physical frequency is (fClk/4)(Frequency Code/227)=fClk·Frequency Code/229, where fClk is the clock oscillator frequency. In the interest of clarity, the experimental results are presented with the reference to the Frequency Code, as it is easy to convert back and forth between the latter and either the normalized frequency f or physical frequency based on the source of system clock.
The characteristic feature of the AD5933 not explicitly mentioned in the datasheet is that the substantial DC offset is always present at the input of the DFT detector. The datasheet [
To observe the effect of this DC leakage experimentally it is sufficient to disconnect everything, except the feedback resistor, from the pin 5. This turns the internal amplifier circuit of the receiving stage into a voltage follower that passes VDD/2 to the ADC input. The exact value of the feedback resistor is not important in these measurements, but the feedback resistor Rfb of 200 kΩ was utilized. Then a sweep can be performed by programming the AD5933 with the parameters shown in Table 1 (as referred to in the datasheet).
To distinguish experimental data from the correspondent identifiers SI and SQ in the expressions, the internal DC leakage data collected from the AD5933 output registers is designated as ΔRe and ΔIm respectively.
The “Real” and “Imaginary” data behave predominantly as predicted by the formulae (2) for ΔI and ΔQ respective gain factors GI and GQ in the range of f from 0 to 2/N corresponding to Frequency Code from 0 to 80000 (
The above experiments can be easily reproduced at higher frequencies to observe that the error from the DC leakage decreases further, but still stays rather prominent in comparison to intrinsic system inaccuracies, noise and interference at all frequencies within the advertised operating frequency range. The calibration method recommended in the datasheet aims to correct only for multiplicative gain and the resulting accuracy suffers greatly from this DC leakage systematic error, which is additive in nature. Narrowing the frequency range, assuming the gain linearly changing across the sweep and using multi-point calibration as advised do not help much, as the DC leakage error oscillates with the frequency.
To remove the effects of the DC leakage the following steps have to be taken:
The additional benefit of this method is that, due to additive nature of the DFT, other errors that are stable in time will all be subtracted from the signal of interest.
A simplified schematic for performing the proposed procedure for the network analysis—the intended purpose of AD5933—is illustrated in (
Depending on the specific nature of the DUT, it may also transfer some or all of the DC component of the excitation voltage from pin 6 (VOUT) to VIN node, so care must be taken to block this DC.
Similarly, a simplified schematic for performing the proposed procedure for measuring the external signal is illustrated on (
The expressions (1) and experiments identified the frequency ranges, where the DFT detector produces substantial gains for DC leakage, both in “Real” (in-phase) and “Imaginary” (quadrature) data. A single frequency measurement within such frequency range is sufficient to obtain the accurate value of a DC signal.
A simplified schematic for performing the procedure is shown in (
The procedure is as follows:
Equivalently, this method can be practiced with the real register data at frequency codes that correspond to acceptable gain values. Using data at a single frequency point from a single data register constitutes a minimalistic version of this method, but the data from one or both real and imaginary registers at a single frequency or multiple frequencies, or data from a whole frequency sweep within suitable range, can be utilized to arrive at the DC signal value. While these versions of the proposed method may provide somewhat better statistics, additional measurement time and processing may prove to produce diminishing returns and have to be tailored to the application-specific requirements.
The methods and the schematics in (
It has been noted earlier that the practical implementation of the DFT in AD5933 inverts the sign of the inner product of the sampled input and the sine test vector. Also, to the contrary of what is reported in the literature, AD5933 outputs the excitation voltage in a form of a sine wave and not the cosine as is customary in the DFT textbooks. To account for these two particularities it makes sense to designate the data produced by the AD5933 as SR, and SIm to distinguish these from the correspondent identifiers SI and SQ introduced earlier and the matrix expression now takes a different form:
Still, the AC leakage errors can be eliminated by solving the system of linear equations for A Cos(φ) and A Sin(φ), which yields the following:
Detailed derivation of the above expressions accounting for AD5933-specific operation is given in (38) Matsiev, L. Improving Performance and Versatility of Systems Based on Single-Frequency DFT Detectors such as AD5933. Electronics 2015, 4, 1-34.
Also, in AD5933 the DFT results are held in the 16-bit “Real” and “Imaginary” registers, which can hold values between 0 and 216−1 only and, as it was mentioned earlier, may overflow. The datasheet does not mention any hardware means to flag this condition and the software provided with the evaluation board offers no means of detecting and correcting the overflow.
The proposed method allows for easy overflow identification and correction by comparing the sign of the collected data to the one predicted by expressions (1) and (3). In the experiments below, when the overflow occurs, the sign of the overflown data turns negative—the opposite of what is predicted by the theory and such data can be corrected by simply adding 216 to it.
To experimentally observe the effects of DFT low-frequency behavior discussed in the theoretical section, after recording the DC leakage sweep with the feedback resistor Rfb of 200 kΩ as explained in the previous section (please see (
The output data “Re” and “Im” collected from the “Real” and “Imaginary” registers is corrected for the fixed-point overflow and ΔRe and ΔIm the DC leakage sweep recorded earlier—is also subtracted. The resulting data SRe=Re−ΔRe and SIm=Im−ΔIm is plotted on (
To process the experimental data shown on (
The experimental data processing steps according to the invented method are illustrated in Table 3, where the first column is Frequency Code, second and third columns are the internal DC leakage, fourth and fifth columns are the raw AC response of the resistor, sixth and seventh columns—DC leakage is subtracted, eighth through tenth are the coefficients a, b and d and eleventh and twelfth are the in-phase and quadrature current through the test resistor corrected for both DC and AC leakage. Five sequential frequency points are shown at the beginning, five—in the middle and five—at end of the sweep
The frequency response of an ideal resistor measured by an ideal network analyzer is supposed to consist of a frequency-independent in-phase component and a zero quadrature component. (
It can be seen that after the processing the in-phase component is much larger than the quadrature one and predominantly constant with the frequency at Frequency Code above about 4000, decreasing sharply at lower Frequency Code values. This means that the applied method allows for complete correction of the DFT leakage errors caused by the discontinuous phasor. Below Frequency Code=4000, which corresponds to about 120 Hz at 16 MHz system clock, the inaccuracy of digital implementation of the DFT becomes prevalent. The quadrature component is close to 0, slowly decreasing into negative values with the increasing frequency. This behavior of the quadrature component is the result of the phase delay caused by the low-pass filter at the input of the ADC, shown on the functional block diagram in the datasheet. This can be easily accounted for and further corrected by applying conventional calibration techniques.
After the additive DC leakage and the AC leakage errors have been eliminated from the raw data by this method, the conventional single-frequency-point calibration and multi-point calibration techniques can be applied and will produce accurate results over a much wider frequency range than when applied to raw data directly. The experimental data indicates that at 16 MHz system clock without any additional hardware the proposed method allows the expansion of the usable operational frequency range down to ˜100 Hz, enabling a very cost-efficient access to the frequencies two decades below 10 KHz. In the range above 10-20 KHz the DC and AC leakage errors do decrease and for certain low-dynamic range and narrow-frequency applications the AD5933 may deliver adequate results as is, but the proposed method enables a far superior performance at all frequencies, pushing the accuracy to the to the maximum that can be achieved by the device.
It should be noted that the expressions (1) through (3) are agnostic to the Nyquist frequency and allow for correct recovery of undersampled input signals. As it was mentioned earlier, the sampling of the input (and also the test phasor) takes place every 4 accumulator increments, so the excitation voltage is digitally synthesized at a sampling rate 4 times higher than the sampling rate of the input and, while the input may be undersampling, the excitation signal still satisfies Nyquist criterion. Notwithstanding the high-frequency input signal suppression by the low pass filter in the AD5933, signals at frequencies up to approximately 950 KHz can be measured and processed using this method, which allows to operate the AD5933 over nearly four-decade frequency range.
Skilled in the art would appreciate that the same methods and systems can be implemented using different hardware, for example ADuCM350 system-on-a-chip or DSP-based and FPGA-based systems for frequency synthesis, signal digitization and processing.
The various examples of the systems and methods around the use of AD5933 device described herein are representative of, and not to be considered limiting of the inventions disclosed and claimed herein.
The present application is related to U.S. provisional application: Ser. No. 62/046,732 filed on Sep. 5, 2014 by Leonid Matsiev.
| Number | Date | Country | |
|---|---|---|---|
| 62046732 | Sep 2014 | US |
