J. Garofalo et al., Automatic Proximity Correction for 0.35 /spl mu/m I-line Photolithography, International Workshop on Numerical Modeling of Processes and Devices for Integrated Circuits, pp. 92-94, Jun. 1994.* |
O.W. Otto et al., Automated Optical Proximity Correction—A Rules-Based Approach, SPIE vol. 2197, pp. 278-293, Jan. 1994.* |
OPRX at SPIE94. [online]. Trans Vector Technologies Corporation, 1994 [retrieved on Jan. 24, 2000]. Retrieved from the Internet: http://www.tvt.com/spie94/SPIE94_1.html, Jan. 1994.* |
Simrule at Bacus95, [online]. Trans Vector Technologies Corporation, 1994 [retrieved on Jan. 14, 2000]. Retrieved from the Internet: http://www.tvt.com/spie95, Jan. 1995.* |
Graphical Examples for OPRX at SPIE94. [online]. Trans Vector Technologies Corporation, 1994 [retrieved on Jan. 21, 2000]. Retrieved from the Internet: http://www.tvt.com/html/graphic-examples.html, Jan. 1995.* |
LayerOps: Hierarchical Layer-to-Layer Operations in OPRX. [online]. Trans Vector Technologies Corporation, 1994 [retrieved on Jan. 14, 2000]. Retrieved from the Internet: http://www.tvt.com/, Jan. 1994.* |
OPRX at SPIE Micro95. [online]. Trans Vector Technologies Corporation, 1994 [retrieved on Jan. 14, 2000]. Retrieved from the Internet: http://www.tvt.com/spie95, Jan. 1995.* |
Trans Vector Technologies Feature Product Sheet. [online]. Trans Vector Technologies Corporation, 1994 [retrieved on Jan. 14, 2000]. Retrieved from the Internet: http://www.tvt.com, Jan. 1994.* |
Feature Overview of OPRX, [online]. Trans Vector Technologies Corporation, 1994 [retrieved on Jan. 21, 2000]. Retrieved from the Internet: http://www.tvt.com/, Jun. 1994.* |
OPRX Product Manual, Trans Vector Technologies. [On Order], Jan. 1994.* |
R. Socha, A. Wong, M. Cagan, Z. Krivokapic and A. Neureuther, “Effects of Wafer Topography on the Formation of Polysilicon Gates”, Dept. of Elec. Eng. and Computer Science, University of Berkeley, SPIE vol. 2440/361. |
John Stirniman and Michael Rieger, “Optimizing Proximity Correction for Wafer Fabrication Processes,” SPIE, vol. 2322, Photomask Technology and Management, XP 000607940, 1994. |
R.C. Henderson and O.W. Otto, “CD data requirements for proximity effect corrections,” SPIE, vol. 2322, Photomask Technology and Management, XP 000607939, 1994. |
E. Barouch, et al., OPTIMASK: an OPC Algorithm for Chrome and Phase-Shift Mask Design, SPIE, vol. 2440, pp. 192-206, Feb. 22-24, 1995, XP002101266. |
H. Futatsuya, et al., “Practical Method of Evaluating Two Dimensional Resist Features for LIthographic DRC,” SPIE, vol. 3051, pp. 499-508, Mar. 12-14, 1995, XP002101267. |
Yamada Akito, “Verifying Method for Layout Data of Semiconductor Device,” Patent Abstracts of Japan, vol. 018, No. 416, Aug. 4, 1994 and JP 06 125007 A, May 6, 1994, abstract. |
S. Kyosuke, “Method and Device for Layout Verification,” Patent Abstracts of Japan, vol. 018, No. 346, , Jun. 29, 1994, and JP 06 83906 A, Mar. 25, 1994, abstract. |
K. Kazuhiro, “LSI Layout Pattern Data Checking Apparatus,” Patent Abstracts of Japan, vol. 016, No. 271, Jun. 18, 1992 and JP 04 063460A, Feb. 28, 1992, abstract. |
F. Takeshi, “Layout Pattern Design Reference/Verification Rule Preparation Supporting Method and System Therefor,” Patent Abstracts of Japan, vol. 098, No. 003, Feb. 27, 1998, and JP 09 288686 A, Nov. 4, 1997. |
M. Takashi, “Layout Verification Method and Device,” Patent Abstracts of Japan, vol. 097, No. 010, Oct. 31, 1997 and JP 09 148441 A, Jun. 6, 1997. |
U. Kazutaka, “Layout Editing Method,” Patent Abstracts of Japan, vol. 097, No. 006, Jun. 30, 1997 and JP 09 044535 A, Feb. 14, 1997, abstract. |
T. Yasuko, “Design Rule Check Execution Device,” Patent Abstracts of Japan, vol. 095, No. 004, May 31, 1995 and JP 07 021239, Jan. 24, 1995. |
I. Hiroshi, “Layout Pattern Inspection Rule Generation System,” Patent Abstracts of Japan, vol. 016, No. 205, May 15, 1992, and JP 04 033168 A, Feb. 4, 1992, abstract. |