Embodiments of the present invention may relate to the field of microprocessor design and testing, and more specifically to a persistent cacheable high volume manufacturing initialization code.
High volume manufacturing (HVM) test costs are highly dependent on the amount of time necessary to run a multitude (typically thousands) of tests to validate all aspects of the microprocessor. Between tests it is necessary to re-initialize the microprocessor to a known state so that subsequent tests may yield an expected result provided that the microprocessor is functioning properly. As the number of required tests increases, the amount of time needed to load and run initialization code becomes non-trivial.
Embodiments of the present invention may become apparent from the following detailed description of arrangements, example embodiments, and the claims when read in connection with the accompanying drawings. While the foregoing and following written and illustrated disclosure focuses on disclosing arrangements and example embodiments of the invention, it should be clearly understood that the same is by way of illustration and example only and embodiments of the invention are not limited thereto.
The following represents brief descriptions of the drawings in which like reference numerals represent like elements and wherein:
In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the invention. It will be apparent, however, to one skilled in the art that embodiments of the invention can be practiced without these specific details. In other instances, structures and devices are shown in block diagram form in order to avoid obscuring the invention.
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments.
Microprocessor 102 may represent any of a wide variety of control logic including, but not limited to one or more of a microprocessor, a programmable logic device (PLD), programmable logic array (PLA), application specific integrated circuit (ASIC), a microcontroller, and the like, although the present invention is not limited in this respect. In one embodiment, microprocessor 102 is an Intel® compatible processor. Microprocessor 102 may have an instruction set containing a plurality of machine level instructions that may be invoked, for example by an application or operating system. Microprocessor 102 may include elements as described in greater detail in regards to
Memory controller 104 may represent any type of chipset or control logic that interfaces system memory 106 with the other components of electronic appliance 100. In one embodiment, a link which communicatively couples microprocessor 102 and memory controller 104, may be a high speed/frequency serial link such as Intel® QuickPath Interconnect. In another embodiment, memory controller 104 may be incorporated along with microprocessor 102 into an integrated package.
System memory 106 may represent any type of memory device(s) used to store data and instructions that may have been or will be used by microprocessor 102. Typically, though the invention is not limited in this respect, system memory 106 will consist of dynamic random access memory (DRAM). In one embodiment, system memory 106 may consist of Rambus DRAM (RDRAM). In another embodiment, system memory 106 may consist of double data rate synchronous DRAM (DDRSDRAM).
Input/output (I/O) controller 108 may represent any type of chipset or control logic that interfaces I/O device(s) 112 with the other components of electronic appliance 100. In one embodiment, I/O controller 108 may be referred to as a south bridge. In another embodiment, I/O controller 108 may comply with the Peripheral Component Interconnect (PCI) Express™ Base Specification, Revision 1.0a, PCI Special Interest Group, released Apr. 15, 2003 and/or other revisions.
Network controller 110 may represent any type of device that allows electronic appliance 100 to communicate with other electronic appliances or devices. In one embodiment, network controller 110 may comply with a The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 802.11b standard (approved Sep. 16, 1999, supplement to ANSI/IEEE Std 802.11, 1999 Edition). In another embodiment, network controller 110 may be an Ethernet network interface card.
Input/output (I/O) device(s) 112 may represent any type of device, peripheral or component that provides input to or processes output from electronic appliance 100.
Processing unit(s) 202 represent the logical and functional elements of microprocessor 102. In some examples, processing units(s) 202 may include processor cores, floating point units, controllers, registers, pointers, etc.
Unified cache 204 represents a level of cache accessible by processing unit(s) 202. In one embodiment, unified cache 204 represents a level two cache. Unified cache 204 may include elements as described in greater detail in regards to
System interface 208 provides a communication connection between microprocessor 102 and other components, for example components of electronic appliance 100 or a test fixture (not shown).
Signature output 210 may provide a status or result from processing unit(s) 202 after tests have been executed. In one embodiment, tester 212 may be coupled with signature output 210 (and/or system interface 208) to functionally test microprocessor 202 by comparing the output to an expected result as part of a HVM testing process, for example as described in regards to
The method continues with masking for (515) and executing initialization code 406 to initialize processing unit(s) 202 and then masking for (520) and executing test code 408 to test processing unit(s) 202. Depending on whether more occurrences of test code 408 need to be run the method may return to 510 or may continue with comparing (525) signature output 210 to an expected result to determine if the device under test has passed. If more testing is needed the method may return to 510 or may finish with blowing (530) fuses 306 to permanently disable control register 304, if so desired.
Although embodiments of the present invention have been described with reference to a number of illustrative embodiments thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this invention. More particularly, reasonable variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the foregoing disclosure, the drawings and the appended claims without departing from the spirit of the invention. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.
Number | Date | Country | |
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Parent | 12560589 | Sep 2009 | US |
Child | 14171522 | US |