Patent Application
20170254841
The present disclosure relates generally to alternating current (AC) circuits, and in particular to phase angle measurements between AC signals.
The measurement of alternating current (AC) power and impedance in an AC system is often made for various reasons. AC power and/or impedance may be measured or otherwise determined in order to improve power transfer efficiency (e.g., inductance switching) in the AC system.
Merely as an illustrative example, consider a wireless power transfer system. A power transmitting unit may include a transmit coil that can be driven by an AC current to generate a magnetic field. A power receiving unit (e.g., a smartphone, a wearable device, etc.) may include a receive coil that can magnetically couple to the magnetic field to receive power wirelessly when placed on the charging surface of the power transmitting unit. AC power and/or impedance measurements may be used to provide protective measures such as cross connection prevention, overload protection of the power amplifier, detection of foreign objects, and so on.
AC power and/or impedance measurements may be used to detect operating conditions in the AC system. In the wireless power transfer example, for instance, AC power and/or impedance measurements may be used to detect the presence of a power receiving unit on the charging surface, provide reverse in-band signaling, detect state machine transitions, and so on.
The measurement of alternating current (AC) power and impedance in an AC system typically requires determining the phase difference (phase angle) between AC voltage and AC current.
In accordance with the present disclosure, a method may include generating a first signal representative of an alternating current (AC) voltage signal and generating a second signal representative of an AC current signal. The first and second signals may be combined with a clock signal to produce a third signal. Phase angle information representative of a phase angle between the AC voltage signal and the AC current signal may be produced based on a pulse count indicative of how many pulses occur in the third signal over a predetermined period of time.
In some aspects, generating the first signal and the second signal may include producing respectively a first square wave from the AC voltage signal and a second square wave from the AC current signal.
In some aspects, combining the first and second signals with a clock signal may include logically AND'ing together the first signal, the second signal, and the clock signal.
In some aspects, combining the first and second signals with a clock signal may include combining the first and second signals to produce a combined signal and combining the combined signal with the clock signal. In some aspects, combining the first and second signals may include logically AND'ing together the first and second signals.
In some aspects, the method may further comprise providing the phase angle information to a controller in a wireless power transmitting device. The AC voltage signal and the AC current signal may be produced in the wireless power transmitting device.
In some aspects, the method may further comprise determining a sign of the phase angle based only on the first signal and the second signal.
In some aspects, producing phase angle information may include accessing data in a data table using the pulse count and determining the phase angle using the accessed data.
In some aspects, producing phase angle information may include evaluating a relationship between phase angle and the number pulses that occur in the third signal over the predetermined period of time.
In some aspects, the accuracy of the phase angle is independent of a frequency of the clock signal.
In accordance with the present disclosure, a method may include generating a first square wave signal representative of an AC voltage signal and generating a second square wave signal representative of an AC current signal. The method may further include generating a third square wave signal by combining at least the first square wave signal and the second square wave signal. A phase angle between the AC voltage signal and the AC current signal may be determined based on how many pulses occur in the third square wave in a predetermined period of time.
In some aspects, the method may further include determining a sign of the phase angle based only the first square wave signal and the second square wave signal.
In some aspects, determining the phase angle may be based on data obtained from accessing a data table using the number of events that occur in the predetermined period of time.
In some aspects, determining the phase angle may include evaluating a relationship between phase angle and the number of events that occur in the predetermined period of time.
In some aspects, the method may further include logically AND'ing together the first square wave signal, the second square wave signal, and a clock signal to produce a third square wave signal. The phase angle may be based on the number of pulses in the third square wave signal during the predetermined period of time.
In some aspects, the method may further include logically AND'ing together the first square wave signal and the second square wave signal to produce an intermediate square wave signal and combining the intermediate square wave signal with a clock signal to produce the third square wave signal.
In accordance with the present disclosure, a circuit may include a first circuit configured to generate a first signal representative of an AC voltage signal. A second circuit may be configured to generate a second signal representative of an AC current signal. A third circuit may be electrically connected to the first and second circuits and configured to combine the first and second signals with a clock signal to produce a third signal. The circuit may include a counter electrically connected to the third circuit and configured to produce a pulse count representative of a number of pulses occurring in the third signal over a predetermined period of time. A computing circuit may be electrically connected to the counter and configured to produce phase angle data representative of a phase angle between the AC voltage signal and the AC current signal using the pulse count.
In some aspects, the first circuit may be a comparator configured to receive the AC voltage signal and produce a first square wave signal therefrom. The second circuit may be a comparator configured to receive the AC current signal and produce a second square wave signal therefrom. In some aspects, either the first comparator or the second comparator may be further configured to produce an inverted square wave.
In some aspects, the third circuit may be an AND gate, the first and second signals may be electrically connected to respective first and second inputs of the AND gate. The clock signal may be provided to a third input of the AND gate. The third signal may be an output of the AND gate.
In some aspects, the third circuit may comprise an AND gate configured to logically AND together the first and second signals to produce an AND'd output and a D-type flip flop electrically connected to the AND gate to receive the AND'd output. The D-type flip flop may have a clock input configured to receive the clock signal. The D-type flip flop may be configured to produce the third signal.
In some aspects, the circuit may further include a fourth circuit electrically connected to the first and second circuits and configured to produce a signal indicative of whether the AC voltage signal leads or lags the AC current signal.
In some aspects, the circuit may further include a memory. The computing circuit may comprise a digital processor configured to access data from the memory using the pulse count and to produce the phase angle data using the data accessed from the memory.
In some aspects, the computing circuit may comprise a digital processor configured to generate the phase angle data using a relationship between the phase angle and the number of pulses that occur in the third signal over the predetermined period of time.
In accordance with the present disclosure, a circuit may include means for generating a first square wave signal representative of an AC voltage signal, means for generating a second square wave signal representative of an AC current signal, means for generating a third square wave signal from the first square wave, the second square wave, and a clock signal, and means for producing phase angle data based on a number of pulses that occur in the third square wave signal in a predetermined period of time.
In some aspects, the circuit may further include means for counting the number of pulses in the third square wave signal that occur during the predetermined period of time. The means for counting may be configured to provide the number of pulses counted to the means for producing.
The following detailed description and accompanying drawings provide a better understanding of the nature and advantages of the present disclosure.
With respect to the discussion to follow and in particular to the drawings, it is stressed that the particulars shown represent examples for purposes of illustrative discussion, and are presented in the cause of providing a description of principles and conceptual aspects of the present disclosure. In this regard, no attempt is made to show implementation details beyond what is needed for a fundamental understanding of the present disclosure. The discussion to follow, in conjunction with the drawings, makes apparent to those of skill in the art how embodiments in accordance with the present disclosure may be practiced. In the accompanying drawings:
In the following description, for purposes of explanation, numerous examples and specific details are set forth in order to provide a thorough understanding of the present disclosure. It will be evident, however, to one skilled in the art that the present disclosure as expressed in the claims may include some or all of the features in these examples, alone or in combination with other features described below, and may further include modifications and equivalents of the features and concepts described herein.
In some embodiments, one or more interface circuits 14, 16 may be used to filter or otherwise condition the respective sensed AC voltage and AC current signals 112, 114. For example, the signal sensed at location A (and/or location B) may contain harmonic content, which can negatively affect the detection of phase angle. Accordingly, in some embodiments, the interface circuits 14, 16 may include filters to filter out the undesired harmonics to produce suitable AC voltage and AC current signals 112, 114, respectively. In some embodiments, the interface circuits 14, 16 may include amplification circuits to boost the sensed signals to adequate levels. In other embodiments, the interface circuits 14, 16 may include any suitable circuitry to otherwise “clean up” the signals sensed at respective locations A and B, to produce respective AC voltage and AC current signals that can be processed in accordance with the present disclosure.
A phase angle detector 102 in accordance with the present disclosure may receive the AC voltage signal 112 and the AC current signal 114. The phase angle detector 102 may produce or otherwise generate phase angle information representative of the phase difference (commonly expressed as phase angle) between the AC voltage signal 112 and the AC current signal 114. In some embodiments, the phase angle information may be digital (e.g., a signed number). In other embodiments, the phase angle information may be analog (e.g., a plus or minus voltage level). In still other embodiments, the phase angle detector 102 may provide phase angle information using both digital and analog formats.
The AC circuitry 12 may receive the phase angle information to control some of its operations. Reference is made to
The front-end circuit 36 may include a filter circuit configured to filter out harmonics or other unwanted frequencies. The front-end circuit 36 may include a matching circuit configured to match the impedance of the transmitter 22 to the impedance of the power transmitting element 52. The front-end circuit 36 may include a tuning circuit (not shown) to create a resonant circuit with the power transmitting element 52. As a result of driving the power transmitting element 52, the power transmitting element 52 may generate a wireless field 56 to wirelessly output power at a level sufficient for charging a battery 62, or otherwise powering a load.
The transmitter 22 may further include a controller 38 operably coupled to the transmit circuitry 24 and configured to control one or more aspects of the transmit circuitry 24, or accomplish other operations relevant to managing the transfer of power. The controller 38 may be a micro-controller or a processor. The controller 38 may be implemented as an application-specific integrated circuit (ASIC). The controller 38 may be operably connected, directly or indirectly, to each component of the transmit circuitry 24. The controller 38 may be further configured to receive information from each of the components of the transmit circuitry 24 and perform calculations based on the received information. The controller 38 may be configured to generate control signals (e.g., signal 33) for each of the components that may adjust the operation of that component. As such, the controller 38 may be configured to adjust or manage the power transfer based on a result of the operations performed by it. The transmitter 22 may further include a memory (not shown) configured to store data, for example, such as instructions for causing the controller 38 to perform particular functions, such as those related to management of wireless power transfer.
The receiver 26 (also referred to herein as power receiving unit, PRU) may include receive circuitry 28 that may include a front-end circuit 42 and a rectifier circuit 44. The front-end circuit 42 may include matching circuitry configured to match the impedance of the receive circuitry 28 to the impedance of the power receiving element 54. The front-end circuit 42 may further include a tuning circuit (not shown)to create a resonant circuit with the power receiving element 54. The rectifier circuit 44 may generate a DC power output from an AC power input to charge the battery 62, as shown in
The receiver 26 may be configured to determine whether an amount of power transmitted by the transmitter 22 and received by the receiver 26 is appropriate for charging the battery 62. In certain embodiments, the transmitter 22 may be configured to generate a predominantly non-radiative field with a direct field coupling coefficient (k) for providing energy transfer. Receiver 26 may directly couple to the wireless field 56 and may generate an output power for storing or consumption by a battery (or load) 62 coupled to the output or receive circuitry 28.
The receiver 26 may further include a controller 46 configured similarly to the transmit controller 38 as described above for managing one or more aspects of the wireless power receiver 26. The receiver 26 may further include a memory (not shown) configured to store data, for example, such as instructions for causing the controller 46 to perform particular functions, such as those related to management of wireless power transfer.
Referring to
The transmitter 22 may include a phase detector 102 (
In other embodiments, the phase detector 102 may be provided in the receiver 26, for example, to determine AC power or impedance, or for other reasons.
The phase angle detector 102 may include a 3-input AND gate 212. The outputs C0 and C1 of respective zero crossing detectors 202, 204 may be provided to two respective inputs of the AND gate 212. The third input of AND gate 212 may receive a clock signal fOSC from a clock 200.
In some embodiments, the clock 200 may be a component in the phase angle detector 102. In other embodiments, the clock 200 may be a component separate from the phase angle detector 102. In some embodiments, the clock 200 may be a system clock used in the system 10 (
The phase angle detector 102 may include a counter 214. The output P of AND gate 212 may be a square wave, representing the logical AND of the square waves C0, C1, and clock signal fOSC. The output P may be provided to the counter 214. The counter 214 may count the number of pulses in output P. In some embodiments, the counter 214 may count on the rising edges of the pulses in output P. In other embodiments, the counter 214 may count on the falling edges of the pulses in output P. As discussed below, output P may be referred to as an “event signa.”
The phase angle detector 102 may include a processor 222. The processor 222 may be any suitable processing unit, such as but not limited to, a general purpose central processing unit (CPU), a microcontroller, a digital signal processor (DSP), and the like. The output of counter 214 may be provided as a data input to the processor 222. The processor 222 may output a signal to a RESET input on the counter 214 after a predetermined period of time. In accordance with the present disclosure, the processor 222 may use the number of pulses counted by the counter 214 (pulse count) during the predetermined period of time to produce phase angle information indicative of the phase angle between the AC voltage signal 112 and the AC current signal 114. In some embodiments, one or more data tables 224 (e.g., stored in a memory 226) may be used to translate or map the pulse count to another data format in order to represent phase angle in a more suitable format. In other embodiments, the pulse count may be converted to an analog signal (e.g., voltage level or a current level) that represents phase angle.
The phase angle detector 102 may include a lead-lag indicator. In some embodiments, the lead-lag indicator may comprise a D-type flip flop 232. The output C1 of zero crossing detector 204 may be provided to the D input of the D-type flip flop 232. The output C0 of zero crossing detector 202 may be provided to the clock input of the D-type flip flop 232. The SET and CLR (reset) inputs may be held LO so that the D input is copied to the output Q on the rising edges in C0.
The output Q of the D-type flip flop 232 may indicate whether the AC voltage signal 112 leads or lags the AC current signal 114. In the configuration shown in
It can be seen from
It was further observed that the accuracy in the phase angle determination was not coupled to the frequency of clock signal fOSC. In other words, accuracy in the determination of phase angle in accordance with the present disclosure may be independent of the clock frequency. Instead, accuracy may be a function of the event signal such as output P of AND gate 212. In particular, it was discovered that counting pulses in the event signal over a longer period of time can increase the accuracy of the phase angle determination. In a particular embodiment, for example, phase angle was determined with an accuracy better than 1% when more than 150 pulses in the event signal were counted. Accordingly, the accuracy of a phase angle can be determined in accordance with the present disclosure without having to increase the clock signal frequency.
Merely to illustrate the point and to provide a sense of the time scales for some embodiments in accordance with the present disclosure, the AC voltage and AC current signals 112, 114 may be 6.78 MHz signals (e.g., for a wireless power transfer system). The clock signal fOSC, however, may be a 32 MHz clock signal. The predetermined period of time for counting pulses by the counter 214, in some embodiments for example, may be in the range 5-10 μS. It will be appreciated, of course, that the AC voltage and AC current signals 112, 114 may be at a frequency other than 6.78 MHz, that a clock frequency other than 32 MHz may be used, and other periods of time may be used to count pulses.
In accordance with the present disclosure, the voltage square wave 302 may be combined with the current square wave 304 to produce a phase angle square wave 306 that represents the phase angle between the AC voltage signal 112 and the AC current signal 114. In some embodiments, for example, the voltage square wave 302 may be AND'd with the current square wave 304 to produce the phase angle square wave 306. As can be seen in
In accordance with the present disclosure, an events square wave 308 may be generated that represents crossing events between the phase angle square wave 306 and the clock signal fOSC. More particularly, in some embodiments, pulses in the events square wave 308 represent crossing events when both the phase angle square wave 306 and the clock signal fOSC are HI.
In some embodiments, the events square wave 308 may be generated by combining together the AC voltage square wave 302, the AC current square wave 304, and the clock signal fOSC. Referring to
In some embodiments, the phase angle detector 102 (e.g.,
The phase angle detector 402 may include a D-type flip flop 406. The output of AND gate 404 may be provided to the D input of the D-type flip flop 406, and the clock signal fOSC may clock the D-type flip flop 406. The output Q of the D-type flip flop 406 may represent an events square wave (e.g., 308,
The counter 214 may count the number of pulses in the output Q of the D-type flip flop 406. The output of counter 214 may be provided as an input to processor 222. In accordance with the present disclosure, the processor 222 may use the number of pulses counted by the counter 214 for a predetermined period of time (referred to herein as “pulse count”) to produce phase angle information indicative of the phase angle between AC voltage signal 112 and AC current signal 114. This aspect of the present disclosure will now be discussed.
It was discovered that pulse count can vary linearly with the phase angle between the AC voltage and AC current signals 112, 114. For example, the pulse count may vary from a minimum (MinCount) when the AC voltage and AC current signals 112, 114 are 90° out of phase to a maximum (MaxCount) when the AC voltage and AC current signals 112, 114 are in phase) (0°) in a linear manner. Accordingly, for a given pulse count C, a phase angle φ1 or φ2 may be obtained using the graph shown in
The relationship shown in
It was noted that the accuracy of the phase angle determination may be improved by counting pulses over a longer period of time. This increased the number of pulses counted; counting more pulses may improve accuracy, without having to increase the clock frequency of the clock signal, e.g., fOSC. Merely to illustrate the point, it was observed that counting at least 150 pulses can provide an accuracy of about 1%. Accordingly, in some embodiments, a time period for counting may be selected so that at least N pulses are counted during that time period. Increasing the time period for counting may increase accuracy.
The graph shown in
In some embodiments, the pulse count may be a signed value. A positive pulse count may indicate that the AC voltage signal 112 lags the AC current signal 114, while a negative pulse count may indicate that the AC voltage signal 112 leads the AC current signal 114. The graph shown in
The relationships shown in
At block 708, the pulse count read out of counter 214 at block 706 may be used to determine a phase angle representative of the phase difference between the AC voltage signal 112 and the AC current signal 114. In some embodiments, the relationship (e.g.,
In some embodiments, the relationship (e.g.,
count=m602×φ+MaxCount1, Eqn. 1
where count is the measured number of pulses,
count=m604×φ+MaxCount2. Eqn. 2
Accordingly, in some embodiments, block 708 the pulse count read out at block 706 may be used to compute the phase angle using Eqn. 1 or Eqn. 2. A leading phase angle may be computed by the processor 222 using Eqn. 1, while a lagging phase angle may be computed using Eqn. 2. The processor 222 may read in lead/lag information (e.g., from D-type flip flop 232) to determine which equation to use.
In some embodiments, the relationship between pulse count and phase angle may be represented using several line segments, such as shown in
Referring to
In accordance with the present disclosure, the voltage square wave 902 may be combined with the current square wave 904 to produce a phase angle square wave 906 that represents the phase angle between the AC voltage signal 112 and the AC current signal 114. In some embodiments, for example, the voltage square wave 902 may be AND'd with the current square wave 904 to produce the phase angle square wave 906. As can be seen in
By comparison, using the circuit shown in
The above description illustrates various embodiments of the present disclosure along with examples of how aspects of the particular embodiments may be implemented. The above examples should not be deemed to be the only embodiments, and are presented to illustrate the flexibility and advantages of the particular embodiments as defined by the following claims. Based on the above disclosure and the following claims, other arrangements, embodiments, implementations and equivalents may be employed without departing from the scope of the present disclosure as defined by the claims.
