The present invention relates to a phase-locked loop and method with frequency calibration, and more particularly to a phase-locked loop and method with frequency calibration for applying to wireless communication.
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The phase-frequency detector 101 receives a reference signal VREF1 and a feedback signal VDIV1, wherein the reference signal VREF1, has a reference frequency fREF1 and a reference phase ΦREF1, and the feedback signal VDIV1 has a frequency fDIV1 and a phase ΦDIV1. The phase-frequency detector 101 makes a comparison among the frequencies fREF1 and fDIV1, and the phases ΦREF1 and ΦDIV1, for producing a comparison result signal VCOMP1 including information about a difference among the frequencies fREF1 and fDIV1, and the phases ΦREF1 and ΦDIV1.
The charge pump 102 receives the comparison result signal VCOMP1 for producing a current signal ISIG1 corresponding to the difference. The loop filter 103 receives the current signal ISIG1 and converts the current signal ISIG1 for producing a voltage controlled signal VCTRL1.
The voltage controlled oscillator 104 receives the voltage controlled signal VCTRL1 for producing an output signal VOUT1 having a frequency fOUT1, wherein the frequency fOUT1 is proportional to the amplitude of the voltage controlled signal VCTRL1. The frequency-dividing unit 105 receives the output signal VOUT1 and performs a frequency division operation a divisor of which is M for producing the feedback signal VDIV1, wherein the frequency fDIV1 is 1/M times as large as the frequency fOUT1 The output signal VOUT1 is adjusted to stabilize due to the feedback mechanism of the frequency-dividing unit 105.
When the phase-locked loop is applied to a high-speed circuit, the design frequency is often difficult to be predicted due to deviation of the manufacturing process, so that the design difficulty of the voltage controlled oscillator and the frequency-dividing unit is increased. For instance, when the frequencies of the voltage controlled oscillator and the frequency-dividing unit deviate, the produced frequency-divisible range may not smoothly cover the adjustable range of the voltage controlled oscillator, which makes the phase-locked loop unable to be locked.
It is an object of the present invention to provide a phase-locked loop and method with frequency calibration. An adjusting signal is produced by a binary search operation for controlling a controllable capacitor array of an oscillation feedback unit. Therefore, the effect reducing the required time of frequency calibration is accomplished.
It is therefore an aspect of the present invention to provide the phase-locked loop including a phase-voltage conversion unit, a calibration unit, and an oscillation feedback unit. The phase-voltage conversion unit receives a reference signal having a first frequency and a first phase, and a first feedback signal having a second frequency and a second phase, and produces a first adjusting signal based on the first frequency, the second frequency, and a phase difference between the first phase and the second phase. The calibration unit receives the reference signal and the first feedback signal, and produces a second adjusting signal based on a frequency difference between the first frequency and the second frequency through a binary search operation. The oscillation feedback unit receives the first adjusting signal and the second adjusting signal, and has a controllable capacitor array controlled by the second adjusting signal for producing a second feedback signal having a third phase locked to the first phase.
It is therefore another aspect of the present invention to provide the frequency calibration method on a phase-locked loop having a controllable capacitor array. The method includes the following steps. A first adjusting signal is produced based on a first frequency and a first phase of a reference signal, and a second frequency and a second phase of a first feedback signal. A second adjusting signal is produced based on a frequency difference between the first frequency and the second frequency through a binary search operation. An oscillation and a second feedback signal having a third phase locked to the first phase is produced.
The foregoing and other features and advantages of the present invention will be more clearly understood through the following descriptions with reference to the drawings, wherein:
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The present invention will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of preferred embodiments of this invention are presented herein for the purposes of illustration and description only; it is not intended to be exhaustive or to be limited to the precise form disclosed.
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The calibration unit 32 receives the reference signal VREF and the first feedback signal VDIV, and produces a second adjusting signal VADJ2 based on a frequency difference between the frequency fREF of the reference signal VREF and the frequency fDIV of the first feedback signal VDIV through a binary search operation. The oscillation feedback unit 33 receives the first adjusting signal VADJ1 and the second adjusting signal VADJ2, and has a controllable capacitor array 33A controlled by the second adjusting signal VADJ2 for producing a second feedback signal having a phase locked to the phase ΦREF of the reference signal VREF. The second feedback signal is fed back to the phase-voltage conversion unit 31 and the calibration unit 32 and is produced for serving as the first feedback signal VDIV.
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The phase-voltage conversion unit 41 includes a phase-frequency detector 411, a charge pump 412, and a loop filter 413. The phase-frequency detector 411 receives a reference signal VREF and a first feedback signal VDIV, wherein the reference signal VREF has a reference frequency fREF and a reference phase ΦREF, and the first feedback signal VDIV has a frequency fDIV and a phase ΦDIV. The phase-frequency detector 411 makes a comparison among the frequencies fREF and fDIV, and the phases ΦREF and ΦDIV, for producing a comparison result signal VCOMP including information about the frequencies fREF and fDIV, and a phase difference between the phases ΦREF and ΦDIV. The charge pump 412 receives the comparison result signal VCOMP for producing a current signal ISIG. The loop filter 413 receives the current signal ISIG and converts the current signal ISIG for producing a first adjusting signal VADJ1, wherein there is a function relation between the amplitude of the first adjusting signal VADJ1 and quantities of the frequencies fREF and fDIV, and a phase difference between the phase ΦREF and the phase ΦDIV.
The calibration unit 42 includes a frequency detector 421, a lock detector 422, a reset controller 423, and a successive approximation register controller 424. The frequency detector 421 receives the reference signal VREF and the first feedback signal fDIV, and compares the frequency fREF of the reference signal VREF with the frequency fDIV of the first feedback signal VDIV for producing a comparison result signal FDOUT having a frequency difference between the frequency fREF and the frequency fDIV, and denoting the frequency fDIV is greater than or less than the frequency fREF. The lock detector 422 receives the reference signal VREF and the first feedback signal VDIV, and compares the phase ΦREF of the reference signal VREF with the phase ΦDIV of the first feedback signal VDIV for producing a lock result signal LDOUT having a phase difference between the phase ΦREF and the phase ΦDIV, and denoting whether a time difference between the phase ΦREF and the phase ΦDIV is within a predetermined period.
The reset controller 423 receives the reference signal VREF and the lock result signal LDOUT for producing a reset signal VRST based on the reference signal VREF and the lock result signal LDOUT. The reset signal VRST is provided to the successive approximation register controller 424 reset to its initial state by a reset state of the reset signal VRST. The successive approximation register controller 424 has N (N=4 in the present embodiment) shift registers (not shown in
The oscillation feedback unit 43 includes a voltage controlled oscillator 431, a frequency-doubling unit 432, a frequency pre-dividing unit 433, and a frequency-dividing feedback unit 434. The voltage controlled oscillator 431 receives the first adjusting signal VADJ1 for producing a first object signal VVCO having a frequency fVCO depending on the amplitude of the first adjusting signal VADJ1. The frequency-doubling unit 432 receives the first object signal VVCO for producing a second object signal VOUT having a frequency fOUT twice higher than the frequency fVCO of the first object signal VVCO.
The frequency pre-dividing unit 433 receives the first object signal VVCO and pre-divides the frequency fVCO of the first object signal VVCO for producing an intermediate signal VDIV2, wherein a relation of a first division ratio is formed by the frequency fDIV2 of the intermediate signal VDIV2 relative to the frequency fVCO of the first object signal VVCO. The frequency-dividing feedback unit 434 receives the intermediate signal VDIV2 and pre-divides the frequency VDIV2 of the intermediate signal VDIV2 for producing the second feedback signal, wherein a relation of a second division ratio is formed by the frequency of the second feedback signal relative to the frequency fDIV2 of the intermediate signal VDIV2. Besides, the second feedback signal is fed back to the phase-voltage conversion unit 41 and the calibration unit 42 and is produced for serving as the first feedback signal VDIV.
One of the oscillation devices, the voltage controlled oscillator 431, the frequency pre-dividing unit 433, and the frequency-dividing feedback unit 434, includes the controllable capacitor array 43A. When the voltage controlled oscillator 431 includes the controllable capacitor array 43A, the frequency fVCO of the first object signal VVCO further depends on the second adjusting signal VADJ2. As shown in
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Four single-side capacitance values (such as 200f of C30, 100f of C20, 50f of C10, and 25f of C00) of the four capacitor strings 53A3, 53A2, 53A1, and 53A0 form a distribution of geometric series with a common ratio of 2. The most significant bit b3 of the four bits b3, b2, b1, and b0 corresponds to the capacitor string 53A3, having the maximum value (such as 200f of C30) of the four single-side capacitance values (such as 200f of C30, 100f of C20, 50f of C10, and 25f of C00), of the four capacitor strings 53A3, 53A2, 53A1, and 53A0. The least significant bit b0 of the four bits b3, b2, b1, and b0 corresponds to the capacitor string 53A0, having the minimum value (such as 25f of C00) of the four single-side capacitance values (such as 200f of C30, 100f of C20, 50f of C10, and 25f of C00), of the four capacitor strings 53A3, 53A2, 53A1, and 53A0.
When an adjusting sub-signal (such as VB2) of the four adjusting sub-signals VB3, VB2, VB1, and VB0 selects a capacitor string (such as 53A2) corresponding thereto, the frequency of the second feedback signal decreases in comparison with a state of the capacitor string (such as 53A2) when not selected. When the adjusting sub-signal (such as VB2) of the four adjusting sub-signals VB3, VB2, VB1, and VB0 does not select the capacitor string (such as 53A2) corresponding thereto, the frequency of the four adjusting sub-signals increases in comparison with a state of the capacitor string (such as 53A2) when selected.
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When the reference signal VREF leads the first feedback signal VDIV more than the period T or the reference signal VREF lags behind the first feedback signal VDIV more than the period T, the lock result signal LDOUT becomes at a low logical level for denoting the lock result signal LDOUT being in a non-lock state. When the reference signal VREF leads the first feedback signal VDIV less than the period T or the reference signal VREF lags behind the first feedback signal VDIV less than the period T, the lock result signal LDOUT becomes at a high logical level for denoting the lock result signal LDOUT being in a lock state.
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Afterward, the operation of the successive approximation register controller 524 is described in details. The successive approximation register controller 524 performs at most four cycling periods CYC1, CYC2, CYC3, and CYC4 of a binary search operation, and each of the four cycling periods CYC1, CYC2, CYC3, and CYC4 can form the digital adjusting value based on the comparison result signal FDOUT, the lock result signal LDOUT, and the reset signal VRST. When the reset signal VRST is in a reset state, the successive approximation register controller 524 is reset, so that the capacitor string 53A3, corresponding to the most significant bit b3 of the four bits b3, b2, b1, and b0, of the four capacitor strings 53A3, 53A2, 53A1, and 53A0 is selected, and the other three capacitor strings 53A2, 53A1, and 53A0 corresponding to the other three bits b2, b1, and b0 of the four bits b3, b2, b1, and b0 are not selected. When the lock result signal LDOUT is in a non-locked state and the reset signal VRST is inverted to be in a non-reset state, the successive approximation register controller 524 determines whether the four capacitor strings 53A3, 53A2, 53A1, and 53A0 are selected in an order beginning from the most significant bit b3 of the four bits b3, b2, b1, and b0 by the comparison result signal FDOUT and the binary search operation in the four cycling periods CYC1, CYC2, CYC3, and CYC4.
When the lock result signal LDOUT is in the non-locked state and the reset signal VRST is in the non-reset state, the successive approximation register controller 524 selects a capacitor string (such as 53A2) corresponding to each cycling period (such as CYC2) from the four capacitor strings 53A3, 53A2, 53A1, and 53A0 in advance in the each cycling period (such as CYC2) of the four cycling periods CYC1, CYC2, CYC3, and CYC4. After a pre-comparison period of the each cycling period (such as CYC2), when the comparison result signal FDOUT shows that the frequency fDIV of the first feedback signal VDIV is greater than the frequency fREF of the reference signal VREF, the successive approximation register controller 524 confirms having selected the capacitor string (such as 53A2) through a corresponding adjusting sub-signal (such as VB2) thereof. After the pre-comparison period of the each cycling period (such as CYC2), when the comparison result signal FDOUT shows that the frequency fDIV is less than the frequency fREF, the successive approximation register controller 524 confirms no selection of the capacitor string (such as 53A2) through the corresponding adjusting sub-signal (such as VB2) thereof.
When the reset signal VRST is in the non-reset state and the lock result signal LDOUT is inverted to be in a locked state, the successive approximation register controller 524 stops performing the binary search operation and holds four selection states of the four capacitor strings 53A3, 53A2, 53A1, and 53A0. Besides, when the reset signal VRST is in the non-reset state and the four cycling periods CYC1, CYC2, CYC3, and CYC4 end, the successive approximation register controller 524 stops performing the binary search operation and holds the four selection states of the four capacitor strings 53A3, 53A2, 53A1, and 53A0.
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The oscillation feedback unit 63 includes a voltage controlled oscillator 631, and a frequency dividing unit 633. The voltage controlled oscillator 631 receives the first adjusting signal VADJ1 for producing a first object signal VVCO having a frequency fVCO depending on an amplitude of the first adjusting signal VADJ1. The frequency dividing unit 633 receives the first object signal VVCO and dividing the frequency fVCO of the first object signal VVCO for producing the second feedback signal, wherein a relation of a division ratio is formed by the frequency of the second feedback signal relative to the frequency fVCO of the first object signal VVCO. Besides, the second feedback signal is fed back to the phase-voltage conversion unit 41 and the calibration unit 42 and is produced for serving as the first feedback signal VDIV.
One of the oscillation devices, the voltage controlled oscillator 631, and the frequency dividing unit 633 includes a controllable capacitor array 63A. When the voltage controlled oscillator 631 includes the controllable capacitor array 63A, the frequency fVCO of the first object signal VVCO further depends on the second adjusting signal VADJ2. As shown in
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While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.
Number | Date | Country | Kind |
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096135809 | Sep 2007 | TW | national |