Patent Application
20150111372
The present invention generally relates to improved processes for fabricating nanomaterials that may be used in semiconductor devices.
The manufacture of future semiconductors drives the relentless pursuit of new processes and processing materials that facilitate reductions in process cost, increases in processing speed, decreased energy utilization by devices and addressing the challenges presented by each change in scale or node.
Earlier high-volume manufacturing (HVM) techniques that facilitated decreased production costs and increased processing speed are not expected to be viable as the size of semiconductor devices and their inherent architecture decrease below the 22 nm node.
In several peer-reviewed publications Javey and his coworkers articulate ideas about the self-assembly of phosphorus and boron monolayers on hydrogen-terminated silicon surfaces (HtermSi or Ht—Si). These reactions require a long exposure time (>2 hrs.), high temperatures (>100° C.) and dopants and solvents that are typically costly to purify. Any one of the aforementioned parameters would present a challenge to adoption of the process to high-volume manufacturing (HVM). However, the combination of parameters creates a much larger challenge and drives the rethinking of published approaches to self-assembled monolayers (SAMs) on Ht—Si.
Thus, a need exists for improved processes that provide advancements toward the formation of nanomaterials that may be used in semiconductor devices.
While certain aspects of conventional technologies have been discussed to facilitate disclosure of the invention, Applicants in no way disclaim these technical aspects, and it is contemplated that the claimed invention may encompass one or more of the conventional technical aspects discussed herein.
In this specification, where a document, act or item of knowledge is referred to or discussed, this reference or discussion is not an admission that the document, act or item of knowledge or any combination thereof was, at the priority date, publicly available, known to the public, part of common general knowledge, or otherwise constitutes prior art under the applicable statutory provisions; or is known to be relevant to an attempt to solve any problem with which this specification is concerned.
Briefly, the present invention satisfies the need for improved processes for fabricating nanomaterials that may be used in semiconductor devices. More particularly, the invention provides improved methods for SAM on Ht—Si for HVM. The present invention may address one or more of the problems and deficiencies of the art discussed above. However, it is contemplated that the invention may prove useful in addressing other problems and deficiencies in a number of technical areas. Therefore, the claimed invention should not necessarily be construed as limited to addressing any of the particular problems or deficiencies discussed herein.
In one aspect, the invention provides a method for preparing a doped silicon material, said method comprising:
In another aspect, the invention provides a method for making an n-region in a semiconductor comprising:
In another aspect, the invention provides a method for selection of phosphorus-containing and arsenic-containing materials, e.g., for the two aspects described above. This aspect broadens the scope of phosphorus-containing and arsenic-containing materials available to the practitioner of this art. This aspect also facilitates the time-effective screening of phosphorus-containing and arsenic-containing compounds for the practitioner.
The present invention is generally directed to improved processes for fabricating nanomaterials that may be used in semiconductor devices. More particularly, the invention provides improved processes for creating phosphorus and/or arsenic monolayers on silicon material substrates. The monolayers may be annealed to dope the surface of semiconductor materials.
Although this invention is susceptible to embodiment in many different forms, certain embodiments of the invention are shown and described. It should be understood, however, that the present disclosure is to be considered as an exemplification of the principles of this invention and is not intended to limit the invention to the embodiments illustrated.
The invention provides the use of a variety of phosphorus- and arsenic-containing inorganic and organic compounds that will self-assemble on the surface of semiconductor materials. The material may be subsequently annealed to dope the surface of the semiconductor material with phosphorus or arsenic.
While there has been recent interest and study relating to bonding monolayers of phosphorus to HF-cleaned silicon wafer surfaces, challenges remain and, to the best of the Applicant's knowledge, to date no other groups have successfully achieved an arsenic-containing monolayer. This is due in part to both a failure to elucidate the mechanism of bonding of the phosphorus-containing compounds to the HF-etched silicon, and to challenges relating to the significant chemical differences between phosphorus and arsenic.
The instant invention includes the first successful MLD of arsenic-containing compounds, which has various advantages over the prior art. These advantages may include utilization of chemicals having lower toxicity, and utilization of chemicals whose toxicological profiles have accessible records of use. The accessibility of toxicology publications and other similar information can help reduce risk in use.
In one aspect, the invention provides a method for preparing a doped silicon material, said method comprising:
The silicon material used according to embodiments of the present invention is known in the art, and includes, e.g., a silicon (Si) wafer/substrate.
In some embodiments, an entire, or essentially an entire, silicon surface is contacted with the dopant solution. In other embodiments, only a portion of a silicon surface is contacted with the dopant solution.
The composition of the dopant solutions used in the inventive processes varies depending on both solvent and solubility of the dopant or dopant-containing compound. In some embodiments, the dopant solutions used in the inventive processes described herein include solutions comprising less than or equal to 20% (wt/wt) dopant-containing compound (e.g., less than or equal to 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1%). For example, in some embodiments, the dopant solution comprises 0.5 to 20% (wt/wt) (e.g., 0.5, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, or 20%) of dopant-containing compound, including any and all ranges and subranges therein.
The dopant-containing compound in the dopant solution is selected from a phosphorus-containing compound and an arsenic-containing compound.
Dopant-containing compounds may be inorganic or organic in nature, and include compounds that are used in common applications such as controlling plant growth as herbicides (cacodylic acid and glyphosate), analytical chemistry agents (phenylarsine oxide), and feed additives (roxarsone).
Various inventive embodiments provide an additional improvement over the prior art, namely, the use of phosphorus- and arsenic-based dopants that help describe a mechanistic realm that defines the interaction between the dopant and the Ht-Si surface.
Many of the dopants and their solutions are stable in air and at room temperature. Experiments performed in oxygen-depleted and oxygen-free environments yield good results. For example, Applicant was also able to process effectively in, inter alia, a normal atmosphere of about 80% nitrogen and 20% oxygen.
Dopant solutions typically comprise one or more solvents. Solvents are well known in the art and a skilled artisan can readily select an appropriate solvent depending on the nature of the dopant-containing compound comprised within the dopant solution.
In some embodiments, the dopant solution comprises a solvent selected from the group consisting of mesitylene, alcohols, water, glycols, polyglycols, tetraglyme, and dimethylsulfoxide.
In some embodiments, the dopant solution comprises a solvent selected from methanol and ethanol.
In some embodiments, the dopant solution comprises water and one or more of an alcohol, glycol, and polyglycol.
In some embodiments, the dopant solution comprises an arsenic-containing compound. In some embodiments, the arsenic-containing compound is selected from those listed in Table A.
Table B lists an HMIS Summary for certain phosphorus- and arsenic-containing compounds that may be used in the present invention.
Table C provides a Solubility Summary for certain arsenic-containing compounds that may be used in the present invention.
In some embodiments, the dopant solution comprises a phosphorus-containing compound. In some embodiments, the phosphorus-containing compound is selected from those listed in Table D.
Table E provides a Solubility Summary for certain phosphorus-containing compounds that may be used in the present invention.
In some embodiments, the dopant-containing compound is selected from a trivalent phosphine oxide, a tetravalent phosphine oxide, phosphoric acid or a derivative thereof, phosphonic acid or a derivative thereof, phosphinic acid or a derivative thereof, and a bisphosphonate.
In some embodiments, the dopant-containing compound is selected from diethyl 1-propylphosphonate, phosphoric acid, phosphonic acid, methylphosphonic acid, and phosphinic acid.
In some embodiments, the dopant-containing compound is selected from the group consisting of arsenic acid or a derivative thereof, arsenous acid, a trivalent organoarsine, a pentavalent organoarsine oxide, a trivalent organoarsine oxide, and an arsenobetaine.
In some embodiments, the dopant-containing compound is selected from the group consisting of triphenylarsine, triphenylarsine oxide, roxarsone, cacodylic acid, phenylarsine oxide, diethyl propylarsenate, and arsenobetaine.
Diffusing the dopant (e.g., P, As, or a P- or As-containing compound or residue thereof) into the silicon material may be carried out by any art-acceptable manner. For example, in some embodiments, the diffusing step comprises one or more annealing steps.
Annealing is known in the art. Where diffusion is achieved via annealing, inventive embodiments encompass any desired annealing capable of diffusing the dopant into the silicon material, including both convention and non-conventional annealing, such as flash anneal, spike anneal, microwave anneal, laser anneal, or soak anneal Annealing may be carried out at any desirable diffusion-achieving temperature. Annealing is commonly carried out, e.g., in an inert atmosphere such as helium or argon, at temperatures from, e.g., 300° C. to 1200° C. In certain embodiments the substrate may be annealed at a temperature between 800° C. and 1100° C. for a period of 0. 5 seconds to 60 minutes (including any and all ranges and subranges therein, e.g., 1-60 seconds). The expression “from 300° C. to 1100° C.” means that the process is carried out either by maintaining any temperature between 300° C. and 1100° C. or by varying the temperature within that range. In some embodiments, the annealing is carried out at a temperature of 450° C. to 1200° C., for example, 450, 475, 500, 525, 550, 575, 600, 625, 650, 675, 700, 725, 750, 775, 800, 825, 850, 875, 900, 925, 950, 975, 1000, 1025, 1050, 1075, 1100, 1125, 1150, 1175, or 1200° C., including any and all ranges and subranges therein (e.g., 800° C. to 1150° C.
In some embodiments, the inventive method comprises, after forming the layer of dopant material on the surface of the silicon material, capping the layer of dopant material with a capping material. Capping materials are known in the art, and include materials that are typically used as a chemical barrier. Nitrides and oxides that can be conformally-coated function in this capacity, and fall within the scope of capping materials as discussed herein. For example, in some embodiments, the capping material is selected from silicon oxide and silicon nitride.
In some embodiments, the inventive method comprises, after forming the layer of dopant material on the surface of the silicon material, capping the layer of dopant material with a capping material, and the diffusing the dopant into the silicon material is carried out after the capping.
The doped silicon material has a sheet resistance (Rs) of less than or equal to 2,500 Ω/sq (e.g., less than or equal to 2500, 2400, 2300, 2200, 2100, 2000, 1900, 1800, 1700, 1600, 1500, 1400, 1300, 1200, 1100, 1000, 900, 800, 700, 600, 500, 400, or 300 Ω/sq). In some embodiments, the doped silicon material has a sheet resistance (Rs) of 150 to 2,000 Ω/sq, including any and all ranges and subranges therein (e.g., 150 to 1000 Ω/sq, 150 to 500 Ω/sq, 200 to 500 Ω/sq, etc.).
In some embodiments, the contacting a surface of the silicon material with the dopant solution comprises contacting the surface with the dopant solution for 1 to 300 minutes (e.g., 1, 2, 3, 4, 5, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 65, 70, 75, 80, 85, 90, 95, 100, 105, 110, 115, 120, 125, 130, 135, 140, 145, 150, 155, 160, 165, 170, 175, 180, 185, 190, 195, 200, 205, 210, 215, 220, 225, 230, 235, 240, 245, 250, 255, 260, 265, 270, 275, 280, 285, 290, or 300 min), including any and all ranges and subranges therein (e.g., 20 to 200 min).
In some embodiments, the surface of the silicon material is contacted with the dopant solution for less than or equal to 180 minutes.
In some embodiments, the surface of the silicon material is contacted with the dopant solution for less than or equal to 30 minutes.
In some embodiments, the contacting a surface of the silicon material with the dopant solution comprises dipping the silicon material surface in the dopant solution.
In some embodiments, surfactants and/or wetting agents may be used in the dopant solution to enable candidate chemicals soluble in organic solvents to achieve sufficient solubility or miscibility in polar solvents (e.g. water) and mixed solvent systems. Surfactants and wetting agents also enable more effective use of aqueous solutions in the presence of hydrophobic and non-polar surfaces like HF-etched silicon wafers.
In some embodiments, the invention relates to self-assembling phosphorus- and/or arsenic-containing dopant solutions used on Ht—Si surfaces. When contacted, the dopant or solute and the Ht—Si surface semiconductor form a bond. The formation of the bond is predicated on the affinity of the P- or As-dopant for the silicon surface. The solvent can facilitate or hinder formation of a bond with the silicon surface.
In another aspect, the invention provides a method for making an n-region in a semiconductor comprising:
In another aspect, the invention provides a method for selection of phosphorus-containing and arsenic-containing materials, e.g., for the two aspects described above. This aspect broadens the scope of phosphorus-containing and arsenic-containing materials available to the practitioner of this art. This aspect, which is illustrated in the following non-limiting examples, also facilitates the time-effective screening of phosphorus-containing and arsenic-containing compounds for the practitioner.
The invention will now be illustrated, but not limited, by reference to the specific embodiments described in the following examples.
Group I Testing
The substrates used in the examples were coupons, with dimensions of about 1″×1″, produced from standard silicon wafers. Surface oxide was removed from each coupon by a 300 second dip in aqueous HF, diluted 100:1, at room temperature followed by a 60 second dip rinse in H2O, and drying with a purified nitrogen jet. The cleaned coupons were immersed for 30 minutes at 60° C. in solutions that contained a phosphorus or an arsenic precursor. This step is termed the MLD soak. Solution volumes were between 60 and 100 mL. After the phosphorus or arsenic MLD soak, the coupons are removed from the solutions, rinsed for 10 seconds in solvent corresponding to the MLD soak solution solvent, then dried with a purified nitrogen jet. The coupons were then capped by chemical vapor deposition of a 200 angstrom film of silicon dioxide. The capped substrates were annealed under argon at 1050° C. for 1 to 30 seconds. Testing criteria and results are shown in Table 1.
When substrates are analyzed by secondary ion mass spectrometry (SIMS), we determined the phosphorus or arsenic concentration (in atoms/cm3) for all samples from two perspectives 1) at the surface and 2) as a function of depth. The samples exhibit values greater than 1019 at the surface and dropping below 1017 by a depth of 30 nm.
Group II Testing
The substrates used in the examples were standard silicon wafers. Surface oxide was removed by a 300 second dip in aqueous HF (100:1) at room temperature followed by a dip rinse in H2O and drying with a purified nitrogen jet. In many experiments, not shown, the dip time ranged from 1 minute to fifteen minutes. After the phosphorus or arsenic MLD step, the substrate surface was capped by physical vapor deposition (sputtering) of a 200 angstrom film of silicon nitride using a single crystal silicon target doped with phosphorus (99.999% purity) and a flow rate of argon 35 SCCM at 300 W power at ambient temperature. The capped substrates were annealed under argon at 1050° C. for 30 seconds. Testing criteria and results are shown in Table 3.
Substrates were analyzed by secondary ion mass spectrometry (SIMS) from two perspectives: 1) at the surface; and 2) as a function of depth, to determine the phosphorus or arsenic concentration (in atoms/cm3) for all samples. The samples exhibited values greater than 1019 at the surface and dropping below 1018 by a depth of 30 nm.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprise” (and any form of comprise, such as “comprises” and “comprising”), “have” (and any form of have, such as “has” and “having”), “include” (and any form of include, such as “includes” and “including”), and “contain” (and any form contain, such as “contains” and “containing”) are open-ended linking verbs. As a result, a method or device that “comprises”, “has”, “includes” or “contains” one or more steps or elements possesses those one or more steps or elements, but is not limited to possessing only those one or more steps or elements. Likewise, a step of a method or an element of a device that “comprises”, “has”, “includes” or “contains” one or more features possesses those one or more features, but is not limited to possessing only those one or more features. Furthermore, a device or structure that is configured in a certain way is configured in at least that way, but may also be configured in ways that are not listed.
As used herein, the terms “comprising” and “including” or grammatical variants thereof are to be taken as specifying the stated features, integers, steps or components but do not preclude the addition of one or more additional features, integers, steps, components or groups thereof. This term encompasses the terms “consisting of” and “consisting essentially of”.
The phrase “consisting essentially of” or grammatical variants thereof when used herein are to be taken as specifying the stated features, integers, steps or components but do not preclude the addition of one or more additional features, integers, steps, components or groups thereof but only if the additional features, integers, steps, components or groups thereof do not materially alter the basic and novel characteristics of the claimed composition, device or method.
All publications mentioned in this specification are herein incorporated by reference as if each individual publication were specifically and individually indicated to be incorporated by reference herein as though fully set forth.
Subject matter incorporated by reference is not considered to be an alternative to any claim limitations, unless otherwise explicitly indicated.
Where one or more ranges are referred to throughout this specification, each range is intended to be a shorthand format for presenting information, where the range is understood to encompass each discrete point within the range as if the same were fully set forth herein.
While several aspects and embodiments of the present invention have been described and depicted herein, alternative aspects and embodiments may be affected by those skilled in the art to accomplish the same objectives. Accordingly, this disclosure and the appended claims are intended to cover all such further and alternative aspects and embodiments as fall within the true spirit and scope of the invention.
This application claims priority to U.S. Provisional Application No. 61/893,339, filed Oct. 21, 2013, the entire contents of which are incorporated herein in their entirety.
| Number | Date | Country | |
|---|---|---|---|
| 61893339 | Oct 2013 | US |
