Patent Application
20250048756
The present disclosure relates to the field of display technology, and in particular to a photo detection substrate, an image sensor, and an electronic apparatus.
An Active Pixel Sensor (APS) is characterized in that a thin film transistor and a photodiode are combined to form a pixel unit. Compared with a conventional Passive Pixel Sensor (PPS), the APS has the advantages of low noise, high reading speed, and the like, and has been widely applied to glass-based image sensors.
In a first aspect, an embodiment of the present disclosure provides a photo detection substrate, including:
In some embodiments, a material of the active layer pattern of the superposed transistor includes an oxide semiconductor material doped with a rare earth element.
In some embodiments, the orthographic projection of the active layer pattern of the superposed transistor on the base substrate is within the orthographic projection of the photoelectric conversion structure in the same detection pixel unit on the base substrate.
In some embodiments, the photo detection substrate further includes a plurality of gate lines sequentially arranged along a first direction and a plurality of signal reading lines sequentially arranged along a second direction, where the plurality of gate lines each extend along the second direction, the plurality of signal reading lines each extend along the first direction, and the first direction and the second direction intersect each other;
In some embodiments, the photo detection substrate further includes:
In some embodiments, the signal reading line is on a side of the circuit connection pattern layer away from the base substrate; and
In some embodiments, a material of the circuit connection pattern layer includes a transparent conductive material.
In some embodiments, the first electrode, the bias voltage supply line, and the gate line are in the same layer.
In some embodiments, the photo detection substrate further includes a bias transmission pattern, where the second electrode of the photoelectric conversion structure is connected to the corresponding bias voltage supply line through the bias transmission pattern; and
In some embodiments, the signal reading circuit includes a switching transistor;
In some embodiments, the bias voltage supply line is in the same layer as the gate line, and the signal reading line extends in the second direction; and
In some embodiments, the second electrode has a third edge and a fourth edge opposite to each other in the first direction;
In some embodiments, the second electrode further has a first edge and a second edge opposite to each other in the second direction;
In some embodiments, the signal reading circuit includes a reset transistor, a source follower transistor, and a selection transistor;
In some embodiments, the reset transistor, the source follower transistor, and the selection transistor each are the superposed transistor.
In some embodiments, the second electrode has a first edge, a second edge, a third edge, and a fourth edge, the first edge and the second edge are opposite to each other in the second direction, the third edge and the fourth edge are opposite to each other in the first direction;
In some embodiments, the reset control line, the bias voltage supply line, the gate line, and the first electrode are arranged in the same layer, and the reset control line and the bias voltage supply line each extend in a second direction;
In some embodiments, the photo detection substrate further includes:
In some embodiments, the photo detection substrate further includes:
In some embodiments, the source follower transistor is the superposed transistor.
In some embodiments, the gate of the reset transistor is in the same layer as the gate of the source follower transistor, and the gate of the selection transistor is in the same layer as the gate of the source follower transistor;
In some embodiments, both of the reset transistor and the selection transistor are the superposed transistors; and
In some embodiments, a material of the active layer pattern of the source follower transistor includes amorphous silicon or polysilicon.
In some embodiments, an orthographic projection of the channel region of the active layer pattern of the source follower transistor on the base substrate is within the orthographic projection of the photoelectric conversion structure in the same detection pixel unit on the base substrate; and
In a second aspect, an embodiment of the present disclosure further provides an image sensor, including the a photo detection substrate as provided in the first aspect.
In a third aspect, an embodiment of the present disclosure further provides an electronic apparatus, including the image sensor as provided in the second aspect.
In order to enable one of ordinary skill in the art to better understand the technical solutions of the present disclosure, a photo detection substrate, an image sensor and an electronic apparatus provided by the present disclosure will be further described in detail below with reference to the accompanying drawings.
Numerous specific details of the present disclosure, such as structures, materials, dimensions, processing methods and techniques of the components, are set forth in the following description in order to provide a more thorough understanding of the present disclosure. However, as will be understood by one of ordinary skill in the art, the present disclosure may not be implemented according to these specific details.
The use of “first”, “second”, and the like in the present disclosure is not intended to indicate any order, quantity, or importance, but rather serves to distinguish one element from another. The word “including”, “includes”, or the like means that the element or item preceding the word includes the element or item listed after the word and its equivalent, but does not exclude other elements or items. The term “coupled”, “connected”, or the like is not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
A transistor employed in the embodiment of the present disclosure may be a thin film transistor, a field effect transistors, or other devices having the same characteristics. The transistor includes a gate and an active layer pattern, where the active layer pattern includes a channel region and a source/drain doped region. The source/drain doped region refers to a region, which has certain conductivity, in a semiconductor material, formed by performing a processing, for example, doping, on the semiconductor material. The source/drain doped region in the active layer pattern may serve as a source and a drain of the transistor. There is no difference in essence between the drain and the source of each transistor in the embodiment of the present disclosure. For distinguishing the two poles of the transistor other than the control pole (i.e., the gate), one of the drain and the source is referred to as a first pole, and the other of the drain and the source is referred to as a second pole. The channel region refers to a region which is between the source and the drain in the active layer pattern and can conduct electricity when the transistor is in a turned-on state (controlled by a gate voltage). Generally, the channel region is a region, which overlaps the gate in a direction perpendicular to a base substrate, in the active layer pattern.
In addition, two structures in a same layer described in the embodiment of the present disclosure mean that the two structures are formed by patterning a same material thin film layer. That is, the two structures may be simultaneously obtained by patterning the same material thin film layer.
The term “about”, “around”, or “approximately” as used in the embodiment of the present disclosure includes the stated values and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art in view of the measurement in question and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, the term “about” may mean a difference from the stated value within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5%.
In an APS structure, an operating state of the thin film transistor in a signal reading circuit directly affects reading of an electrical signal, and thus the stability of the thin film transistor is particularly important. However, in practical applications, it is found that the semiconductor material contained in the active layer pattern in the thin film transistor is very susceptible to water, oxygen and hydrogen, resulting in poor stability. The semiconductor material is particularly susceptible to hydrogen, and the hydrogen permeation may cause the semiconductor material contained in the active layer pattern to be transformed into a conductor, so that the electrical characteristics of the thin film transistor are changed.
Specifically, in the related art, all the thin film transistors in the signal reading circuit are each located between a photodiode and the base substrate. That is, the manufacturing process of all the thin film transistors in the related art is completed prior to the manufacturing process of the photodiodes. A large amount of hydrogen-related particles may be generated in the deposition process of the photodiodes. When the hydrogen-related particles penetrate into the channel region of the active layer pattern in the thin film transistor, the electrical characteristics of the channel region may be changed, for example, the threshold voltage of the thin film transistor is severely shifted, thereby affecting the overall performance of the APS.
In addition, the thin film transistor and the photodiode are staggered in the related art. In a high-resolution product, a size of a pixel is small, an effective area of the photodiode is compressed, so that the electric signal output by the photodiode is weak, which is not beneficial to subsequent detection.
To effectively solve at least one technical problem existing in the related art, an embodiment of the present disclosure provides a photo detection substrate.
The detection pixel units are located on the base substrate GL, and the detection pixel units each include a signal reading circuit 1 and a photoelectric conversion structure 3. The signal reading circuit 1 includes at least one transistor including a gate and an active layer pattern. The active layer pattern includes a channel region and a source/drain doped region. At least one transistor in the signal reading circuit 1 is a superposed transistor MR. The superposed transistor MR is located on a side of the photoelectric conversion structure 3 away from the base substrate GL. An orthographic projection of the active layer pattern of the superposed transistor MR on the base substrate GL overlaps an orthographic projection of the photoelectric conversion structure 3 in the same detection pixel unit on the base substrate GL. A material of the gate of the superposed transistor MR includes a transparent conductive material.
In the embodiment of the present disclosure, by setting at least one transistor in the signal reading circuit 1 as the superposed transistor MR on the side of the photoelectric conversion structure 3 away from the base substrate GL, that is, the manufacturing process of the superposed transistor MR is performed subsequent to the manufacturing process of the photoelectric conversion structure 3, the problem that the hydrogen-related particles in the manufacturing process of the photoelectric conversion structure 3 penetrate into the channel region of the superposed transistor MR can be prevented, so that the electrical characteristics of the channel region of the superposed transistor MR can be ensured to be stable. Furthermore, alternatively, an orthographic projection of the channel region of the active layer pattern of the superposed transistor MR on the base substrate GL overlaps the orthographic projection of the photoelectric conversion structure 3 in the same detection pixel unit on the base substrate GL.
Meanwhile, the orthographic projections of the active layer pattern of the superposed transistor MR and the photoelectric conversion structure 3 on the base substrate GL overlap each other, so that the superposed transistor MR and the photoelectric conversion structure 3 can be stacked in the direction perpendicular to the base substrate GL, which is beneficial to increase an overall size of the photoelectric conversion structure 3 in the detection pixel unit. In addition, through stacking the superposed transistor MR and the photoelectric conversion structure 3, the gate of superposed transistor MR will inevitably overlap the photoelectric conversion structure 3 in the direction of perpendicular to base substrate GL. In this case, the gate of the superposed transistor MR is made of a transparent conducting material, so that the gate of the superposed transistor MR can be prevented from shielding light of the photoelectric conversion structure 3, and an actual irradiated area of photoelectric conversion structure 3 can be effectively improved, thereby an intensity of an electrical signal output from the photodiode outputs can be improved, which is beneficial for subsequent detection.
Based on the above, it can be seen that with the technical solution of the present disclosure, on one hand, the influence of the manufacturing process of the photoelectric conversion structure 3 on the channel region of at least a portion of the transistors (which may be designed according to actual requirements, and specific examples may be referred to the following description) in the signal reading circuit 1 can be effectively prevented, and on the other hand, it is beneficial to improve the overall size and the actual irradiated area of the photoelectric conversion structure 3, and it is beneficial to improve the intensity of the electrical signal output from the photodiode, which is beneficial for the subsequent detection.
In some embodiments, the material of the gate of the superposed transistor MR includes Indium Tin Oxide (ITO).
In an embodiment of the present disclosure, the gate of the superposed transistor MR is made of a transparent conductive material, that is, light passing through the gate of the superposed transistor MR may irradiate the channel region of the superposed transistor MR (and then may reach the photoelectric conversion structure 3 through the channel region). In this case, the light has a certain influence on the electrical characteristics of the channel region of the superposed transistor MR, resulting in a shift of the electrical characteristics of the channel region of the superposed transistor MR.
Therefore, the material of the active layer pattern of the superposed transistor MR is improved in the embodiment of the disclosure. Specifically, the material of the active layer pattern of the superposed transistor MR employs a metal oxide semiconductor material with high mobility and high light stability, such as any one or more of Indium Zinc Oxide (IZO), Indium Gallium Zinc Oxide (IGZO), Indium Gallium Zinc Tin Oxide (IGZTO), Indium Gallium Oxide (IGO), or Indium Zinc Tin Oxide (IZTO) based materials, each of which is doped with rare earth elements. Specifically, the metal oxide semiconductor material may be indium zinc oxide doped with lanthanum (La) element or praseodymium (Pr) element, indium zinc oxide doped with cerium (Ce) element, indium gallium zinc oxide (IGZO) doped with praseodymium element, or the like.
In the embodiment of the present disclosure, by employing an oxide semiconductor material doped with a rare earth element as the material of the active layer pattern of the superposed transistor MR, the light stability of the channel region of the superposed transistor MR can be effectively improved.
In some embodiments, an orthographic projection of the active layer pattern of the superposed transistor MR on the base substrate GL is within an orthographic projection of the photoelectric conversion structure 3 in the same detection pixel unit on the base substrate GL. In this case, the active layer pattern of the superposed transistor MR is arranged directly above the photoelectric conversion structure 3, which is beneficial to increase the overall size of the photoelectric conversion structure 3.
In some embodiments, the photoelectric conversion structure 3 includes a PIN photodiode and a PN photodiode, and an operating state of the photo sensor can be controlled by controlling voltages applied to the first electrode 301 and the second electrode 303. The photoelectric conversion layer 302 may include a P-type semiconductor layer (e.g., P-type Si layer) and an N-type semiconductor layer (e.g., N-type Si layer) stacked together, and in this case, the photoelectric conversion structure 3 is a PN photodiode. The photoelectric conversion layer 302 may alternatively include a P-type semiconductor layer, an intrinsic semiconductor layer (e.g., an intrinsic Si layer), and an N-type semiconductor layer, which are stacked together, and in this case, the photoelectric conversion structure 3 is a PIN photodiode. Illustratively, the intrinsic semiconductor layer is an a-Si material, the P-type semiconductor layer is an a-Si material doped with B ions, and the N-type semiconductor layer is an a-Si material doped with P ions.
In some embodiments, the second electrode 303 is a transparent electrode, and may be made of a transparent metal oxide material such as indium tin oxide, indium zinc oxide, or gallium zinc oxide. The first electrode 301 is a metal electrode, and may be made of a metal material such as copper, aluminum, titanium, or molybdenum, or an alloy material. It should be noted that in the embodiment of the present disclosure, a “transparent” structure means that the structure can transmit light, and does not mean that the structure has a light transmittance of 100%.
In some embodiments, an area of an orthographic projection of the first electrode 301 on the base substrate GL is greater than an area of an orthographic projection of the photoelectric conversion layer 302 on the base substrate GL, and the area of the orthographic projection of the photoelectric conversion layer 302 on the base substrate GL is equal to or greater than an area of an orthographic projection of the second electrode 303 on the base substrate GL.
In some embodiments, the orthographic projection of the active layer pattern of the superposed transistor MR on the base substrate GL is within the orthographic projection of the second electrode 303 of the photoelectric conversion structure 3 in the same detection pixel unit on the base substrate GL.
In practical applications, a direct current bias voltage is applied to the second electrode 303, and in this case, the second electrode 303 may serve as a shielding electrode to shield and protect the active layer pattern (including the channel region) of the superposed transistor MR, for example, to suppress an influence of charges induced in the base substrate on the electrical characteristics of the channel region of the superposed transistor MR. It is beneficial to improve the uniformity of the threshold voltage of the superposed transistors MR in different detection pixel units.
In some embodiments, the photo detection substrate further includes a plurality of gate lines GATE sequentially arranged along a first direction X and a plurality of signal reading lines RL sequentially arranged along a second direction Y, where the gate lines GATE each extend along the second direction Y, the signal reading lines RL each extend along the first direction X, and the first direction X and the second direction Y intersect each other. The plurality of gate lines GATE and the plurality of signal reading lines RL define a plurality of detection pixel units. The signal reading circuit 1 in the detection pixel unit is connected to a corresponding gate line GATE and a corresponding signal reading line RL. The photo detection substrate further includes a plurality of bias voltage supply lines Vin. The photoelectric conversion structure 3 includes a first electrode 301, a photoelectric conversion layer 302, and a second electrode 303, which are arranged sequentially in a direction away from the base substrate GL, where the first electrode 301 is connected to the corresponding signal reading circuit 1, and the second electrode 303 is connected to a corresponding bias voltage supply line Vin.
In some embodiments, the photo detection substrate further includes a circuit connection pattern layer, which is located on a side of the superposed transistor MR away from the base substrate GL. The circuit connection pattern layer includes a plurality of circuit connection patterns, each of which is connected to the source/drain doped region of a corresponding transistor.
In some embodiments, the signal reading line RL is located on a side of the circuit connection pattern layer away from the base substrate GL. The circuit connection pattern layer includes a first circuit connection pattern CL1. The signal reading line RL is connected to the source/drain doped region of the corresponding transistor in the signal reading circuit 1, through a corresponding first circuit connection pattern CL1.
In some embodiments, a material of the circuit connection pattern layer includes a transparent conductive material. In an embodiment of the present disclosure, the circuit connection pattern in the circuit connection pattern layer is required to be connected to the source/drain doped region of the corresponding transistor. That is, the circuit connection pattern may overlap a region where the photoelectric conversion structure 3 (especially the second electrode 303) is located. In order to prevent the circuit connection pattern from shielding light to the photoelectric conversion structure 3, it is preferable to employ a transparent conductive material, such as indium tin oxide, as the material of the circuit connection pattern layer.
In some embodiments, the first electrode 301, the bias voltage supply line Vin, and the gate line GATE are arranged in a same layer. That is, the first electrode 301, the bias voltage supply line Vin, and the gate line GATE may be simultaneously formed based on one patterning process, which is beneficial to shorten the production period.
In some embodiments, the photo detection substrate further includes a bias transmission pattern CP, through which the second electrode 303 of the photoelectric conversion structure 3 is connected to a corresponding bias voltage supply line Vin. The bias transmission pattern CP is arranged in the same layer as the gate of the superposed transistor MR. That is, the bias transmission pattern CP and the gate of the superposed transistor MR may be simultaneously formed based on one patterning process, which is beneficial to shorten the production period.
The photo detection substrate in the present disclosure will be described in detail with reference to specific examples.
With continued reference to
In the drawings, M0_g denotes the gate of the switching transistor M0, and M0_a denotes the active layer pattern (including the channel region and the source/drain doped region) of the switching transistor M0.
In some embodiments, the bias voltage supply line Vin is arranged in the same layer as the gate line GATE, and the signal reading line RL extends in the second direction Y. A bias voltage supply line Vin and a gate line GATE corresponding to the detection pixel unit are located on two opposite sides of the photoelectric conversion structure 3 in the detection pixel unit in the first direction X, respectively.
In some embodiments, the second electrode 303 has a third edge EG3 and a fourth edge EG4, which are opposite to each other in the first direction X. A gate line GATE corresponding to the detection pixel unit is located on a side closer to the fourth edge EG4 of the second electrode 303 in the detection pixel unit. An orthographic projection of the gate M0_g of the switching transistor M0 on a plane, where the second electrode 303 is located, intersects the fourth edge EG4. A bias voltage supply line Vin corresponding to the detection pixel unit is located on a side closer to the third edge EG3 of the second electrode 303 in the detection pixel unit. The photo detection substrate further includes the bias transmission pattern CP, through which the second electrode 303 of the photoelectric conversion structure 3 is connected to the corresponding bias voltage supply line Vin. The bias transmission pattern CP is arranged in the same layer as the gate of the superposed transistor MR, and an orthographic projection of the bias transmission pattern CP on the plane, where the second electrode 303 is located, intersects the third edge EG3.
In some embodiments, the second electrode 303 further has a first edge EG1 and a second edge EG2, which are opposite to each other in the second direction Y.
The photo detection substrate further includes a wiring layer, which is located on a side of the superposed transistor MR away from the base substrate GL. The wiring layer includes the signal reading line RL. A signal reading line RL corresponding to the detection pixel unit is located on a side closer to the first edge EG1 of the second electrode 303 in the detection pixel unit.
The photo detection substrate further includes a circuit connection pattern layer, which is located between the superposed transistor MR and the wiring layer. The circuit connection pattern layer includes a first circuit connection pattern CL1 and a second circuit connection pattern CL2.
A part, which serves as the first pole of the switching transistor M0, of the source/drain doped region of the active layer pattern M0_a of the switching transistor M0 is connected to the corresponding signal reading line RL through a corresponding first circuit connection pattern CL1. An orthographic projection of the first circuit connection pattern CL1 on the plane, where the second electrode 303 is located, intersects the first edge EG1.
A part, which serves as the second pole of the switching transistor M0, of the source/drain doped region of the active layer pattern M0_a of the switching transistor M0 is connected to the first electrode 301 of the photoelectric conversion structure 3 in the same detection pixel unit through a corresponding second circuit connection pattern CL2. An orthographic projection of the second circuit connection pattern CL2 on the plane, where the second electrode 303 is located, intersects the fourth edge EG4.
Referring to
First, as shown in
Then, referring to
Next, as shown in
Next, a gate insulating layer GI is formed on a side of the active layer pattern away from the base substrate GL.
Next, as shown in
Then, an interlayer dielectric layer ILD is formed.
Next, as shown in
Taking the manufacturing of the detection pixel unit shown in
Next, a first passivation layer PVX1 and a planarization layer PLN are sequentially formed.
Next, referring to
Alternatively, a second passivation layer PVX2 is further arranged on a side of the wiring layer away from the base substrate GL.
A gate M1_g of the reset transistor M1 is connected to a reset control line RESET, a first pole of the reset transistor M1 is connected to a reset voltage supply line Vrst, and a second pole of the reset transistor M1 is connected to a first electrode 301 of a photoelectric conversion structure 3. A gate M2_g of the source follower transistor M2 is connected to a first electrode 301 of the photoelectric conversion structure 3, a first pole of the source follower transistor M2 is connected to an operating voltage supply line Vdd, and a second pole of the source follower transistor M2 is connected to a first pole of the selection transistor M3. A gate M3_g of the selection transistor M3 is connected to a corresponding gate line GATE, and a second pole of the selection transistor M3 is connected to a corresponding signal reading line RL.
In the drawings, M1_g denotes the gate of the reset transistor M1, M1_a denotes an active layer pattern (including a channel region and a source/drain doped region) of the reset transistor M1; M2_g denotes the gate of the source follower transistor M2, and M2_a denotes an active layer pattern (including a channel region and a source/drain doped region) of the source follower transistor M2; M3_g denotes the gate of the selection transistor M3, and M2_a denotes an active layer pattern (including a channel region and a source/drain doped region) of the selection transistor M3.
Referring to
In some embodiments, the second electrode 303 has a first edge EG1, a second edge EG2, a third edge EG3, and a fourth edge EG4, where the first edge EG1 and the second edge EG2 are opposite to each other in the second direction Y, and the third edge EG3 and the fourth edge EG4 are opposite to each other in the first direction X.
The second electrode 303 includes a first sub-region and a second sub-region arranged in the second direction Y, where the channel region of the source follower transistor M2 is located in the first sub-region, and both of the channel region of the reset transistor M1 and the channel region of the selection transistor M3 are located in the second sub-region.
An orthographic projection of the gate M2_g of the source follower transistor M2 on a plane, where the second electrode 303 is located, intersects the third edge EG3. An orthographic projection of the gate M2_1 of the reset transistor M1 on the plane, where the second electrode 303 is located, intersects the second edge EG2. An orthographic projection of the gate M3_g of the selection transistor M3 on the plane, where the second electrode 303 is located, intersects the fourth edge EG4.
In some embodiments, the reset control line RESET, the bias voltage supply line Vin, the gate line GATE, the first electrode 301 are arranged in a same layer, and both the reset control line RESET and the bias voltage supply line Vin extend in the second direction Y.
One of a bias voltage supply line Vin and a reset control line RESET corresponding to the detection pixel unit is located on a side closer to the third edge EG3 of the second electrode 303 in the detection pixel unit, and the other of the bias voltage supply line Vin and the reset control line RESET corresponding to the detection pixel unit is located on a side closer to the fourth edge EG4 of the second electrode 303 in the detection pixel unit.
A gate line GATE corresponding to the detection pixel unit is located on a side closer to the fourth edge EG4 of the second electrode 303 in the detection pixel unit.
A part of the first electrode 301 of the photoelectric conversion structure 3, which is in contact with the gate M2_g of the corresponding source follower transistor M2, is located on a side closer to the third edge EG3 of the second electrode 303 in the detection pixel unit.
In some embodiments, the photo detection substrate further includes a wiring layer, which is located on a side of the superposed transistor MR away from base substrate GL. The wiring layer includes the reset voltage supply line Vrst, the operating voltage supply line Vdd, and the signal reading line RL. The reset voltage supply line Vrst and the operating voltage supply line Vdd each extend in the first direction X.
An operating voltage supply line Vdd corresponding to the detection pixel unit is located on a side closer to the first edge EG1 of the second electrode 303 in the detection pixel unit.
A reset voltage supply line Vrst and a signal reading line RL corresponding to the detection pixel unit each are located on a side closer to the second edge EG2 of the second electrode 303 in the detection pixel unit.
In some embodiments, the photo detection substrate further includes a circuit connection pattern layer, which is located between the superposed transistor MR and the wiring layer. The circuit connection pattern layer includes a first circuit connection pattern CL1, a second circuit connection pattern CL2, a third circuit connection pattern CL3, and a fourth circuit connection pattern CL4.
A part, which serves as the second pole of the selection transistor M3, of the source/drain doped region of the active layer pattern M3_a of the selection transistor M3 is connected to a corresponding signal reading line RL through a corresponding first circuit connection pattern CL1. An orthographic projection of the first circuit connection pattern CL1 on the plane, where the second electrode 303 is located, intersects the second edge EG2.
A part, which serves as the first pole of the reset transistor M1, of the source/drain doped region of the active layer pattern M1_a of the reset transistor M1 is connected to the first electrode 301 of the corresponding photoelectric conversion structure 3 through a corresponding second circuit connection pattern. An orthographic projection of the second circuit connection pattern CL2 on the plane, where the second electrode 303 is located, intersects the third edge EG3.
A part, which serves as the second pole of the reset transistor M1, of the source/drain doped region of the active layer pattern M1_a of the reset transistor M1 is connected to a corresponding reset voltage supply line Vrst through a corresponding third circuit connection pattern. An orthographic projection of the third circuit connection pattern CL3 on the plane, where the second electrode 303 is located, intersects the second edge EG2.
A part, which serves as the first pole of the source follower transistor M2, of the source/drain doped region of the active layer pattern M2_a of the source follower transistor M2 is connected to a corresponding operating voltage supply line Vdd through a corresponding fourth circuit connection pattern. An orthographic projection of the fourth circuit connection pattern CL4 on the plane, where the second electrode 303 is located, intersects the first edge EG1.
The source follower transistor M2 is only exemplarily shown in
It should be noted that, in a case where the reset transistor M1, the source follower transistor M2, and the selection transistor M3 are all superposed transistors MR, the arrangement of the reset transistor M1, the source follower transistor M2, and the selection transistor M3 above the photoelectric conversion structure 3 shown in
It should be noted that a process of manufacturing the photo detection substrate including the detection pixel unit shown in
As an alternative embodiment, the gate M1_g of the reset transistor M1 is arranged in the same layer as the gate M2_g of the source follower transistor M2, and the gate M3_g of the selection transistor M3 is arranged in the same layer as the gate M2_g of the source follower transistor M2. The active layer pattern M1_a of the reset transistor M1 is arranged in the same layer as the active layer pattern M2_a of the source follower transistor M2, and there is no overlap between an orthographic projection of the active layer pattern M1_a of the reset transistor M1 on the base substrate GL and an orthographic projection of the photoelectric conversion structure 3 in the same detection pixel unit on the base substrate GL. The active layer pattern M3_a of the selection transistor M3 is arranged in the same layer as the active layer pattern M2_a of the source follower transistor M2, and there is no overlap between an orthographic projection of the active layer pattern M3_a of the selection transistor M3 on the base substrate GL and the orthographic projection of the photoelectric conversion structure 3 in the same detection pixel unit on the base substrate GL.
That is, although the reset transistor and the selection transistor M3 are located on the side of the photoelectric conversion structure 3 away from the base substrate GL, the active layer patterns M3_a of the reset transistor and the selection transistor M3 do not overlap the photoelectric conversion structure 3 in a direction perpendicular to the base substrate GL.
Generally, the source follower transistor M2 has the largest size, and the source follower transistor M2 has the highest requirement for the stability of the electrical characteristics, so that only the source follower transistor M2 may be selectively arranged right above the photoelectric conversion structure 3 as a reset transistor, and the other reset transistors each are arranged on either side of the photoelectric conversion structure 3. With such a design, the requirement of the source follower transistor M2 on the stability of the electrical characteristics can be met, and meanwhile, it is convenient to design the wiring of the detection pixel unit.
It should be noted that a process of manufacturing the photo detection substrate including the detection pixel unit shown in
Alternatively, a material of the active layer pattern M2_a of the source follower transistor M2 includes amorphous silicon or polysilicon. Low temperature polysilicon is described as an example herein. In this case, the photo detection substrate is a photo detection substrate based on the LTPO technology. The source follower transistor M2 is a low temperature polysilicon transistor, so that transconductance thereof can be improved, and signal amplification ratio thereof can be improved. The reset transistor M1 and the selection transistor M3 are metal oxide transistors, so that off-state leakage current thereof can be effectively reduced.
In some embodiments, an orthographic projection of the channel region M2_a1 of the active layer pattern M2_a of the source follower transistor M2 on the base substrate GL is within an orthographic projection of the photoelectric conversion structure 3 in the same detection pixel unit on the base substrate GL; and an orthographic projection of at least a part of the source/drain doped region M2_a2 of the active layer pattern M2_a of the source follower transistor M2 on the base substrate GL is outside the orthographic projection of the photoelectric conversion structure 3 in the same detection pixel unit on the base substrate GL.
In the present disclosure, the source follower transistor M2 of low temperature polysilicon is placed below the photoelectric conversion structure 3, and the photoelectric conversion structure 3 the source follower transistor M2 are stacked together, which is beneficial to increase the overall size of the photoelectric conversion structure 3.
It should be noted that the process of manufacturing the photo detection substrate including the detection pixel unit shown in
It should be noted that, the present disclosure is not limited to the relative positions of the reset transistor M1, the source follower transistor M2, and the selection transistor M3 in the direction parallel to the base substrate GL in the detection pixel unit shown in
Based on the same inventive concept, an embodiments of the present disclosure further provide an image sensor, which includes the photo detection substrate provided in the above embodiments, and specific description of the photo detection substrate may be referred to the foregoing description, and is not repeated here.
The image sensor may include peripheral circuits such as a row driver circuit, a column driver circuit, an amplifier circuit, and a pre-processing circuit, in addition to the photo detection substrate. These circuits are all conventional structures in the art, and the detailed circuit structure and operation process thereof are not described herein again.
Based on the same inventive concept, an embodiment of the present disclosure further provides an electronic apparatus including an image sensor, where the image sensor employs the above-described image sensor. The electronic apparatus may be a digital camera, a mobile phone, a tablet computer, a notebook computer, or the like.
It will be understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principles of the present disclosure, and the present disclosure is not limited thereto. It will be apparent to one of ordinary skill in the art that various modifications and improvements can be made without away from the spirit and essence of the present disclosure, and such modifications and improvements are also considered to be within the scope of the present disclosure.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2023/078825 | 2/28/2023 | WO |
