Patent Application
20180254300
The invention relates to photodiode arrays and more particularly to photodiode arrays having layers of indium gallium arsenide (InGaAs) and indium phosphide (InP), and to the manufacturing method thereof.
One of the methods for manufacturing a photodiode array in semiconductor materials with narrow band gap (often for detection in infrared light) is to insert the active detection layer with narrow band gap between two semiconductor materials with wide band gap. The two semiconductor layers with wide band gap consist of efficient protection/passivation whilst remaining transparent to the radiation wavelength intended to be detected by the photodiodes.
In addition, with suitable doping, the two heterojunctions between the active layer and the two protection/passivation layers confine photoelectric charges within the active detection layer and improve the quantum yield of the photodiode thus formed.
An InGaAs photodiode is a typical example of this physical structure. The active detection layer is consisting of InGaAs material to obtain an adjustable band gap as a function of the indium and gallium composition of the InGaAs material, ideal for operating in the Short WaveInfraRed band (SWIR) in the order of 0.9 to 3 μm.
Indium phosphide and indium gallium arsenide share the same face-centred crystalline structure. The most widely used composition is In0.53Ga0.47As. The size of the crystal lattice is then comparable with that of the InP substrate, in particular the lattice parameters. This crystalline compatibility allows epitaxial growth of an active InGaAs layer of excellent quality on an InP substrate. The band gap of In0.53Ga0.47As is about 0.73 eV, capable of detection up to a wavelength of 1.68 μm in the SWIR band. It is the subject of increasing interest in fields of application such as spectrometry, night vision, sorting of used plastics, etc.
The two protection/passivation layers are generally consisting of InP. More especially, since the In0.53Ga0.47As composition has the same crystal lattice size as InP, this allows a very low dark current as from ambient temperature.
Up until now, the best configuration of InGaAs photodiodes is consisting of selective doping areas in zinc Zn, of P-type, on epitaxial InP/InGaAs/InP layers of N-type, to constitute the anodes of the photodiodes which collect the charges. Such a configuration is said to be “P-on-N”.
Another solution to prepare a photodiode array is a so-called “N-on-P” configuration, where the anodes of the photodiodes which collect the charges are of N-type, on epitaxial layers of P-type. However, it is difficult to work with a P-type substrate, and selective doping of N-type is ill controlled. U.S. Pat. No. 8,610,170 B2 proposes an alternative solution for an “N-on-P” configuration illustrated in
However, this approach requires deep depth of diffusion for Zn doping when forming the area 104; the Zn dopants must enter into the entire thickness of the photosensitive layer 102 to reach the buried buffer layer 108. Yet diffusion of dopants does not only take place depth-wise, but also laterally parallel to the surface of the array. Therefore, the deeper the diffusion of Zn dopants, the wider it is.
For example, to maintain good quantum yield, the thickness of the photosensitive layer 102 of InGaAs is preferably at least 3 to 5 μm. A shallower depth reduces the efficacy of photon absorption. For such a thickness of 3 to 5 μm, lateral diffusion of Zn dopants around the incident area of doping i.e. the exposed areas of the mask used for diffusion, is 6 to 10 μm. It is therefore ascertained that the width of the portions of area 104 surrounding a cathode will be larger than 10 μm, i.e. more than twice the thickness of the photosensitive layer 102.
As a result, the pitch of the photodiodes on the surface of the array must be sufficiently large to allow an area 104 of Zn doping having portions of large width, and this approach therefore does not allow a photodiode array to be obtained having a high density of photodiodes on the surface thereof.
In addition, this lateral extension of portions of area 104 brings a related reduction in the surface area occupied by the cathodes insulated by said portions of said area 104. Returning to the preceding example, for a photodiode pitch of 10 to 15 μm, the size of the cathode becomes small in relation to the width of the portions of area 104. Yet the lifetime of charge carriers in the Zn diffusion area 104 is fairly short on account of the high doping level. Collecting efficiency therefore becomes reduced.
This same patent proposes another embodiment to form trenches around cathode areas of a photodiode before diffusing zinc. These trenches allow Zn diffusion to reach the buried buffer layer 108 faster, and therefore allow limiting of the lateral extension of this diffusion. However, experience has shown that damage related to the etching of these trenches considerably deteriorates the quality of the photodiodes, particularly in terms of dark current.
It is one objective of the invention to propose a photodiode array and the method for manufacture thereof, allowing insulating of the cathodes from one another whilst maintaining good quantum yield and good surface yield of the array. With the invention it is possible to obtain “N-on-P” photodiodes having improved photoelectric performance and compatible with a reduction in the pitch of the photodiodes, allowing a reduction in costs and increased resolution of InGaAs photodiode arrays.
For this purpose, there is proposed a photodiode array comprising:
By doped region of the second type is meant a region of a material comprising dopants of the second type resulting for example from diffusion thereof in said material, in higher concentration than any dopants of the first type.
The invention is advantageously completed by the following characteristics taken alone or in any technically possible combination:
The invention also relates to a sensor comprising a photodiode array of the invention, and a read-out circuit connected to contacts of the cathode areas to read the photodiodes of said array.
The invention also relates to a method for manufacturing an array according to one of the preceding claims, comprising the steps of:
Other characteristics and advantages of the invention will become apparent from the following description that is solely illustrative and nonlimiting. This description is to be read in connection with the appended drawings in which:
In the different Figures, same references designate similar elements.
In the following description, as an illustrative example, the first type of conductivity is conductivity of N-type, whilst the second type of conductivity is conductivity of P-type. It would also be possible, by adapting the components, that the first type of conductivity is conductivity of P-type whilst the second type of conductivity is conductivity of N-type.
With reference to
The array also comprises an active layer 5 of indium gallium arsenide InGaAs constituting a photosensitive layer above the substrate 4. The thickness of the active layer is preferably greater than 3 μm and preferably less than 5 μm. The active layer 5 may be non-doped (intrinsic) or N-doped at low concentration e.g. a concentration of dopants of between 1013 and 1017 cm−3,
Between the substrate 4 and the active layer 5, i.e. at their interface, there is a buried region 8 consisting of a P-doped area e.g. consisting of diffusion of zinc. The thickness of the buried region 8 is preferably greater than 0.01 μm and preferably less than 1 μm. If the thickness of the buried region 8 is too great this could absorb too much light.
The buried region 8 can be formed in several manners. As illustrated in
The array, above the active layer 5, also comprises an upper layer 6 of indium phosphide having conductivity of N-type. The thickness of the upper layer 6 is preferably greater than 0.1 μm and preferably less than 1 μm. The upper layer 6 can be N-doped for example at a dopant concentration of between 1015 and 1018 cm−3, typically of silicon. Preferably, the doping of the upper layer 6 is stronger than that of the active layer 5 by a factor of at least 10.
Insofar as some compositions of the active layer 5 have a crystal size close to that of an InP layer, especially the composition In0.53Ga0.47As, the superimposition of an InP layer over the active layer 5 allows dark current to be reduced to a very low level, as from ambient temperature. Similarly, a passivation layer 10 in dielectric material such as silicon nitride can be provided on the surface of the array above the upper layer 6.
The array also comprises at least one doped region 12 of P-type in the upper layer 6 and in the active layer 5. More specifically, the doped region 12 extends from the upper layer 6 as far as into the active layer 5 without reaching the buried region 8 or the substrate 4. The doped region 12 passes through the thickness of the upper layer 6 but does not pass through the thickness of the active layer 5. This doped region 12 of P-type forms an anode common to the photodiode array, that is therefore shared by several photodiodes and even preferably by all the photodiodes.
Preferably, the doped region 12 of P-type extends into the active layer 5 from the upper layer 6 over a depth that is less than one quarter of the thickness of said active layer 5, and further preferably less than one eighth of the thickness of said active layer 5. For example, for an active layer 5 having a thickness of 3 μm to 5 μm it is sufficient that the doped region 12 enters the active layer 5 to a depth of between 0.1 μm and 0.5 μm.
The P-type dopants of the doped region 12 may be zinc atoms and are preferably derived from diffusion from the surface of the upper layer 6 in the direction of the active layer 5.
The doped region 12 individually delimits several cathode areas 13, free of P-type doping, in the upper layer 6. The cathode areas 13 are separated from one another in the upper layer 6 by the doped region 12 in continuous manner i.e. each cathode area 13 is surrounded by the doped area 12 without discontinuity at the upper layer 6. Each of said cathode areas 13 constitutes a cathode of a photodiode. Each cathode area 13 is provided with a contact 14 to a read-out circuit adapted to read said photodiode.
The doped region 12 can therefore have a grid shape as in
At the interfaces between P-type and N-type materials (PN junction), space charge areas are created, also called depletion areas since they are depleted of free carriers. An anode space charge area 15 extends into the active layer 5 from each interface between the doped region 12 of P-type and the active layer 5. Similarly, a buried space charge area 16 extends into the active layer 5 from the interface between said active layer 5 and the buried region 8.
A space charge area 19 is also seen extending into the upper layer 6 from each interface between the doped region 12 of P-type and the upper layer 6, and a space charge area 17 extending into the substrate 4 from the interface between the buried region 8 and said substrate 4.
The electric field generated by a space charge area, oriented from the positive charges (in area N) in the direction of the negative charges (in area P) carries the electrons and the holes in the opposite direction to the phenomenon of charge carrier diffusion. The junction therefore reaches equilibrium since the phenomenon of charge carrier diffusion and the electric field created by this space charge area offset one another.
A space charge area therefore constitutes insulation for the charge carriers, confined within the constituent materials of the PN junction. In an array of the invention, the cathodes are electrically insulated from one another by space charge areas in the active layer 5.
For this purpose, the anode space charge area 15 and the buried space charge area 16 join together in the active layer 5 as illustrated in
The extension of a space charge area from the PN junction by which it is generated varies with the charge carrier concentration of the materials of the PN junction i.e. with the dopant concentration thereof. The doping level of P-type dopants in the doped region 12 is greater than the doping level of N-type dopants in the active layer 5, for example with a difference of a factor of at least 10. The anode space charge area 15 therefore extends essentially into the active layer 5. For example, the doping level in the doped region 12 is in the order of 1018 cm−3, whilst the active layer 5 has a doping level lower than 1016 cm−3—typically 1015 cm−3—, and the anode space charge area 12, in the absence of polarization, extends by 1 μm into the active layer 5 from the interface between said active layer 5 and the doped region 12. Similar for the buried space charge area 16. Therefore, for an active layer 5 of InGaAs having a thickness of 2 μm, the anode space charge areas 15 and the buried space charge areas 16 join together, even without polarization, at the described concentrations.
It is therefore possible to insulate the cathodes from one another i.e. prevent the passing of charges from one cathode to another cathode, without the doped region 12 reaching the buried region 8, by means of the continuity of the space charge areas around each area 18 of the active layer 5 free of P-type doping. However, in the absence of polarization, the extension of a space charge area from a PN junction remains limited, which means that this insulation can only be achieved with an active layer 5 of narrow thickness, or by limiting the residual distance d1 between the doped region 12 and the buried region 8 to less than the extension of their respective space charge areas in the absence of polarization.
So that it is possible to increase the thickness of the active layer 5, and hence improve the quantum yield thereof, whilst maintaining this insulation, without the depth of entry of the doped region 12 into the active layer 5 being too great however, it is possible to bias the PN junctions. The extension of a space charge area from the PN junction by which it is generated also varies with the voltages applied either side of the PN junction i.e. with the polarization of said junction. In particular, reverse bias i.e. with a higher potential applied to the cathode than to the anode, allows increased extension of a space charge area. It is then possible via reverse bias to cause the space charge areas to join up via their extension.
The structure of the array is similar to that described with reference to
In addition, each cathode area 13 of the upper layer 6 is provided with a contact 14 and connectors 21 connecting said contact 14 with a power source (not illustrated), constituting cathode bias means. The contact connected to the power source is preferably the same as the one adapted for connection to the read-out circuit, but it may be different.
Also, the doped region 12 is provided with at least one contact 20, optionally with several contacts 20, and connectors 22 connecting said contact 22 with a power source (not illustrated) constituting anode bias means.
Therefore, each cathode area 13 is connected to cathode bias means adapted to apply a first voltage Vk to each of the cathode areas 13, and the doped area 12 is connected to anode bias means adapted to apply a second voltage Va1 to said doped area 12. In the Figures, the first voltage is denoted Vk1, Vk2, Vk3, Vk4 to illustrate the independency between the first voltages of each cathode. It is to be noted that the first voltage Vki at a cathode may correspond to the voltage representing exposure of the photodiodes to light, that is read by the read-out circuits. Each photodiode may therefore have a voltage that varies differently as a function of its own exposure. In all cases, the first voltage Vk varies over a range between a minimum cathode voltage Vkmin and maximum cathode voltage Vkmax.
The first voltage Vk and the second voltage Va1 have different values. The difference in value between the first voltage Vk and second voltage Va1 determines the extension of the anode space charge area 15 into the active layer 5, and in particular the distance d2 over which the anode space charge area 15 extends into the active layer 5 from the interface between the doped region 12 and said active layer 5. For example, a difference of 1 V between the value of the first voltage Vk and the value of the second voltage Va1 allows an increase of 1 μm in distance d2 for a doped region 12 doped with zinc at 1018 cm−3 and for an active layer 5 doped with N dopants at 1015 cm−3.
The second voltage Va1 is chosen to be sufficiently lower than the minimum cathode voltage Vkmin so that the anode space charge area 15 extends into the active layer 5 as far as the buried space charge area 16. This provides insulation of the areas 18 of the active layer 5 by the space charge areas in
The buried region 8 can also be connected to bias means adapted to apply a third voltage Va2 to said buried region 8. To avoid having to connect the buried region 8 via an interconnect hole, this connection is preferably obtained via the periphery of the photodiode array. For this purpose, a P-doped peripheral area 24 of the array extends from the surface of the array i.e. the upper part 6 as far as the buried layer 8. This P-doped peripheral area 24 corresponds to the doping e.g. by diffusion of the peripheral sides of the active layer 5 and upper layer 6. The peripheral area 24 is provided with a contact 23 (see
The first voltage Vk and the third voltage Va2 have different values. The difference in value between the first voltage Vk and the third voltage Va2 determines the extension of the buried space charge area 16 into the active layer 5, and in particular the distance d3 over which the buried space charge area 16 extends into the active layer 5 from the interface between the buried region 8 and said active layer 5.
The third voltage Va2 is chosen to be sufficiently lower than the minimum cathode voltage Vkmin so that the buried space charge area 16 extends into active layer 5 as far as the anode space charge area 15. The second voltage Va1 and the third voltage Va2 may have the same values, but preferably have different values.
The doped region 12 of P-type and the upper layer 6 of N-type are in contact and their respective doping levels are relatively high compared with the doping of the active layer 5: for example 1015 to 1018 cm−3 for the upper layer 6, and 1018 cm−3 with Zn for the doped region 12, against 1013 to 1017 cm−3 for the active layer 5, bearing in mind that the doping of the upper layer 6 is preferably at least ten times greater than the doping of the active layer 5. It follows that a difference in value between the first voltage Vk and the second voltage Va1 that is too high may generate strong leakage currents in the PN junction constituted by the interface between the doped region 12 and the upper layer 6. On the other hand, the doping level in the active layer 5 being much lower, there is less risk of generating strong leakage currents in the PN junction constituted by the interface between the buried region 8 and the upper layer 6.
Therefore, the difference in value between the minimum cathode voltage Vkmin and the second voltage Va1 is preferably lower than the difference between the minimum cathode voltage Vkmin and the third voltage Va2. For example, returning to the preceding examples, with minimum polarization of 0.3 V between the minimum cathode voltage Vkmin and the second voltage Va1, and minimum polarization of 1.8 V between the minimum cathode voltage Vkmin and the third voltage Va2, it is possible to cause the space charge areas 15, 16 to join together in an active layer of 3 μm thickness.
When insulation is obtained, we therefore have the sum:
To limit the applied voltages, it is preferable however that the distance d4 separating the anode space charge area 15 from the buried space charge area 16 in the active layer 5, in the absence of polarization, should not be too great. Preferably distance d4 is twice shorter than the minimum between d2 and d3 in the absence of polarization:
d4<min(d2,d3).
It is to be noted that it is not necessary that both the second voltage Va1 and the third voltage Va2 should be lower than the lower limit of the variation range of the first voltage Vk, i.e. lower than the minimum cathode voltage Vkmin. It is sufficient that one thereof is sufficiently lower than this minimum cathode voltage Vkmin to ensure sufficiently large extension of its space charge area so that it joins up with the other space charge area. The other anode voltage could then be slightly higher than the first voltage without interrupting the insulation of the cathodes for as long as the space charge areas . . . . However, to be on the safe side, it is better if both the second voltage Va1 and the third voltage Va2 are lower than the lower limit of the variation range of the first voltage Vk, i.e. lower than the minimum cathode voltage Vkmin.
Irrespective of the method used to cause the anode space charge area 15 and the buried space charge area 16 to join together, (via doping and/or polarization) the cathodes are separated from one another by continuity of space charge area. The photoelectrons are therefore repelled towards the cathode and confined therein. In addition, it is not necessary for the active layer 5 to be highly doped: the lifetime of charge carriers in the active layer 5 and hence in the cathode, is extended. In this manner, detection is improved compared with the solution proposed in U.S. Pat. No. 8,610,170 B2. Also, the doped region 12 does not need to pass through the entire thickness of the active layer 5, and the lateral diffusion of dopants forming this doped region 12 therefore remains limited, thereby allowing a reduction in the spatial pitch of the photodiodes in comparison with the solution proposed in U.S. Pat. No. 8,610,170 B2, and hence an increase in the resolution of the array.
With reference to
At a first step, illustrated in
At a fourth step illustrated in
At a sixth step illustrated in
At a seventh step illustrated in
Dopants of P-type are then diffused through the exposed areas 32 in the upper layer 6 and in the active layer 5 to define the doped region 12 of P-type so that the doped region 12 extends from the upper layer 6 as far as into the active layer 5 without reaching the buried region 8 or the substrate 4. The diffusion of dopants is therefore interrupted before the doped region 12 reaches the buried region 8. On peripheral sides of the active layer 5 and of the upper layer 6. a peripheral P-doped area 24 is also created extending from the surface of the array i.e. the upper part 6 as far as the buried layer 8.
At an eighth step illustrated in
The invention is not limited however to the embodiment described and illustrated in the appended Figures. Modifications remain possible, in particular in respect of the forming of the various elements or substitution thereof by technical equivalents, without departing from the scope of protection of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 1557925 | Aug 2015 | FR | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/FR2016/052129 | 8/26/2016 | WO | 00 |
