Patent Application
20230420586
This disclosure relates generally to nitride-based photodiodes for conversion of light energy to electrical power, particularly at high light and current densities, and methods for fabrication. The invention can be applied to applications involving conversion of light energy to electrical energy, particularly via optical fibers, other optoelectronic devices, and similar products.
Electrical power is typically transmitted over a wire, for example, a copper wire. However, such wires can be heavy, cumbersome, and expensive, and the transmitted power can be subject to electromagnetic interference. Some of these limitations can be overcome by transmitting power over an optical fiber. However, unfortunately, with current conventional designs such approaches are not yet commercially viable. In addition, current approaches generally involve light at infrared wavelengths, which has certain disadvantages over visible light, or visible optical radiation, such as greater sensitivity to temperature variations in the surrounding environment.
Gallium nitride (GaN) based optoelectronic and electronic devices are of tremendous commercial importance. The best-developed of these devices include light emitting diodes (LEDs) and laser diodes, and GaN-based power diodes and transistors are becoming increasingly important. There is also interest in emerging applications. De Santi, and coauthors [Materials 11, 153 (2018)] described an application whereby electrical power is converted to optical power using a laser diode, the optical power is coupled to an optical fiber and transmitted to a remote location, then the optical power is converted back to electrical power using a photodiode. Both the laser diode and the photodiode were based on GaN-on-sapphire devices and the system performance was relatively poor. The photodiode was a particular challenge, with a reported efficiency of 17%. GaN-based solar cells have also been reported by a number of groups, typically utilizing GaN-on-sapphire structures for low power (ca. one sun) applications. Even concentrator solar cell structures, which are well known in the art for other materials systems, are only able to generate substantially lower current densities than those that are the principal focus of the current invention.
Related applications have been disclosed using GaAs-based lasers and photodiodes, at wavelengths in the near-infrared. However, due to its larger bandgap, photodiodes based on the nitrides should enable considerably higher open-circuit voltages and superior efficiencies at elevated temperatures and at high input power levels, relative to corresponding GaAs-based devices and systems.
Recently, Cardwell and D'Evelyn [US 2021/0020798, US 2021/0167231] have disclosed a number of embodiments of nitride-based photodiode structures, devices, and optical systems. The performance of nitride photodiode with Indium, Gallium, Nitride (InGaN) absorber layers can suffer from strain-induced defect generation, especially for relatively thick absorber layers or relatively high In concentrations. Such defects can reduce the external quantum efficiency, fill factor, and open circuit voltage of the photodiode. Under monochromatic illumination, the power conversion efficiency (PCE) can be expressed as a product of the zero-bias external quantum efficiency (EQE), the fill factor (FF), and eVoc/hν, where Voc represents the open circuit voltage, e represents the electron charge, and hν represents the photon energy. Further improvements are highly desirable.
In an example, the present invention provides a photodiode device. The optical device has a gallium and nitrogen containing substrate member having a backside surface and an upper surface. The device has an N-type gallium and nitrogen containing material having a silicon dopant overlying the upper surface, the N-type gallium and nitrogen containing material being configured as a buffer material. In an example, the buffer material has a thickness ranging from about 0.5 micrometer to one and a half micrometer. The device has a superlattice (SL) indium gallium nitrogen containing material overlying the N-type gallium and nitrogen containing material. The superlattice comprises a plurality of indium gallium nitrogen containing material layers and gallium and nitrogen containing material layers. The superlattice is a periodic structure that has twenty-five to eighty indium gallium nitrogen containing material layers and gallium and nitrogen containing material layers. The device has a lower barrier (LB) indium gallium nitrogen containing material overlying the SL indium gallium nitrogen containing material. The LB material has an indium concentration ranging from zero to four percent. The LB material has a thickness ranging from 6 to 14 nanometers. In an example, the device has a plurality of quantum well regions ranging from 30 to 50 quantum wells overlying the LB indium gallium nitrogen containing material. Each of the quantum wells has an indium gallium nitride material having a thickness of 2.0 nanometers to 4.0 nanometers, and an indium concentration ranging from ten percent to 14 percent, and a gallium nitride material having a thickness of 1.0 nanometers to 2.5 nanometers. In an example, the plurality of quantum well regions is in an undoped state. The device has an upper barrier layer, including indium gallium nitrogen containing material overlying the plurality of quantum well regions. The indium gallium nitride in the upper barrier layer has a concentration ranging from zero to four percent, and a thickness of 4 nanometers to 10 nanometers. In an example, the upper barrier material is in an undoped state. The device has an upper cladding layer, including gallium nitrogen containing material overlying the upper barrier layer. The upper cladding layer gallium and nitrogen containing material comprises a magnesium dopant material having a concentration 8×1019 atoms/cm3 to 6×1020 atoms/cm3, and a thickness of sixteen nanometers to twenty-four nanometers. The device has a P-type gallium and nitrogen containing material overlying the upper cladding layer indium, gallium, and nitrogen containing material. The P-type material is a cap material. In an example, the device has a P-type contact comprises gallium and nitrogen material having a magnesium dopant material. In an example, the P-type contact is in electrical and physical contact with the P-type gallium and nitrogen containing material.
In an example, the present invention provides a photodiode device. The device has a gallium and nitrogen containing substrate member having a backside surface and an upper surface. The device has an absorber layer comprising a plurality of quantum well regions overlying the upper surface. The device has a plurality of hexagonal shaped pyramid structures spatially disposed along the backside surface. In an example, each of the hexagonal shaped pyramid structures has a height ranging from about 0.3 micrometer to about 30 micrometers, and a base ranging from about 0.3 micrometer to 30 micrometer. In an example, each of the hexagonal shaped pyramid structures extends from a crystalline structure of the gallium and nitrogen containing substrate member, and has an irregularity in size ranging from 0% to 50%, but can be others. In an example, the device has an interior region (typically planar in shape) disposed between a pair of the plurality of hexagonal shaped pyramid structures. The device has a plurality of nanodots spatially disposed overlying the interior region and overlying a surface region of each of the hexagonal shaped pyramid structures and configured to direct electromagnetic radiation having a wavelength ranging from 360 to 500 nanometers the absorber layer to increase an absorption of the radiation into the absorber layer, and thereby coupling additional radiation into the absorber layer.
Disclosed herein is a nitride photodiode that, when illuminated with one or more wavelengths between 360 nm and 500 nm at a power density >1 W/cm2, has a positive fill factor temperature coefficient in one or more temperature intervals above −50° C., a fill factor >70% at one or more temperatures above −50° C., and a power conversion efficiency >40% at one or more temperatures above −50° C.
So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only exemplary embodiments and are therefore not to be considered limiting of its scope, and may admit to other equally effective embodiments.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.
According to the present disclosure, techniques related to manufacturing and applications of power photodiode structures and devices based on group-III metal nitride and gallium-based substrates are provided. More specifically, embodiments of the disclosure include techniques for fabricating photodiode devices comprising one or more of GaN, AlN, InN, InGaN, AlGaN, and AlInGaN, structures and devices. Certain aspects of this invention may also extend to other material systems. Such structures or devices can be used for a variety of applications including optoelectronic devices, photodiodes, power-over-fiber receivers, and others.
As noted previously, lasers and photodiodes are better developed in the GaAs material system. One of the key differences in materials properties between the arsenide and nitride systems is that the bandgap may be varied readily with minimal impact on lattice constant in the case of the arsenides, e.g., via AlGaAs, but not in the case of the nitrides. Traditional photodiode package architectures incorporating nitride absorber layers may require an absorber layer thickness on the order of several hundred nanometers to absorb the large majority of the incident light. Assuming an absorber layer absorption coefficient of 1×105 cm−1, the light absorbed in a single pass is approximately 39%, 63%, 87%, 95%, and 98% for thicknesses of 50, 100, 200, 300, and 400 nm, respectively. In the case of the nitrides, such a thickness of InGaN, with sufficient indium (In) to efficiently absorb blue or violet light, may be too strained to avoid relaxation by dislocation generation or by cracking, which will reduce the electrical performance of the formed device. Cardwell and D'Evelyn [US 2021/0020798, US 2021/0167231] disclosed an approach to circumvent this problem, involving delivering electromagnetic radiation along long optical paths through an absorber layer to achieve near-100% optical absorption even when a relatively thin absorber layer containing power photodiode structure is provided. Additional benefits of their approach include excellent heat dissipation, zero or very low grid shadow losses, and long effective minority carrier lifetimes. Here, the effective minority carrier lifetime includes photon recycling, defined as reabsorption of photons emitted by the absorber layer. The term “light” and “optical radiation” are often used herein interchangeably and are both intended to generally describe electromagnetic radiation at one or more wavelengths unless otherwise noted in the context of the discussion.
Many of the embodiments disclosed by Cardwell and D'Evelyn [US 2021/0020798, US 2021/0167231] utilize multiple optical paths through the device layers via an optical cavity, in order to obtain the desired power conversion efficiency (PCE). The present inventors have discovered that a subset of these structures, together with a number of additions, refinements, and/or improved structures, yield excellent PCE with only two passes through the device layers and provide surprising benefits in the performance of the devices at elevated temperature. In particular, the inventive structures enable power photodiodes in which the temperature coefficients of the fill factor (FF), external quantum efficiency (EQE), and power conversion efficiency (PCE) are all positive. The inventors are not aware of any previously-disclosed power photodiode structures or devices that have all these properties.
In particular, the use of multiple-quantum-well (MQW) absorber layers, also known as active regions or active layers, with (Al)InGaN wells and (Al)(In)GaN barriers between wells and surrounding the absorber region in nitride photodiodes can delay the on-set of strain-induced defect generation, and thereby enable greater total thickness of absorbing (Al)InGaN in the absorber region, or higher indium (In) fraction in the absorbing layers for a given absorber thickness. However, the presence of barrier layers can impede the collection of photogenerated carriers from the absorber region, leading to degradation of the fill factor, especially at elevated input optical power densities. This carrier collection problem can be exacerbated by built-in polarization fields generated in the nitrides. It has been found that tuning the photodiode epitaxial structure for a given photodiode operating temperature, input wavelength, and input power density/distribution in such a way that the fill factor and the power conversion efficiency have positive temperature coefficients near the photodiode operating temperature can maximize the photodiode power conversion efficiency, even with just a two-pass device architecture. The tuning of the photodiode epitaxial structure has included optimizing the thickness and composition of well and barrier layers, the thickness and composition of a superlattice layer, doping levels in and thicknesses of dopant, cladding, and contact layers, and the like.
A power nitride photodiode that efficiently converts optical energy to electrical energy and can operate at elevated temperatures is suitable for applications requiring high temperature operation where more traditional, lower bandgap photodiodes or photovoltaics are more substantially degraded by elevated temperatures. Additionally, the capability of nitride photodiodes to maintain high efficiency at elevated temperatures and power levels can enable packaged photodiode modules with higher power densities without requiring active cooling. Power nitride photodiodes can be used in power-over-fiber or power-over-air systems. Such systems may have applications in automotive, aviation, lighting, etc.
The power conversion efficiency (PCE) η of a power photodiode may be written as η=Vmp×Imp/Pin, where Pin is the input radiative power, Vmp is the voltage at the maximum obtainable power and Imp is the current at the maximum obtainable power. Another way of expressing the PCE is η=Voc×Isc× FF/Pin, as illustrated schematically in
Relative to prior art photodiodes designed for much lower photon fluxes, mostly fabricated using GaN-on-sapphire structures, the inventive photodiodes, including GaN-on-GaN structures, feature high conversion efficiency due to careful optimization of the composition and doping of the semiconductor layers and to large area p-side electrical contacts with high reflectivity for use with a two-reflection excitation architecture and with very low contact resistance to minimize lateral ohmic losses at high current densities. In certain embodiments, the current photodiode structures are designed for applications where illumination is provided by a single laser or multiple lasers and enters the structure though an edge or through an aperture. In certain embodiments, the laser light is coupled into an aperture formed in the photodiode structure using optical fibers, lenses, or waveguides. In certain embodiments, the inventive photodiode structures further incorporate a much lower dislocation density, with longer minority carrier diffusion lengths to enable higher currents plus longer minority carrier lifetimes to achieve higher open circuit voltages and fill factors. In addition, the inventive devices may include electrically conductive substrates, enabling vertical transport in vertically oriented power devices for a simpler design and reduced series resistance, and transparent substrates with a very similar refractive index of that of the absorber layers, minimizing optical losses. For example, as illustrated in
Large-area surface 102 may have a maximum dimension between about 0.2 millimeter and about 600 millimeters and a minimum dimension between about 0.2 millimeter and about 600 millimeters and substrate 101 may have a thickness between about 10 micrometers and about 10 millimeters, or between about 100 micrometers and about 2 millimeters. In certain embodiments, substrate 101 is substantially circular, with one or more orientation flats or notches. In alternative embodiments, substrate 101 is substantially rectangular. In certain embodiments, large-area surface 102 has a maximum diametral dimension or rectangular-edge dimension of about 50 mm, 100 mm, 125 mm, 150 mm, 200 mm, 250 mm, 300 mm, or 450 mm. The variation in the crystallographic orientation of the large-area surface 102 may be less than about 5 degrees, less than about 2 degrees, less than about 1 degree, less than about 0.5 degrees, less than about 0.2 degrees, less than about 0.1 degrees, or less than about 0.05 degrees relative to the average crystallographic orientation of the large area surface.
Large-area surface 102 of substrate 101 may have a threading dislocation density less than about 1010 cm−2, less than about 109 cm−2, less than about 108 cm−2, less than about 107 cm−2, less than about 106 cm−2, less than about 105 cm−2, less than about 104 cm−2, less than about 103 cm−2, or less than about 102 cm−2. Large-area surface 102 of substrate 101 may have a stacking-fault concentration below about 104 cm−1, below about 103 cm−1, below about 102 cm−1, below about 10 cm−1 or below about 1 cm−1. Large-area surface 102 of substrate 101 may have a symmetric x-ray rocking curve full width at half maximum (FWHM) less than about 500 arcsec, less than about 300 arcsec, less than about 200 arcsec, less than about 100 arcsec, less than about 50 arcsec, less than about 35 arcsec, less than about 25 arcsec, or less than about 15 arcsec. Large-area surface 102 of substrate 101 may have a crystallographic radius of curvature greater than 0.1 meter, greater than 1 meter, greater than 10 meters, greater than 100 meters, or greater than 1000 meters, in at least one or at least two independent or orthogonal directions. In a specific embodiment, large-area surface 102 of substrate 101 has a threading dislocation density less than about 105 cm−2, a stacking-fault concentration below about 10 cm−1, and a symmetric x-ray rocking curve full width at half maximum (FWHM) less than about 50 arcsec. The reduced dislocation density in the substrate 101, relative to most prior art photodiodes, is expected to result in a reduced dislocation density in the semiconductor layers of the photodiode and to a higher open-circuit voltage Voc and a higher efficiency at high current densities.
Substrate 101 may have a thickness between about 10 microns and about 100 millimeters, or between about 0.1 millimeter and about 10 millimeters. Substrate 101 may have a dimension, including a diameter, of at least about 5 millimeters, at least about 10 millimeters, at least about 25 millimeters, at least about 50 millimeters, at least about 75 millimeters, at least about 100 millimeters, at least about 150 millimeters, at least about 200 millimeters, at least about 300 millimeters, at least about 400 millimeters, or at least about 600 millimeters. In a specific embodiment, substrate 101 has a thickness between about 250 micrometers and about 600 micrometers, a maximum lateral dimension or diameter between about 15 millimeters and about 160 millimeters, and includes regions where the concentration of threading dislocations is less than about 104 cm−2.
In certain embodiments, substrate 101 consists of or includes a single-crystalline group-III metal nitride layer 1104 bonded to or formed on a surface of a template substrate 1101. The single-crystalline group-III metal nitride layer 1104 may include gallium. The single-crystalline group III metal nitride layer 1104 may be deposited by HVPE, by metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or the like. The single-crystalline group-III metal nitride layer 1104 may have a thickness between about 1 micrometer and about 100 micrometers, between about 2 micrometers and about 25 micrometers, or between about 3 micrometers and about 15 micrometers. In certain embodiments, the single-crystalline group-III metal nitride layer 1104 has a wurtzite crystal structure and a crystallographic orientation within 5 degrees, within 2 degrees, within 1 degree, or within 0.5 degree of (0001)+c-plane. In certain embodiments, a nucleation layer (not shown) is present at the interface between the template substrate 1101 and the single-crystalline group-III metal nitride layer 1104. In certain embodiments, the nucleation layer consists of or includes one or more of aluminum nitride, gallium nitride, and zinc oxide. In certain embodiments, the nucleation layer is deposited on the template substrate 1101 by at least one of low-temperature MOCVD, sputtering, and electron-beam evaporation. In certain embodiments, the nucleation layer has a thickness between about 1 nanometer and about 200 nanometers or between about 10 nanometers and about 50 nanometers. In certain embodiments, the substrate further includes one or more strain-management layers, for example, an AlGaN layer or a strained-layer superlattice.
In certain embodiments, one or more n-type layers 105, comprising AluInvGa1-u-vN layers, where 0≤u, v, u+v≤1, or, in a specific embodiment, GaN, is deposited on the substrate. The carrier concentration in n-type layer 105 may lie in the range between about 1016 cm−3 and 1020 cm−3. In certain embodiments, silicon, germanium, or oxygen is the n-type dopant in n-type layer 105. In certain embodiments, the n-type carrier concentration in the n-type layer 105 lies in the range between 1×1018 cm−3 and 8×1018 cm−3. A high doping level may be particularly desirable if substrate 101 has a (0001)+c-plane orientation, as piezoelectric fields may more effectively be screened for efficient carrier collection. A high doping level may also be desirable if template substrate 1101 is electrically insulating or highly resistive. The deposition may be performed using metalorganic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). In certain embodiments, n-type layer 105 has a thickness between about 0.2 micrometer and about 5 micrometers, or between about 0.5 micrometer and about 1.5 micrometers.
In certain embodiments, a strained-layer superlattice (SLS) 106 is deposited on or overlying n-type layer 105. In certain embodiments, the SLS includes or consists of alternating layers of AlInGaN, where the alternating layers have a difference in In content of between about 0.5 atomic % and about 4 atomic %, where the atomic % is expressed as a metal fraction (i.e., as a percentage of the total of In, Ga, and Al). In a specific embodiment, the SLS includes or consists of alternating layers of GaN and InGaN, with the InGaN including an In content between about 0.5 atomic % and about 4 atomic % or between about 1 atomic % and about 3 atomic %, the layer thickness is between about 0.5 nanometer and about 3 nanometers or between about 1 nanometer and about 2 nanometers and a total of between about 25 and 80 GaN/InGaN layers are included. The layers in the SLS may be doped n-type, for example, using Si, Ge, and/or O, and may include a dopant level between about 1×1018 cm−3 and about 5×1019 cm−3 or between about 2×1018 cm−3 and about 4×1018 cm−3.
In certain embodiments, a lower cladding layer 107, also referred to herein as a lower barrier layer, may be deposited on or overlying strained-layer superlattice 106. Lower cladding layer 107 may include or consist of InGaN, with 0-4 atomic % of In, and may have a doping level between about 1×1019 cm−3 and about 5×1019 cm−3. In one example, the lower cladding layer 107 includes up to about 4 atomic % of indium (In), such as between 0.1 atomic % and 4 atomic %. As noted by Cardwell and D'Evelyn, a high doping level and/or the presence of In can improve carrier transport via favorable band lineups in +c-plane-oriented device structures. A high doping level may be particularly desirable if substrate 101 has a (0001)+c-plane orientation, as piezoelectric fields may be more effectively screened for efficient carrier collection. Lower cladding layer 107 may have a thickness between about 6 nanometers and about 14 nanometers.
An absorber layer 108, also referred to herein as an active layer, may be deposited on or overlying lower cladding layer 107. Absorber layer 108 may include or consist of a multiple quantum well (MQW), including alternating layers of AlwInxGa1-w-xN well layers and AlyInzGa1-y-zN barrier layers, respectively, where 0≤w, x, y, z, w+x, y+z≤1, where w<u, y and/or x>v, z so that the bandgap of the well layer(s) is less than that of cladding layer 107, of strained-layer superlattice 106, and of n-type layer 105. The absorber layer 108 may include between 25 and 100, between 30 and 75, or between 35 and 50 quantum wells (not shown). The quantum wells may comprise InGaN well layers and GaN barrier layers. The well layers may each have a thickness between about 2 nanometers and about 5 nanometers, or between about 2.5 nanometers and about 4 nanometers. The barrier layers may each have a thickness between about 0.5 nanometer and about 2.5 nanometers, or between about 1 nanometer and about 2 nanometers. In certain embodiments, the absorber layer 108 is deposited by MOCVD, at a substrate temperature between about 700 and about 950 degrees Celsius.
In certain embodiments, the absorber layer 108 is unintentionally doped. In certain embodiments, the absorber layer 108 is n-type doped, using oxygen, silicon, or germanium, as a dopant, with a dopant concentration between about 5×1015 cm−3 and about 5×1019 cm−3, or between about 5×1016 cm−3 and about 5×1018 cm−3. In certain embodiments, the absorber layer 108 is p-type doped, using Mg as a dopant, with a dopant concentration between about 5×1015 cm−3 and about 5×1019 cm−3, or between about 5×1016 cm−3 and about 5×1018 cm−3. In some embodiments, the absorber layer 108 has a bandgap wavelength that is between about 360 and about 550 nanometers, such as a bandgap wavelength that is between about 400 nanometers and about 500 nanometers.
The composition and structure of the absorber layer 108 are chosen to provide light absorption at preselected wavelengths, for example, near 405 nanometers or near 450 nanometers. In certain embodiments, the wavelength for optimum absorption is selected to lie between about 360 nanometers and about 500 nanometers. The absorber layer 108 may be characterized by photoluminescence spectroscopy. In certain embodiments, the composition of the absorber layer 108 is chosen such that the photoluminescence spectrum has a peak that is longer in wavelength than the desired absorption wavelength of the photodiode structure 1000 by between 5 nanometers and 50 nanometers or by between 10 nanometers and 25 nanometers. In certain embodiments, the well layers contain In at between about 10 atomic % and about 14 atomic %. In certain embodiments, the quality and layer thicknesses within the absorber layer 108 are characterized by x-ray diffraction.
In certain embodiments, the absorber layer 108 is terminated by an upper barrier layer 109, which may also be referred to herein as a first upper barrier layer. Upper barrier layer 109 may consist of GaN, or InGaN, with 0-4 atomic % of indium (In). In one example, the upper barrier layer 109 includes up to about 4 atomic % of indium (In), such as between 0.1 atomic % and 4 atomic %. Upper barrier layer 109 may have a thickness between about 4 nanometers and about 10 nanometers. In certain embodiments, upper barrier layer 109 is unintentionally doped. In certain embodiments, upper barrier layer 109 has a graded composition, with the In concentration varying between a first level and a second level.
In certain embodiments, an upper cladding layer 110, which may also be referred to herein as a second upper barrier layer, is deposited on or overlying upper barrier layer 109. Upper cladding layer 110 may include or consist of heavily-Mg-doped GaN and may have a thickness between about 10 nanometers and about 30 nanometers or between about 16 nanometers and about 24 nanometers. Upper cladding layer 110 may have a Mg concentration between about 8×1019 cm−3 and about 6×1020 cm−3 or between about 1.5×1020 cm−3 and about 4×1020 cm−3.
Next, a p-type layer 111, formed of AlqInrGa1-q-rN, where 0≤q, r, q+r≤1, or of GaN, is deposited on or overlying upper cladding layer 110. The p-type layer 111 may be doped with Mg, to a level between about 1018 cm−3 and 1021 cm−3, or between about 1019 cm−3 and about 8×1019 cm−3, and may have a thickness between about 5 nanometers and about 100 nanometers or between about 25 nanometers and about 75 nanometers.
A p-contact layer 112 may then be deposited on or overlying p-type layer 111. The p-contact layer 111 may be doped with Mg, to a level between about 1019 cm−3 and 1022 cm−3, or between about 1020 cm−3 and about 6×1020 cm−3, and may have a thickness between about 2 nanometers and about 50 nanometers, between about 10 nanometers and about 25 nanometers.
The semiconductor layers, which include the n-type layer 105, the strained-layer superlattice 106, the lower cladding layer 107, the absorber layer 108, the upper barrier layer 109, the upper cladding layer 110, the p-type layer 111, and the p-contact layer 112, are epitaxial and have the same crystallographic orientation, to within about two degrees, within about one degree, within about 0.5 degree, or within about 0.2 degree, as the crystallographic orientation of large-area surface 102 of substrate 101, have a very high crystalline quality, comprise nitrogen, and may have a surface dislocation density below 109 cm−2. The semiconductor layers may have a surface dislocation density below 1010 cm−2, below 109 cm−2, below 108 cm−2, below 107 cm−2 below 106 cm−2, below 105 cm−2, below 104 cm−2, below 103 cm−2, or below 102 cm−2. The semiconductor layers may have a dislocation density that is within a factor of five, a factor of two, or a factor of 1.2 of the dislocation density of large-area surface 102.
In a specific embodiment, the semiconductor layers have an orientation within five degrees of (0001) c-plane and the FWHM of the 0002 x-ray rocking curve of the top surface is below 300 arc sec, below 100 arc sec, or below 50 arc sec.
In order to maximize the efficiency of a packaged photodiode, it may be important to maximize the reflectivity of the top side of the photodiode structure 1000 and also to minimize the electrical resistance of the contacts in the photodiode structure. Referring again to
Referring again to
In certain embodiments, particularly embodiments where the n-side reflective electrical contact includes aluminum, in order to reduce the contact resistance of the n-side reflective electrical contact, the back side of substrate 101 is processed by reactive ion etching (RIE) using a chlorine-containing gas or plasma. In one specific embodiment, the chlorine-containing gas or plasma includes SiCl4. In certain embodiments, in order to reduce the contact resistance of the n-side reflective electrical contact, further cleaning steps are performed. In certain embodiments, the further cleaning steps include or consist of one or more of treatment by a mineral acid, such as hydrochloric acid, nitric acid, or aqua regia, a buffered oxide etch, by dry etching, or by treatment with a plasma, such as an argon plasma.
In certain embodiments, for example, where substrate 101 is a template that includes an insulating template substrate 1101, an n-side electrical contact is deposited instead on a portion of at least one of n-type layer 105, strained-layer superlattice (SLS) 106, or lower cladding layer 107, for example, at the bottom of a trench (not shown) that is formed through absorber layer 108.
The photodiode structures 1000 described in the present disclosure are intended for use in a photodiode die that is disposed within a packaged photodiode assembly, and, typically, includes a single-reflection geometry. The photodiode die, or simply “die”, typically includes a portion of a substrate that is formed by a singulation, cleaving or other similar process and includes the various photodiode structure 1000 elements described herein. In some embodiments, a photodiode die includes a photodiode structure having aperture 120 (
In certain embodiments, at least a portion of backside surface 130 of the substrate 101 is roughened, to facilitate light entry into the device structure and to help trap the light within it, as shown schematically in
Referring again to
In certain embodiments, a chip or die that includes a photodiode structure such as that described above is incorporated into an optical cavity, many examples of which are described by Cardwell and D'Evelyn. In one specific embodiment, the optical cavity may include a tapered hole within a silver foil or plate, as shown schematically in
In the inventive structures described herein, the absorber layer 108 includes a large number of relatively thin well and barrier layers, with the large number enabling quite robust external quantum efficiencies, even with only two optical passes through the absorber layer, and the thinness of the MQW layers (specifically, the barrier layers) serves a dual purpose of strain management and maintenance of high carrier collection efficiency and improved fill factor. This combination, together with the addition of an upper barrier layer, which the inventors have found improves device performance, is found to give rise to the unanticipated, and surprising, result that each of the fill factor, the external quantum efficiency, and the power conversion efficiency increase over the temperature range between 25 degrees Celsius and 80 degrees Celsius. In certain embodiments, the fill factor increases by at least 2%, at least 3%, at least 4%, at least 5%, or at least 6% as the temperature of the semiconductor layers within the photodiode device area is increased from 25 degrees Celsius to 80 degrees Celsius. In certain embodiments, the external quantum efficiency increases by at least 1%, at least 2%, or at least 3% as the temperature of the semiconductor layers within the photodiode device area is increased from 25 degrees Celsius to 80 degrees Celsius. In certain embodiments, the power conversion efficiency increases by at least 2%, at least 3%, at least 4%, at least 5%, or at least 6% as the temperature of the semiconductor layers within the photodiode device area is increased from 25 degrees Celsius to 80 degrees Celsius. In certain embodiments, each of the fill factor, the external quantum efficiency, and the power conversion efficiency increase monotonically over the temperature range between 25 degrees Celsius and 70 degrees Celsius. Without wishing to be bound by theory, the inventors believe that this phenomenon is due to phonon-assisted tunneling.
In other words, phonons within the semiconductor layers are able to assist carriers in surmounting the barrier heights created by the various barrier layers, including barrier layers within the multiple quantum well within the absorber layer 108 and the upper barrier layer 109. The inventors further believe that the SLS, positioned below the lower cladding layer, helps reduce the concentration of point defects, such as Shockley-Read-Hall defects, that can lead to non-radiative recombination, within the absorber layer and within the cladding layers, thereby increasing the EQE.
Embodiments provided by the present disclosure are further illustrated by reference to the following comparative examples and exemplary process examples. It will be apparent to those skilled in the art that many modifications, both to materials, and methods, may be practiced without departing from the scope of the disclosure.
An epitaxial structure similar to
Hexagonal pyramidal structures are then formed on the backside of the substrate, by exposure to a 2.3 molar solution of KOH at a temperature of approximately 60 degrees Celsius for approximately one hour. The morphology of the hexagonal pyramidal structures is similar to that shown in
Hexagonal pyramidal structures similar to those shown in
A device structure similar to that described in Example 1 and shown in
The electrical and photoelectrical characteristics of the device are measured using a setup similar to that shown schematically in
The die or chip described above undergoes fiber-illuminated current-voltage testing using a test configuration as shown in
While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
This patent application claims the benefit of U.S. Provisional Patent Application No. 63/356,231, filed Jun. 28, 2022, and U.S. Provisional Patent Application No. 63/500,862, filed May 8, 2023, each of which is incorporated by reference herein.
| Number | Date | Country | |
|---|---|---|---|
| 63500862 | May 2023 | US | |
| 63356231 | Jun 2022 | US |
