Claims
- 1. A pillar CMOS FET circuit comprising:A silicon substrate; a single undivided unitary pillar of epitaxial silicon extending from a base at said substrate to a distal end; said pillar having opposite sides with an N well on one side thereof and a P well on the other side thereof in contact with said N well; an N+ diffusion in said P well at said distal end of said pillar and a P+ diffusion in the N well at said distal end of said pillar; an N well in said substrate in contact with said N well in said pillar and a P well in said substrate in contact with said P well in said pillar; a N+ diffusion in said P well in said substrate and a P+ diffusion in said N well in said substrate; and gate insulator and gate electrodes on said opposite sides of said pillar.
- 2. The invention is defined in claim 1 wherein said N+ diffusion in said P well in said substrate and said P+ diffusion in said N well each extend at least to the base of the epitaxial silicon pillar.
- 3. The invention is defined in claim 1 wherein a mask material of dielectric material is disposed on said substrate, and a plurality of wiring channels are formed in said mask material, and polysilicon is deposited in said wiring channels to connect said FET device as an inverter.
- 4. The invention as defined in claim 1 wherein said gate electrodes are polysilicon.
RELATED APPLICATIONS
This application is a divisional of application Ser. No. 09/009,456, filed Jan. 20,1998, now U.S. Pat. No. 6,100,123.
US Referenced Citations (11)
Non-Patent Literature Citations (2)
Entry |
IBM Technical Disclosure Bulletin, “Structures and Layout of a New Self-Aligned Pilar CMOS Logic Gate and SRAM Cell,” vol. 32, No. 9A, Feb. 1990, pp. 338-340.* |
IBM Technical Disclosure Bulletin, “New Self-Aligned Pillar CMOS Technology-Structures and Fabrication Methods,” vol. 32, No. 8A, Jan. 1990, pp. 144-145. |