Patent Application
20250078727
The present disclosure relates to the technical field of display, in particular to a pixel circuit, a method for driving the pixel circuit, a display substrate and a display device.
Silicon-based light emitting diode display devices are also called silicon-based LED display devices. Silicon-based LED display devices are manufactured by mature Complementary Metal Oxide Semiconductor (CMOS for short) integrated circuit process, which has advantages such as small size, high Pixels Per Inch (PPI for short), high refresh rate, etc. It is widely used in various fields such as medicine, military affairs, aerospace and consumer electronics, especially in fields such as wearable devices, Virtual Reality (VR for short) or Augmented Reality (AR for short) near-eye display.
The following is a summary of subject matter described herein in detail. The summary is not intended to limit the protection scope of claims.
In a first aspect, the present disclosure provides a pixel circuit including: a drive circuit and a light emitting element connected in series between a first power supply terminal and a third power supply terminal; the drive circuit is configured to provide a drive current and control a time length of conduction of a current path between the first power supply terminal and the third power supply terminal; the light emitting element is configured to receive the drive current in the current path and emit light; the drive circuit includes a drive control sub-circuit, a light emitting control sub-circuit and a time-length control sub-circuit.
The drive control sub-circuit is electrically connected with a first scan signal terminal, a first data signal terminal, a first node and a second node respectively, and is configured to provide the drive current to the first node under control of the first scan signal terminal, the first data signal terminal and the second node.
The light emitting control sub-circuit is electrically connected with a light emitting signal terminal, the first power supply terminal and the second node respectively, and is configured to provide a signal of the first power supply terminal to the second node under control of the light emitting signal terminal.
The time-length control sub-circuit is electrically connected with a second scan signal terminal, a second data signal terminal, a second power supply terminal, the first node and a third node respectively, and is configured to provide a signal of the first node to the third node under control of the second scan signal terminal and the second data signal terminal.
The light emitting element is electrically connected with the third node and the third power supply terminal respectively.
In some possible implementation modes, when a signal of the first scan signal terminal is an effective level signal, a signal of the second scan signal terminal is an effective level signal, and a signal of the light emitting signal terminal is an ineffective level signal.
When the signal of the light emitting signal terminal is an effective level signal, the signals of the first scan signal terminal and the second scan signal terminal are ineffective level signals.
In some possible implementation modes, the drive control sub-circuit is further electrically connected with a third scan signal terminal, is configured to provide a drive current to the first node under control of the first scan signal terminal, the third scan signal terminal, the first data signal terminal and the second node.
When the signal of the first scan signal terminal is an effective level signal, a signal of the third scan signal terminal is an effective level signal.
When the signal of the light emitting signal terminal is an effective level signal, the signal of the third scan signal terminal is an ineffective level signal.
In some possible implementation modes, the pixel circuit further including: a reset sub-circuit and/or a node control sub-circuit.
The reset sub-circuit is electrically connected with a reset signal terminal, an initial signal terminal and the third node respectively, and is configured to provide a signal of the initial signal terminal to the third node under control of the reset signal terminal.
The node control sub-circuit is electrically connected with the first scan signal terminal, a control signal terminal and the first node respectively, and is configured to provide a signal of the control signal terminal to the first node or read the signal of the first node to the control signal terminal under control of the first scan signal terminal, wherein a voltage value of the signal of the control signal terminal is constant.
In some possible implementation modes, when a signal of the reset signal terminal is an effective level signal, signals of the first scan signal terminal, the second scan signal terminal and the light emitting signal terminal are ineffective level signals.
When the signal of the first scan signal terminal is an effective level signal, the signal of the reset signal terminal is an ineffective level signal.
When the signal of the light emitting signal terminal is an effective level signal, the signal of the reset signal terminal is an ineffective level signal.
In some possible implementation modes, the drive control sub-circuit includes: a first transistor, a second transistor, and a first capacitor.
A control electrode of the first transistor is electrically connected with a fourth node, a first electrode of the first transistor is electrically connected with the second node, and a second electrode of the first transistor is electrically connected with the first node.
A control electrode of the second transistor is electrically connected with the first scan signal terminal, a first electrode of the second transistor is electrically connected with the first data signal terminal, and a second electrode of the second transistor is electrically connected with the fourth node.
One plate of the first capacitor is electrically connected with the fourth node, and the other plate of the first capacitor is electrically connected with a fourth power supply terminal or the first node.
In some possible implementation modes, the drive control sub-circuit includes: a first transistor, a second transistor, a third transistor, and a first capacitor.
A control electrode of the first transistor is electrically connected with a fourth node, a first electrode of the first transistor is electrically connected with the second node, and a second electrode of the first transistor is electrically connected with the first node.
A control electrode of the second transistor is electrically connected with the first scan signal terminal, a first electrode of the second transistor is electrically connected with the first data signal terminal, and a second electrode of the second transistor is electrically connected with the fourth node.
A control electrode of the third transistor is electrically connected with the third scan signal terminal, a first electrode of the third transistor is electrically connected with the first data signal terminal, and a second electrode of the third transistor is electrically connected with the fourth node.
One plate of the first capacitor is electrically connected with the fourth node, and the other plate of the first capacitor is electrically connected with a fourth power supply terminal or the first node.
The second transistor and the third transistor are of different transistor types.
In some possible implementation modes, the light emitting control sub-circuit includes a fourth transistor.
A control electrode of the fourth transistor is electrically connected with the light emitting signal terminal, a first electrode of the fourth transistor is electrically connected with the first power supply terminal, and a second electrode of the fourth transistor is electrically connected with the second node.
In some possible implementation modes, the time-length control sub-circuit includes a fifth transistor, a sixth transistor, and a second capacitor.
A control electrode of the fifth transistor is electrically connected with a fifth node, a first electrode of the fifth transistor is electrically connected with the first node, and a second electrode of the fifth transistor is electrically connected with the third node.
A control electrode of the sixth transistor is electrically connected with the second scan signal terminal, a first electrode of the sixth transistor is electrically connected with the second data signal terminal, and a second electrode of the sixth transistor is electrically connected with the fifth node.
One plate of the second capacitor is electrically connected with the fifth node, and another plate of the second capacitor is electrically connected with the second power supply terminal.
In some possible implementation modes, the reset sub-circuit includes a seventh transistor.
A control electrode of the seventh transistor is electrically connected with the reset signal terminal, a first electrode of the seventh transistor is electrically connected with the initial signal terminal, and a second electrode of the seventh transistor is electrically connected with the third node.
In some possible implementation modes, the node control sub-circuit includes an eighth transistor.
A control electrode of the eighth transistor is electrically connected with the first scan signal terminal, a first electrode of the eighth transistor is electrically connected with the control signal terminal, and a second electrode of the eighth transistor is electrically connected with the first node.
In some possible implementation modes, the drive control sub-circuit includes: a first transistor, a second transistor, and a first capacitor, the light emitting control sub-circuit includes: a fourth transistor, and the time-length control sub-circuit includes: a fifth transistor, a sixth transistor, and a second capacitor.
A control electrode of the first transistor is electrically connected with a fourth node, a first electrode of the first transistor is electrically connected with the second node, and a second electrode of the first transistor is electrically connected with the first node.
A control electrode of the second transistor is electrically connected with the first scan signal terminal, a first electrode of the second transistor is electrically connected with the first data signal terminal, and a second electrode of the second transistor is electrically connected with the fourth node.
A control electrode of the fourth transistor is electrically connected with the light emitting signal terminal, a first electrode of the fourth transistor is electrically connected with the first power supply terminal, and a second electrode of the fourth transistor is electrically connected with the second node.
A control electrode of the fifth transistor is electrically connected with a fifth node, a first electrode of the fifth transistor is electrically connected with the first node, and a second electrode of the fifth transistor is electrically connected with the third node.
A control electrode of the sixth transistor is electrically connected with the second scan signal terminal, a first electrode of the sixth transistor is electrically connected with the second data signal terminal, and a second electrode of the sixth transistor is electrically connected with the fifth node.
One plate of the first capacitor is electrically connected with the fourth node, and the other plate of the first capacitor is electrically connected with a fourth power supply terminal or the first node.
One plate of the second capacitor is electrically connected with the fifth node, and the other plate of the second capacitor is electrically connected with the second power supply terminal.
In some possible implementation modes, the drive control sub-circuit includes: a first transistor, a second transistor, a third transistor, and a first capacitor, the light emitting control sub-circuit includes: a fourth transistor, and the time-length control sub-circuit includes: a fifth transistor, a sixth transistor, and a second capacitor.
A control electrode of the first transistor is electrically connected with a fourth node, a first electrode of the first transistor is electrically connected with the second node, and a second electrode of the first transistor is electrically connected with the first node.
A control electrode of the second transistor is electrically connected with the first scan signal terminal, a first electrode of the second transistor is electrically connected with the first data signal terminal, and a second electrode of the second transistor is electrically connected with the fourth node.
A control electrode of the third transistor is electrically connected with a third scan signal terminal, a first electrode of the third transistor is electrically connected with the first data signal terminal, and a second electrode of the third transistor is electrically connected with the fourth node.
A control electrode of the fourth transistor is electrically connected with the light emitting signal terminal, a first electrode of the fourth transistor is electrically connected with the first power supply terminal, and a second electrode of the fourth transistor is electrically connected with the second node.
A control electrode of the fifth transistor is electrically connected with a fifth node, a first electrode of the fifth transistor is electrically connected with the first node, and a second electrode of the fifth transistor is electrically connected with the third node.
A control electrode of the sixth transistor is electrically connected with the second scan signal terminal, a first electrode of the sixth transistor is electrically connected with the second data signal terminal, and a second electrode of the sixth transistor is electrically connected with the fifth node.
One plate of the first capacitor is electrically connected with the fourth node, and the other plate of the first capacitor is electrically connected with the fourth power supply terminal or the first node.
One plate of the second capacitor is electrically connected with the fifth node, and the other plate of the second capacitor is electrically connected with the second power supply terminal.
The second transistor and the third transistor are of opposite transistor types.
In some possible implementation modes, the pixel circuit further including: a reset sub-circuit and/or a node control sub-circuit, the drive control sub-circuit includes a first transistor, a second transistor and a first capacitor, the light emitting control sub-circuit includes a fourth transistor, the time-length control sub-circuit includes a fifth transistor, a sixth transistor and a second capacitor, the reset sub-circuit includes a seventh transistor, and the node control sub-circuit includes an eighth transistor.
A control electrode of the first transistor is electrically connected with a fourth node, a first electrode of the first transistor is electrically connected with the second node, and a second electrode of the first transistor is electrically connected with the first node.
A control electrode of the second transistor is electrically connected with the first scan signal terminal, a first electrode of the second transistor is electrically connected with the first data signal terminal, and a second electrode of the second transistor is electrically connected with the fourth node.
A control electrode of the fourth transistor is electrically connected with the light emitting signal terminal, a first electrode of the fourth transistor is electrically connected with the first power supply terminal, and a second electrode of the fourth transistor is electrically connected with the second node.
A control electrode of the fifth transistor is electrically connected with a fifth node, a first electrode of the fifth transistor is electrically connected with the first node, and a second electrode of the fifth transistor is electrically connected with the third node.
A control electrode of the sixth transistor is electrically connected with the second scan signal terminal, a first electrode of the sixth transistor is electrically connected with the second data signal terminal, and a second electrode of the sixth transistor is electrically connected with the fifth node.
A control electrode of the seventh transistor is electrically connected with a reset signal terminal, a first electrode of the seventh transistor is electrically connected with an initial signal terminal, and a second electrode of the seventh transistor is electrically connected with the third node.
A control electrode of the eighth transistor is electrically connected with the first scan signal terminal, a first electrode of the eighth transistor is electrically connected with a control signal terminal, and a second electrode of the eighth transistor is electrically connected with the first node.
One plate of the first capacitor is electrically connected with the fourth node, and the other plate of the first capacitor is electrically connected with a fourth power supply terminal or the first node; when the pixel circuit includes a node control sub-circuit, the other plate of the first capacitor is electrically connected with the first node.
One plate of the second capacitor is electrically connected with the fifth node, and the other plate of the second capacitor is electrically connected with the second power supply terminal.
In some possible implementation modes, the pixel circuit further including: a reset sub-circuit and/or a node control sub-circuit, the drive control sub-circuit includes: a first transistor, a second transistor, a third transistor and a first capacitor, the light emitting control sub-circuit includes a fourth transistor, the time-length control sub-circuit includes a fifth transistor, a sixth transistor and a second capacitor, the reset sub-circuit includes a seventh transistor, and the node control sub-circuit includes an eighth transistor.
A control electrode of the first transistor is electrically connected with a fourth node, a first electrode of the first transistor is electrically connected with the second node, and a second electrode of the first transistor is electrically connected with the first node.
A control electrode of the second transistor is electrically connected with the first scan signal terminal, a first electrode of the second transistor is electrically connected with the first data signal terminal, and a second electrode of the second transistor is electrically connected with the fourth node.
A control electrode of the third transistor is electrically connected with a third scan signal terminal, a first electrode of the third transistor is electrically connected with the first data signal terminal, and a second electrode of the third transistor is electrically connected with the fourth node.
A control electrode of the fourth transistor is electrically connected with the light emitting signal terminal, a first electrode of the fourth transistor is electrically connected with the first power supply terminal, and a second electrode of the fourth transistor is electrically connected with the second node.
A control electrode of the fifth transistor is electrically connected with a fifth node, a first electrode of the fifth transistor is electrically connected with the first node, and a second electrode of the fifth transistor is electrically connected with the third node.
A control electrode of the sixth transistor is electrically connected with the second scan signal terminal, a first electrode of the sixth transistor is electrically connected with the second data signal terminal, and a second electrode of the sixth transistor is electrically connected with the fifth node.
A control electrode of the seventh transistor is electrically connected with a reset signal terminal, a first electrode of the seventh transistor is electrically connected with an initial signal terminal, and a second electrode of the seventh transistor is electrically connected with the third node.
A control electrode of the eighth transistor is electrically connected with the first scan signal terminal, a first electrode of the eighth transistor is electrically connected with a control signal terminal, and a second electrode of the eighth transistor is electrically connected with the first node.
One plate of the first capacitor is electrically connected with the fourth node, and the other plate of the first capacitor is electrically connected with a fourth power supply terminal or the first node; when the pixel circuit includes the node control sub-circuit, the other plate of the first capacitor is electrically connected with the first node.
One plate of the second capacitor is electrically connected with the fifth node, and the other plate of the second capacitor is electrically connected with the second power supply terminal.
The second transistor and the third transistor are of opposite transistor types.
In some possible implementation modes, the light emitting element includes: a miniature light emitting diode or a mini light emitting diode.
In a second aspect, the present disclosure further provides a display substrate, which includes a display area provided with multiple pixels and a non-display area provided on and surrounding at least one side of the display area, and the pixel circuit described above is provided in the pixels.
In some possible implementation modes, the pixel circuit includes: a node control sub-circuit and the display substrate further includes: a first chip connected with a control signal terminal and a second chip connected with the first data signal terminal.
The first chip is configured to provide a signal to the control signal terminal in a display stage, read the signal of the control signal terminal in a non-display stage, and is further configured to obtain a threshold voltage of a first transistor according to the signal of the control signal terminal, generate a control signal according to the threshold voltage of the first transistor, and send the control signal to the second chip.
The second chip provides a signal to the first data signal terminal according to the control signal.
In a third aspect, the present disclosure further provides a display device, including the display substrate described above.
In a fourth aspect, the present disclosure further provides a method for driving a pixel circuit, which is configured to drive the pixel circuit described above, the pixel circuit is located in a display substrate, the display substrate has a display stage, the display stage includes multiple display frames, the display frame includes at least one display sub-frame; the at least one display sub-frame includes a light emitting data writing stage and a light emitting stage, and the method includes:
In the light emitting data writing stage, the drive control sub-circuit providing a drive current to the first node under control of the first scan signal terminal, the first data signal terminal and the second node, and the time-length control sub-circuit providing the signal of the first node to the third node under control of the second scan signal terminal and the second data signal terminal.
In the light emitting stage, the light emitting control sub-circuit providing the signal of the first power supply terminal to the second node under control of the light emitting signal terminal.
In some possible implementation modes, the pixel circuit further includes: a reset sub-circuit, the display sub-frame further includes: a reset stage, and the method further includes:
In the reset stage, the reset sub-circuit providing a signal of an initial signal terminal to the third node under control of a reset signal terminal.
In some possible implementation modes, the pixel circuit further includes a node control sub-circuit, the display substrate further includes a non-display stage, the non-display stage includes a compensation data writing stage and a compensation stage, the method further including:
In the light emitting data writing stage and the compensation data writing stage, the node control sub-circuit providing a signal of a control signal terminal to the first node under control of the first scan signal terminal
In the compensation stage, the node control sub-circuit reading the signal of the first node to the control signal terminal under control of the first scan signal terminal.
Other aspects may be understood upon reading and understanding of the drawings and the detailed description.
Accompanying drawings are used for providing understanding of technical solutions of the present disclosure, and form a part of the specification. They are used for explaining the technical solutions of the present disclosure together with the embodiments of the present disclosure, but do not form a limitation on the technical solutions of the present disclosure.
To make objectives, technical solutions, and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It is to be noted that implementation modes may be implemented in multiple different forms. Those of ordinary skills in the art may easily understand such a fact that implementations modes and contents may be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be explained as being limited to contents described in following implementation modes only. The embodiments in the present disclosure and features in the embodiments may be combined randomly with each other if there is no conflict. In order to keep following description of the embodiments of the present disclosure clear and concise, detailed descriptions about part of known functions and known components are omitted in the present disclosure. The drawings of the embodiments of the present disclosure only involve structures involved in the embodiments of the present disclosure, and other structures may refer to usual designs.
In the drawings, a size of each constituent element, a thickness of a layer, or a region is exaggerated sometimes for clarity. Therefore, one implementation mode of the present disclosure is not necessarily limited to the sizes, and shapes and sizes of various components in the drawings do not reflect actual scales. In addition, the drawings schematically illustrate ideal examples, and one implementation mode of the present disclosure is not limited to the shapes, numerical values, or the like shown in the drawings.
Ordinal numerals such as “first”, “second”, and “third” in the specification are set to avoid confusion between constituent elements, but not to set a limit in quantity.
In the specification, for convenience, wordings indicating orientation or positional relationships, such as “middle”, “upper”, “lower”, “front”, “back”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, and “outside”, are used for illustrating positional relationships between constituent elements with reference to the drawings, and are merely for facilitating the description of the specification and simplifying the description, rather than indicating or implying that a referred device or element must have a particular orientation and be constructed and operated in the particular orientation. Therefore, they cannot be understood as limitations on the present disclosure. The positional relationships between the constituent elements may be changed as appropriate according to directions for describing the various constituent elements. Therefore, appropriate replacements may be made according to situations without being limited to the wordings described in the specification.
In the specification, unless otherwise specified and defined explicitly, terms “mount”, “mutually connect”, and “connect” should be understood in a broad sense. A connection may be a fixed connection, a detachable connection, or an integral connection. It may be a mechanical connection or an electrical connection. It may be a direct mutual connection, or an indirect connection through middleware, or an internal communication between two components. Those of ordinary skills in the art may understand specific meanings of these terms in the present disclosure according to specific situations.
In the specification, a transistor refers to an element which includes at least three terminals, i.e., a gate electrode, a drain electrode and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain) and the source electrode (source electrode terminal, source region, or source), and a current can flow through the drain electrode, the channel region, and the source electrode. It is to be noted that, in the specification, the channel region refers to a region through which the current mainly flows.
In the specification, a first electrode may be a drain electrode, and a second electrode may be a source electrode. Or, the first electrode may be the source electrode, and the second electrode may be the drain electrode. In cases that transistors with opposite polarities are used, a current direction changes during operation of a circuit, or the like, functions of the “source electrode” and the “drain electrode” are sometimes interchangeable. Therefore, the “source electrode” and the “drain electrode” are interchangeable in the specification.
In the specification, “electrical connection” includes a case that constituent elements are connected together through an element with a certain electrical effect. The “element with the certain electrical effect” is not particularly limited as long as electrical signals may be sent and received between the connected constituent elements. Examples of the “element with the certain electrical effect” not only include electrodes and wirings, but also include switch elements such as transistors, resistors, inductors, capacitors, other elements with various functions, etc.
In the specification, “parallel” refers to a state in which an angle formed by two straight lines is above −10° and below 10°, and thus also includes a state in which the angle is above −5° and below 5°. In addition, “perpendicular” refers to a state in which an angle formed by two straight lines is above 80° and below 100°, and thus also includes a state in which the angle is above 85° and below 95°.
In the specification, a “film” and a “layer” are interchangeable. For example, a “conductive layer” may be replaced with a “conductive film” sometimes. Similarly, an “insulation film” may be replaced with an “insulation layer” sometimes.
In the present disclosure, “about” refers to that a boundary is defined not so strictly and numerical values within process and measurement error ranges are allowed.
Due to the non-uniform manufacturing process of light emitting diode elements, lighting up voltages of different light-emitting diode elements are inconsistent. In addition, electro-optic conversion characteristics (including efficiency, uniformity, color coordinates, etc.) of self-luminous elements are changed with the current, so that a display product including the light emitting diode elements performs displaying with non-uniform with a low light emitting efficiency, and a display effect of the display product is reduced.
As shown in
As shown in
In an exemplary embodiment, the first power supply terminal VDD continuously provides a high-level signal, and the second power supply terminal Vcom1 and the third power supply terminal VSS continuously provide low-level signals. Exemplarily, a voltage value of the signal of the second power supply terminal Vcom1 may be 0V, and a voltage value of the signal of the third power supply terminal VSS may be negative, for example,-2V.
In an exemplary embodiment, the light emitting element includes a first electrode and a second electrode. Exemplarily, the first electrode of the light emitting element is electrically connected with the third node N3, and the second electrode of the light emitting element is electrically connected with the third power supply terminal VSS.
In an exemplary embodiment, the light emitting element may be a miniature light emitting diode or a mini light emitting diode. A typical size (e.g. length) of the miniature light emitting diode may be less than 80 μm, e.g. 10 μm to 50 μm, and does not include a growth substrate (e.g. sapphire). A typical size (e.g. length) of the mini light emitting diode may be about 80 to 350 μm, e.g. 100 to 220 um.
The pixel circuit in the present disclosure can control a light emitting time length of the light emitting element by the time-length control sub-circuit and the light emitting control sub-circuit in an interval where photoelectric parameters of the light emitting element are relatively stable.
In an exemplary embodiment, the pixel circuit in the present disclosure may be disposed on a silicon-based substrate. Being disposed on the silicon-based substrate, the pixel circuit in the present disclosure can achieve an improved electrical stability. Because the pixel circuit disposed on the silicon-based substrate has good electrical stability, the drive circuit in the pixel circuit disposed on the silicon-based substrate does not need to be provided with an internal compensation circuit, so that an area occupied by the drive circuit can be reduced, the PPI of a display product where the pixel circuit is located can be improved, a “screen window effect” can be avoided, and a display effect of the display product where the pixel circuit is located can be improved.
The pixel circuit according to the embodiment of the present disclosure includes: a drive circuit and a light emitting element connected in series between a first power supply terminal and a third power supply terminal. The drive circuit is configured to provide a drive current and control a time length of conduction of a current path between the first power supply terminal and the third power supply terminal. The light emitting element is configured to receive the drive current in the current path and emitting light. The drive circuit includes a drive control sub-circuit, a light emitting control sub-circuit and a time-length control sub-circuit. The drive control sub-circuit is electrically connected with a first scan signal terminal, a first data signal terminal, a first node and a second node respectively, and is configured to provide the drive current to the first node under control of the first scan signal terminal, the first data signal terminal and the second node. The light emitting control sub-circuit is electrically connected with a light emitting signal terminal, the first power supply terminal and the second node respectively, and is configured to provide a signal of the first power supply terminal to the second node under control of the light emitting signal terminal. The time-length control sub-circuit is electrically connected with a second scan signal terminal, a second data signal terminal, a second power supply terminal, the first node and a third node respectively, and is configured to provide a signal of the first node to the third node under control of the second scan signal terminal and the second data signal terminal. The light emitting element is electrically connected with the third node and the third power supply terminal respectively. In the present disclosure, by providing the light emitting control sub-circuit and the time-length control sub-circuit, the light emitting time length of the light emitting element can be controlled, uniformity and light emitting efficiency of the light emitting element under low gray scale is improved, and the display effect of the display product is improved.
In an exemplary embodiment, when a signal of the first scan signal terminal Gate1 is an effective level signal, a signal of the second scan signal terminal Gate2 is an effective level signal, and a signal of the light emitting signal terminal EM is an ineffective level signal. When the signal of the light emitting signal terminal EM is an effective level signal, the signals of the first scan signal terminal Gate1 and the second scan signal terminal Gate2 are ineffective level signals.
In an exemplary embodiment, a pixel circuit is disposed in a display substrate, and the display substrate has a display stage and a non-display stage.
In an exemplary embodiment, the display stage may include multiple display frames, and each display frame includes at least one display sub-frame. The display sub-frame includes a light emitting data writing stage and a light emitting stage. The display frame in the present disclosure includes at least one display sub-frame, which can realize multi-scanning in one frame, realizes flexible control of the light emitting time length of the light emitting element, improves uniformity of the pixel circuit under low gray scale, improves the contrast, and improves the display effect of the display product.
In an exemplary embodiment, the non-display stage may include a power-on stage, a power-off stage, and an idle stage between the display stages.
In an exemplary embodiment, time lengths of light emitting stages of different display sub-frames may be the same or may be different. When the time lengths of the light emitting stages of different display sub-frames are different, a time length of a light emitting stage of a later display sub-frame is shorter than that of an earlier display sub-frame, which can realize more accurate control of the light emitting time length of the light emitting element.
In an exemplary embodiment, in the light emitting data writing stage, the signal of the first scan signal terminal Gate1 and the signal of the second scan signal terminal Gate2 are effective level signals, and the signal of the light emitting signal terminal EM is an ineffective level signal. In the light emitting stage, the signal of the first scan signal terminal Gate1 and the signal of the second scan signal terminal Gate2 are ineffective level signals, and the signal of the light emitting signal terminal EM is an effective level signal.
In an exemplary embodiment, when the signal of the first scan signal terminal Gate1 is an effective level signal, the signal of the third scan signal terminal Gate3 is an effective level signal, and when the signal of the light emitting signal terminal EM is an effective level signal, the signal of the third scan signal terminal Gate3 is an ineffective level signal.
In an exemplary embodiment, the signal of the third scan signal terminal Gate3 is an effective level signal in the light emitting data writing stage, and the signal of the third scan signal terminal Gate3 is an ineffective level signal in the light emitting stage.
As shown in
In the present disclosure, by providing the reset sub-circuit, the uniformity of light emitting of the light emitting element can be ensured and the display effect of the display product can be improved.
As shown in
In an exemplary embodiment, a voltage value of the signal of the control signal terminal S is constant, and the voltage value of the signal of the control signal terminal S may be 0V.
In the present disclosure, by providing the node control sub-circuit, the first node can be reset in a display stage, and the signal of the first node N1 in a non-display stage can also be obtained, so as to externally compensate the signal of the first data signal terminal Data1 in the display stage and improve the display effect of the display product.
In an exemplary embodiment, when a signal of the reset signal terminal Reset is an effective level signal, signals of the first scan signal terminal Gate1, the second scan signal terminal Gate2 and the light emitting signal terminal EM are ineffective level signals. When the signal of the first scan signal terminal Gate1 is an effective level signal, the signal of the reset signal terminal Reset is an ineffective level signal. When the signal of the light emitting signal terminal EM is an effective level signal, the signal of the reset signal terminal Reset is an ineffective level signal.
In an exemplary embodiment, a display sub-frame may further include a reset stage when the pixel circuit includes a reset sub-circuit. The reset stage occurs before the light emitting data writing stage. Herein, in the reset stage, the signal of the reset signal terminal Reset is an effective level signal, and the signals of the first scan signal terminal Gate1, the second scan signal terminal Gate2 and the light emitting signal terminal EM are ineffective level signals, in the light emitting data writing stage and the light emitting stage, the signal of the reset signal terminal Reset is an ineffective level signal.
In an exemplary embodiment, the drive control sub-circuit may also be electrically connected with a fourth power supply terminal. The third power supply terminal and the fourth power supply terminal may be the same power supply terminal or may be different power supply terminals, which is not limited in the present disclosure.
In an exemplary embodiment, transistor types of the second transistor T2 and the third transistor T3 are different.
In the present disclosure, the second transistor T2 and the third transistor T3 correspond to transmission gates, which can increase a writing range of the data signal of the first data signal terminal Data1 and improve the reliability of the pixel circuit.
Two exemplary configurations of the drive control sub-circuit are shown in
An exemplary structure of the light emitting control sub-circuit is shown in
An exemplary structure of the time-length control sub-circuit is shown in
An exemplary structure of the reset sub-circuit is shown in
An exemplary structure of the node control sub-circuit is shown in
As shown in
In an exemplary embodiment, transistor types of the first transistor T1, the second transistor T2, the fourth transistor T4 to the sixth transistor T6 may be the same or may be different, which are not limited in the present disclosure.
In an exemplary embodiment, the first transistor T1, the second transistor T2, the fourth transistor T4 to the sixth transistor T6 are all metal oxide semiconductor transistors. The metal oxide semiconductor transistors can reduce leakage current, improve performance of the pixel circuit, and reduce power consumption of the pixel circuit.
As shown in
In an exemplary embodiment, the second transistor T2 and the third transistor T3 are of opposite transistor types.
In an exemplary embodiment, transistor types of the first transistor T1, the second transistor T2, the fourth transistor T4 to the sixth transistor T6 may be the same or may be different, which are not limited in the present disclosure.
In an exemplary embodiment, the first transistor T1 to the sixth transistor T6 are all metal oxide semiconductor transistors. The metal oxide semiconductor transistors can reduce leakage current, improve the performance of the pixel circuit, and reduce the power consumption of the pixel circuit.
As shown in
As shown in
In an exemplary embodiment, the other plate of the first capacitor C1 is electrically connected with the first node N1 when the pixel circuit includes a node control sub-circuit, and the other plate of the first capacitor C1 may be electrically connected with the fourth power supply terminal Vcom2 or the first node N1 when the pixel circuit does not include a node control sub-circuit.
In an exemplary embodiment, transistor types of the first transistor T1, the second transistor T2, the fourth transistor T4 to the eighth transistor T8 may be the same or may be different, which are not limited in the present disclosure.
In an exemplary embodiment, the first transistor T1, the second transistor T2, the fourth transistor T4 to the eighth transistor T8 are all metal oxide semiconductor transistors. The metal oxide semiconductor transistors can reduce leakage current, improve the performance of the pixel circuit, and reduce the power consumption of the pixel circuit.
As shown in
As shown in
In an exemplary embodiment, the other plate of the first capacitor C1 is electrically connected with the first node N1 when the pixel circuit includes a node control sub-circuit, and the other plate of the first capacitor C1 may be electrically connected with the fourth power supply terminal Vcom2 or may be electrically connected with the first node N1 when the pixel circuit does not include a node control sub-circuit.
In an exemplary embodiment, the second transistor T2 and the third transistor T3 are of opposite transistor types.
In an exemplary embodiment, transistor types of the first transistor T1 to the eighth transistor T8 may be the same or may be different, which are not limited in the present disclosure.
In an exemplary embodiment, the first transistor T1 to the eighth transistor T8 are all metal oxide semiconductor transistors. The metal oxide semiconductor transistors can reduce leakage current, improve the performance of the pixel circuit, and reduce the power consumption of the pixel circuit.
In an exemplary embodiment, the first transistor T1 may be referred to as a drive transistor, and the first transistor T1 determines a drive current flowing between the second node N2 and the first node N1 according to a potential difference between the control electrode and the first electrode of the first transistor T1.
In an exemplary embodiment, the light emitting element in the present disclosure may be a silicon-based LED, i.e., the light emitting element is disposed on a silicon-based substrate.
In an exemplary embodiment, all of the transistors in the present disclosure may be disposed on a silicon-based substrate and may be metal oxide semiconductor transistors, and a breadth-length ratio of an active layer of the metal oxide semiconductor transistor is in the (sub) micron order, that is, its size is small. Therefore, the pixel circuit in the present disclosure may also be referred to as a silicon-based circuit.
Because the breadth-length ratio of the active layer of the metal oxide semiconductor transistor is in (sub) micron order, a high PPI, usually above 2000-3000PPI, can be achieved on the display substrate where the pixel circuit is located, and consequently a “screen window effect” is avoided. Since electrical performance of a metal oxide semiconductor transistor is relatively stable, electrical performance of a silicon-based circuit is more stable, there is no need for excessive internal threshold compensation while pursuing high PPI.
Exemplary embodiments of the present disclosure are described below through an operation process of the pixel circuit illustrated in
In a light emitting data writing stage P1, a signal of the first scan signal terminal Gate1 is a high-level signal, the second transistor T2 is turned on, the first data signal terminal Data1 outputs a data voltage, and a signal of the first data signal terminal Data1 is written to the fourth node N4 through the turned-on second transistor T2. A signal of the second scan signal terminal Gate2 is a high-level signal, the sixth transistor T6 is turned on, the second data signal terminal Data2 outputs a data voltage, a signal of the second data signal terminal Data2 is written to the fifth node N5 through the turned-on sixth transistor T6. When the signal of the second data signal terminal Data2 is a high-level signal, the fifth transistor T5 is turned on, when the signal of the second data signal terminal Data2 is a low-level signal, the fifth transistor T5 is turned off, a signal of the light emitting signal terminal EM is a high-level signal, the fourth transistor T4 is turned off, and the light emitting element L does not emit light.
In a light emitting stage P2, the signal of the light emitting signal terminal EM is a low-level signal, the fourth transistor T4 is turned on, a high-level signal of the first power supply terminal VDD is written to the second node N2 through the turned-on fourth transistor T4. The signal of the first scan signal terminal Gate1 is a low-level signal, the second transistor T2 is turned off, the fourth node N4 maintains a signal of the previous stage, and the first transistor T1 is turned on. The signal of the second scan signal terminal Gate2 is a low-level signal, the sixth transistor T6 is turned off, the fifth node N5 maintains a signal of the previous stage, and the fifth transistor T5 is kept in the turned-on or turned-off state of the previous stage. When the fifth transistor T5 is turned on, a current path between the first power supply terminal VDD and the third power supply terminal VSS is turned on, and the light emitting element L emits light, when the fifth transistor T5 is turned off, the current path between the first power supply terminal VDD and the third power supply terminal VSS is turned off, and the light emitting element L does not emit light.
Exemplary embodiments of the present disclosure are described below through an operation process of the pixel circuit illustrated in
In a light emitting data writing stage P1, the signal of the first scan signal terminal Gate1 is a high-level signal, the second transistor T2 is turned on, the signal of the third scan signal terminal Gate3 is a low-level signal, the third transistor T3 is turned on. The first data signal terminal Data1 outputs a data voltage, a signal of the first data signal terminal Data1 is written to the fourth node N4 through the turned-on second transistor T2 and the turned-on third transistor T3. A signal of the second scan signal terminal Gate2 is a high-level signal, the sixth transistor T6 is turned on, the second data signal terminal Data2 outputs a data voltage, a signal of the second data signal terminal Data2 is written to the fifth node N5 through the turned-on sixth transistor T6. When the signal of the second data signal terminal Data2 is a high-level signal, the fifth transistor T5 is turned on, when the signal of the second data signal terminal Data2 is a low-level signal, the fifth transistor T5 is turned off, the signal of the light emitting signal terminal EM is a high-level signal, the fourth transistor T4 is turned off, and the light emitting element L does not emit light.
In a light emitting stage P2, the signal of the light emitting signal terminal EM is a low-level signal, the fourth transistor T4 is turned on, a high-level signal of the first power supply terminal VDD is written to the second node N2 through the turned-on fourth transistor T4. The signal of the first scan signal terminal Gate1 is a low-level signal, the second transistor T2 is turned off, the signal of the third scan signal terminal Gate3 is a high-level signal, the third transistor T3 is turned off. The fourth node N4 maintains a signal of the previous stage, the first transistor T1 is turned on, the signal of the second scan signal terminal Gate2 is a low-level signal, and the sixth transistor T6 is turned off. The fifth node N5 maintains a signal of the previous stage, the fifth transistor T5 holds the turned-on or turned-off state of the previous stage. When the fifth transistor T5 is turned on, a current path between the first power supply terminal VDD and the third power supply terminal VSS is turned on, and the light emitting element L emits light. When the fifth transistor T5 is turned off, the current path between the first power supply terminal VDD and the third power supply terminal VSS is turned off, and the light emitting element L does not emit light.
Exemplary embodiments of the present disclosure are described below through an operation process of the pixel circuit illustrated in
In a reset stage P3, a signal of the reset signal terminal Reset is a high-level signal, the seventh transistor T7 is turned on, a signal of the initial signal terminal INIT is written to the third node N3 through the turned-on seventh transistor T7, so that a first electrode of the light emitting element is reset. A signal of the first scan signal terminal Gate1 is a low-level signal, the second transistor T2 is turned off, a signal of the second scan signal terminal Gate2 is a low-level signal, the sixth transistor T6 is turned off, a signal of the light emitting signal terminal EM is a high-level signal, the fourth transistor T4 is turned off, and the light emitting element L does not emit light.
In a light emitting data writing stage P1, the signal of the first scan signal terminal Gate1 is a high-level signal, the second transistor T2 is turned on, the first data signal terminal Data1 outputs a data voltage. A signal of the first data signal terminal Data1 is written to the fourth node N4 through the turned-on second transistor T2, the signal of the second scan signal terminal Gate2 is a high-level signal, the sixth transistor T6 is turned on. The second data signal terminal Data2 outputs a data voltage, a signal of the second data signal terminal Data2 is written to the fifth node N5 through the turned-on sixth transistor T6. When the signal of the second data signal terminal Data2 is a high-level signal, the fifth transistor T5 is turned on, when the signal of the second data signal terminal Data2 is a low-level signal, the fifth transistor T5 is turned off. The signal of the light emitting signal terminal EM is a high-level signal, the fourth transistor T4 is turned off, the signal of the reset signal terminal Reset is a low-level signal, the seventh transistor T7 is turned off, and the light emitting element L does not emit light.
In a light emitting stage P2, the signal of the light emitting signal terminal EM is a low-level signal, the fourth transistor T4 is turned on, and a high-level signal of the first power supply terminal VDD is written to the second node N2 through the turned-on fourth transistor T4. The signal of the reset signal terminal Reset is a low-level signal, the seventh transistor T7 is turned off, the signal of the first scan signal terminal Gate1 is a low-level signal, and the second transistor T2 is turned off. The fourth node N4 maintains a signal of the previous stage, the first transistor T1 is turned on, the signal of the second scan signal terminal Gate2 is a low-level signal, the sixth transistor T6 is turned off, the fifth node N5 maintains a signal of the previous stage, and the fifth transistor T5 holds the turned-on or turned-off state of the previous stage. When the fifth transistor T5 is turned on, the current path between the first power supply terminal VDD and the third power supply terminal VSS is turned on, and the light emitting element L emits light, when the fifth transistor T5 is turned off, the current path between the first power supply terminal VDD and the third power supply terminal VSS is turned off, and the light emitting element L does not emit light.
Exemplary embodiments of the present disclosure are described below through an operation process of the pixel circuit illustrated in
In a reset stage P3, a signal of the reset signal terminal Reset is a high-level signal, the seventh transistor T7 is turned on, a signal of the initial signal terminal INIT is written to the third stage N3 through the turned-on seventh transistor T7, so that a first electrode of the light emitting element is reset. A signal of the first scan signal terminal Gate1 is a low-level signal, the second transistor T2 is turned off, a signal of the third scan signal terminal Gate3 is a high-level signal, the third transistor T3 is turned off. A signal of the second scan signal terminal Gate2 is a low-level signal, the sixth transistor T6 is turned off, a signal of the light emitting signal terminal EM is a high-level signal, the fourth transistor T4 is turned off, and the light emitting element L does not emit light.
In a light emitting data writing stage P1, the signal of the first scan signal terminal Gate1 is a high-level signal, the second transistor T2 is turned on, the signal of the third scan signal terminal Gate3 is a low-level signal, the third transistor T3 is turned on. The first data signal terminal Data1 outputs a data voltage, a signal of the first data signal terminal Data1 is written to the fourth node N4 through the turned-on second transistor T2 and the turned-on third transistor T3. The signal of the second scan signal terminal Gate2 is a high-level signal, the sixth transistor T6 is turned on, the second data signal terminal Data2 outputs a data voltage, a signal of the second data signal terminal Data2 is written to the fifth node N5 through the turned-on sixth transistor T6. When the signal of the second data signal terminal Data2 is a high-level signal, the fifth transistor T5 is turned on. When the signal of the second data signal terminal Data2 is a low-level signal, the fifth transistor T5 is turned off, the signal of the light emitting signal terminal EM is a high-level signal, the fourth transistor T4 is turned off, the signal of the reset signal terminal Reset is a low-level signal, the seventh transistor T7 is turned off, and the light emitting element L does not emit light.
In a light emitting stage P2, the signal of the light emitting signal terminal EM is a low-level signal, the fourth transistor T4 is turned on, the high-level signal of the first power supply terminal VDD is written to the second node N2 through the turned-on fourth transistor T4. The signal of the reset signal terminal Reset is a low-level signal, the seventh transistor T7 is turned off, the signal of the first scan signal terminal Gate1 is a low-level signal, the second transistor T2 is turned off. The signal of the third scan signal terminal Gate3 is a high-level signal, the third transistor T3 is turned off, the fourth node N4 maintains a signal of the previous stage, the first transistor T1 is turned on, the signal of the second scan signal terminal Gate2 is a low-level signal, the sixth transistor T6 is turned off, the fifth node N5 maintains a signal of the previous stage, and the fifth transistor T5 holds the turned-on or turned-off state of the previous stage. When the fifth transistor T5 is turned on, a current path between the first power supply terminal VDD and the third power supply terminal VSS is turned on, and the light emitting element L emits light, when the fifth transistor T5 is turned off, the current path between the first power supply terminal VDD and the third power supply terminal VSS is turned off, and the light emitting element L does not emit light.
Exemplary embodiments of the present disclosure are described below through an operation process of the pixel circuit illustrated in
In a light emitting data writing stage P1, a signal of the first scan signal terminal Gate1 is a high-level signal, the second transistor T2 and the eighth transistor T8 are turned on, and the first data signal terminal Data1 outputs a data voltage. A signal of the first data signal terminal Data1 is written to the fourth node N4 through the turned-on second transistor T2, a signal of the control signal terminal S is written to the first node N1 through the turned-on eighth transistor T8, a signal of the second scan signal terminal Gate2 is a high-level signal, the sixth transistor T6 is turned on, the second data signal terminal Data2 outputs a data voltage, and a signal of the second data signal terminal Data2 is written to the fifth node N5 through the turned-on sixth transistor T6. When the signal of the second data signal terminal Data2 is a high-level signal, the fifth transistor T5 is turned on, when the signal of the second data signal terminal Data2 is a low-level signal, the fifth transistor T5 is turned off, a signal of the light emitting signal terminal EM is a high-level signal, the fourth transistor T4 is turned off, and the light emitting element L does not emit light.
In a light emitting stage P2, the signal of the light emitting signal terminal EM is a low-level signal, the fourth transistor T4 is turned on, the high-level signal of the first power supply terminal VDD is written to the second node N2 through the turned-on fourth transistor T4. The signal of the first scan signal terminal Gate1 is a low-level signal, the second transistor T2 and the eighth transistor T8 are turned off, the fourth node N4 maintains a signal of the previous stage, and the first transistor T1 is turned on. The signal of the second scan signal terminal Gate2 is a low-level signal, the sixth transistor T6 is turned off, the fifth node N5 maintains a signal of the previous stage, and the fifth transistor T5 holds the turned-on or turned-off state of the previous stage. When the fifth transistor T5 is turned on, a current path between the first power supply terminal VDD and the third power supply terminal VSS is turned on, and the light emitting element L emits light, when the fifth transistor T5 is turned off, the current path between the first power supply terminal VDD and the third power supply terminal VSS is turned off, and the light emitting element L does not emit light.
Exemplary embodiments of the present disclosure are described below through an operation process of the pixel circuit illustrated in
In a light emitting data writing stage P1, a signal of the first scan signal terminal Gate1 is a high-level signal, the second transistor T2 and the eighth transistor T8 are turned on, a signal of the third scan signal terminal Gate3 is a low-level signal, the third transistor T3 is turned on. The first data signal terminal Data1 outputs a data voltage, a signal of the first data signal terminal Data1 is written to the fourth node N4 through the turned-on second transistor T2 and the turned-on third transistor T3, a signal of the control signal terminal S is written to the first node N1 through the turned-on eighth transistor T8. A signal of the second scan signal terminal Gate2 is a high-level signal, the sixth transistor T6 is turned on, the second data signal terminal Data2 outputs a data voltage, and a signal of the second data signal terminal Data2 is written to the fifth node N5 through the turned-on sixth transistor T6. When the signal of the second data signal terminal Data2 is a high-level signal, the fifth transistor T5 is turned on, when the signal of the second data signal terminal Data2 is a low-level signal, the fifth transistor T5 is turned off, a signal of the light emitting signal terminal EM is a high-level signal, the fourth transistor T4 is turned off, and the light emitting element L does not emit light.
In a light emitting stage P2, the signal of the light emitting signal terminal EM is a low-level signal, the fourth transistor T4 is turned on, a high-level signal of the first power supply terminal VDD is written to the second node N2 through the turned-on fourth transistor T4. The signal of the first scan signal terminal Gate1 is a low-level signal, the second transistor T2 and the eighth transistor T8 are turned off. The signal of the third scan signal terminal Gate3 is a high-level signal, the third transistor T3 is turned off, the fourth node N4 maintains a signal of the previous stage, and the first transistor T1 is turned on. The signal of the second scan signal terminal Gate2 is a low-level signal, the sixth transistor T6 is turned off, the fifth node N5 maintains a signal of the previous stage, and the fifth transistor T5 holds the turned-on or turned-off state of the previous stage. When the fifth transistor T5 is turned on, a current path between the first power supply terminal VDD and the third power supply terminal VSS is turned on, and the light emitting element L emits light. When the fifth transistor T5 is turned off, the current path between the first power supply terminal VDD and the third power supply terminal VSS is turned off, and the light emitting element L does not emit light.
Exemplary embodiments of the present disclosure are described below through an operation process of the pixel circuit illustrated in
In a reset stage P3, a signal of the reset signal terminal Reset is a high-level signal, the seventh transistor T7 is turned on, a signal of the initial signal terminal INIT is written to the third node N3 through the turned-on seventh transistor T7, so that a first electrode of the light emitting element is reset. A signal of the first scan signal terminal Gate1 is a low-level signal, the second transistor T2 and the eighth transistor T8 are turned off, a signal of the second scan signal terminal Gate2 is a low-level signal, the sixth transistor T6 is turned off, a signal of the light emitting signal terminal EM is a high-level signal, the fourth transistor T4 is turned off, and the light emitting element L does not emit light.
In a light emitting data writing stage P1, the signal of the first scan signal terminal Gate1 is a high-level signal, the second transistor T2 and the eighth transistor T8 are turned on, and the first data signal terminal Data1 outputs a data voltage. A signal of the first data signal terminal Data1 is written to the fourth node N4 through the turned-on second transistor T2, a signal of the control signal terminal S is written to the first node N1 through the turned-on eighth transistor T8. The signal of the second scan signal terminal Gate2 is a high-level signal, the sixth transistor T6 is turned on, the second data signal terminal Data2 outputs a data voltage, and the signal of the second data signal terminal Data2 is written to the fifth node N5 through the turned-on sixth transistor T6. When the signal of the second data signal terminal Data2 is a high-level signal, the fifth transistor T5 is turned on, when the signal of the second data signal terminal Data2 is a low-level signal, the fifth transistor T5 is turned off, the signal of the light emitting signal terminal EM is a high-level signal, the fourth transistor T4 is turned off, the signal of the reset signal terminal Reset is a low-level signal, the seventh transistor T7 is turned off, and the light emitting element L does not emit light.
In a light emitting stage P2, the signal of the light emitting signal terminal EM is a low-level signal, the fourth transistor T4 is turned on, the high-level signal of the first power supply terminal VDD is written to the second node N2 through the turned-on fourth transistor T4. The signal of the reset signal terminal Reset is a low-level signal, the seventh transistor T7 is turned off, the signal of the first scan signal terminal Gate1 is a low-level signal, the second transistor T2 and the eighth transistor T8 are turned off. The fourth node N4 maintains a signal of the previous stage, the first transistor T1 is turned on, the signal of the second scan signal terminal Gate2 is a low-level signal, the sixth transistor T6 is turned off, the fifth node N5 maintains a signal of the previous stage, and the fifth transistor T5 holds the turned-on or turned-off state of the previous stage. When the fifth transistor T5 is turned on, a current path between the first power supply terminal VDD and the third power supply terminal VSS is turned on, and the light emitting element L emits light, when the fifth transistor T5 is turned off, the current path between the first power supply terminal VDD and the third power supply terminal VSS is turned off, and the light emitting element L does not emit light.
Exemplary embodiments of the present disclosure are described below through an operation process of the pixel circuit illustrated in
In a reset stage P3, a signal of the reset signal terminal Reset is a high-level signal, the seventh transistor T7 is turned on, a signal of the initial signal terminal INIT is written to the third stage N3 through the turned-on seventh transistor T7, so that a first electrode of the light emitting element is reset. A signal of the first scan signal terminal Gate1 is a low-level signal, the second transistor T2 and the eighth transistor T8 are turned off, a signal of the third scan signal terminal Gate3 is a high-level signal, and the third transistor T3 is turned off. A signal of the second scan signal terminal Gate2 is a low-level signal, the sixth transistor T6 is turned off, a signal of the light emitting signal terminal EM is a high-level signal, the fourth transistor T4 is turned off, and the light emitting element L does not emit light.
In a light emitting data writing stage P1, the signal of the first scan signal terminal Gate1 is a high-level signal, the second transistor T2 and the eighth transistor T8 are turned on, the signal of the third scan signal terminal Gate3 is a low-level signal, the third transistor T3 is turned on. The first data signal terminal Data1 outputs a data voltage, a signal of the first data signal terminal Data1 is written to the fourth node N4 through the turned-on second transistor T2 and the turned-on third transistor T3, and a signal of the control signal terminal S is written to the first node N1 through the turned-on eighth transistor T8. The signal of the second scan signal terminal Gate2 is a high-level signal, the sixth transistor T6 is turned on, the second data signal terminal Data2 outputs a data voltage, and the signal of the second data signal terminal Data2 is written to the fifth node N5 through the turned-on sixth transistor T6. When the signal of the second data signal terminal Data2 is a high-level signal, the fifth transistor T5 is turned on, when the signal of the second data signal terminal Data2 is a low-level signal, the fifth transistor T5 is turned off, the signal of the light emitting signal terminal EM is a high-level signal, the fourth transistor T4 is turned off, the signal of the reset signal terminal Reset is a low-level signal, the seventh transistor T7 is turned off, and the light emitting element L does not emit light.
In a light emitting stage P2, the signal of the light emitting signal terminal EM is a low-level signal, the fourth transistor T4 is turned on, a high-level signal of the first power supply terminal VDD is written to the second node N2 through the turned-on fourth transistor T4. The signal of the reset signal terminal Reset is a low-level signal, the seventh transistor T7 is turned off, the signal of the first scan signal terminal Gate1 is a low-level signal, the second transistor T2 and the eighth transistor T8 are turned off, the signal of the third scan signal terminal Gate3 is a high-level signal, the third transistor T3 is turned off. The fourth node N4 maintains a signal of a previous stage, the first transistor T1 is turned on, the signal of the second scan signal terminal Gate2 is a low-level signal, the sixth transistor T6 is turned off, the fifth node N5 maintains a signal of a previous stage, the fifth transistor T5 holds the turned-on or turned-off state of the previous stage. When the fifth transistor T5 is turned on, a current path between the first power supply terminal VDD and the third power supply terminal VSS is turned on, and the light emitting element L emits light, when the fifth transistor T5 is turned off, the current path between the first power supply terminal VDD and the third power supply terminal VSS is turned off, and the light emitting element L does not emit light.
In the present disclosure, according to the signal of the second data signal terminal Data2, the fifth transistor T5 is controlled to be turned on or turned off in at least one display sub-frame within a display frame, and under a same drive current in the current path between the first power supply terminal VDD and the third power supply terminal VSS, the light emitting element emits light for different time length, so as to achieve an effect of different brightness and gray scale.
In an exemplary embodiment,
The drive control sub-circuit and the light emitting control sub-circuit in the present disclosure are configured to control a voltage amplitude of a control electrode of the first transistor, so that the light emitting brightness amplitude of the light emitting element L can be controlled. The time-length control sub-circuit controls a time length of the current path of the pixel circuit and controls a total brightness of the light emitting element L in a display frame.
Exemplary embodiments of the present disclosure are described below through an operation process of the pixel circuit illustrated in
In conjunction with
In a compensation data writing stage SP1, a signal of the light emitting signal terminal EM is a high-level signal, the fourth transistor T4 is turned off, a signal of the first scan signal terminal Gate1 is a high-level signal, the first data signal terminal Data1 outputs a data voltage, the second transistor T2 and the eighth transistor T8 are turned on. A signal of the first data signal terminal Data1 is written to the fourth node N4 through the turned-on second transistor T2, the first transistor T1 is turned on, and a signal of the control signal terminal S is written to the first node N1 through the turned-on eighth transistor T8. A signal of the second scan signal terminal Gate2 is a high-level signal, the second data signal terminal Data2 outputs a low-level data voltage, the sixth transistor T6 is turned on, a signal of the second data signal terminal Data2 is written to the fifth node N5 through the turned-on sixth transistor T6, and the fifth transistor T5 is turned off.
In a compensation stage SP2, the signal of the second scan signal terminal Gate2 is a low-level signal, the sixth transistor T6 is turned off, the fifth node N5 maintains a signal of the previous stage, and the fifth transistor T5 is turned off. The signal of the light emitting signal terminal EM is a low-level signal, the fourth transistor T4 is turned on, a signal of the first power supply terminal VDD is written to the second node N2 through the turned-on fourth transistor T4. The signal of the first scan signal terminal Gate1 is a high-level signal, the first data signal terminal Data1 outputs a data voltage, the second transistor T2 and the eighth transistor T8 are continuously turned on. The signal of the first data signal terminal Data1 is written to the fourth node N4 through the turned-on second transistor T2. The first transistor T1 is turned on, the signal of the first power supply terminal VDD is charged to the first node N1 through the turned-on fourth transistor T4, the second node N2 and the turned-on first transistor T1, until the voltage value of a signal of the first node N1 is Vdata1-Vth1, wherein Vdata1 is a voltage value of the signal of the first data signal terminal Data1, and Vth1 is a threshold voltage of the first transistor. At this time, a voltage difference between two ends of the first capacitor C1 is Vth1, the first transistor T1 is turned off, and the signal of the first node N1 can be read to the control signal terminal S through the turned-on eighth transistor T8.
Exemplary embodiments of the present disclosure are described below through an operation process of the pixel circuit illustrated in
With reference to
In a compensation data writing stage SP1, a signal of the light emitting signal terminal EM is a high-level signal, the fourth transistor T4 is turned off, a signal of the first scan signal terminal Gate1 is a high-level signal, the first data signal terminal Data1 outputs a data voltage, the second transistor T2 and the eighth transistor T8 are turned on. A signal of the third scan signal terminal Gate3 is a low-level signal, the third transistor T3 is turned on, a signal of the first data signal terminal Data1 is written to the fourth node N4 through the turned-on second transistor T2 and the turned-on third transistor T3. The first transistor T1 is turned on, and a signal of the control signal terminal S is written to the first node N1 through the turned-on eighth transistor T8. A signal of the second scan signal terminal Gate2 is a high-level signal, the second data signal terminal Data2 outputs a low-level data voltage, the sixth transistor T6 is turned on, a signal of the second data signal terminal Data2 is written to the fifth node N5 through the turned-on sixth transistor T6, and the fifth transistor T5 is turned off.
In a compensation stage SP2, the signal of the second scan signal terminal Gate2 is a low-level signal, the sixth transistor T6 is turned off, the fifth node N5 maintains a signal of the previous stage, and the fifth transistor T5 is turned off. The signal of the light emitting signal terminal EM is a low-level signal, the fourth transistor T4 is turned on, a signal of the first power supply terminal VDD is written to the second node N2 through the turned-on fourth transistor T4. The signal of the first scan signal terminal Gate1 is a high-level signal, the first data signal terminal Data1 outputs a data voltage, the second transistor T2 and the eighth transistor T8 are continuously turned on. The signal of the third scan signal terminal Gate3 is a low-level signal, the third transistor T3 is turned on, the signal of the first data signal terminal Data1 is written to the fourth node N4 via the second transistor T2 and the third transistor T3 which are turned on. The first transistor T1 is turned on, the signal of the first power supply terminal VDD is charged to the first node N1 through the turned-on fourth transistor T4, the turned-on second node N2 and the turned-on first transistor T1, until a voltage value of a signal of the first node N1 is Vdata1-Vth1, wherein Vdata1 is a voltage value of the signal of the first data signal terminal Data1, and Vth1 is a threshold voltage of the first transistor. At this time, a voltage difference between two ends of the first capacitor C1 is Vth1, the first transistor T1 is turned off, and the signal of the first node N1 can be read to the control signal terminal S through the turned-on eighth transistor T8.
According to the present disclosure, the threshold voltage Vth1 of the first transistor can be obtained according to the signal of the control signal terminal S by reading the signal of the first node N1 to the control signal terminal S, and the data signal of the first data signal terminal Data1 in a display stage is externally compensated according to the threshold voltage Vth1 of the first transistor.
An embodiment of the present disclosure further provides a method for driving the pixel circuit, which is configured to drive the pixel circuit. The pixel circuit is located in a display substrate, and the display substrate has a display stage, the display stage includes multiple display frames. The display frame includes at least one display sub-frame, and each display sub-frame includes a light emitting data writing stage and a light emitting stage. The method for driving the pixel circuit according to the embodiment of the present disclosure may include the following steps.
In step 100, in the light emitting data writing stage, the drive control sub-circuit provides a drive current to the first node under control of the first scan signal terminal, the first data signal terminal and the second node, and the time-length control sub-circuit provides a signal of the first node to the third node under control of the second scan signal terminal and the second data signal terminal.
In step 200, in the light emitting stage, the light emitting control sub-circuit provides a signal of the first power supply terminal to the second node under control of the light emitting signal terminal.
The pixel circuit is the pixel circuit according to any one of the foregoing embodiments, and the implementation principles and implementation effects are similar, which will not be repeated here.
In an exemplary embodiment, the pixel circuit may further include a reset sub-circuit, the display sub-frame may further include a reset stage, and the method for driving the pixel circuit according to an exemplary embodiment may further include the following steps.
In the reset stage, the reset sub-circuit provides a signal of the initial signal terminal to the third node under control of the reset signal terminal.
In an exemplary embodiment, the pixel circuit may further include a node control sub-circuit, the display substrate may further include a non-display stage. The non-display stage includes a compensation data writing stage and a compensation stage, and the method for driving the pixel circuit according to an exemplary embodiment may further include the following steps.
In the light emitting data writing stage and the compensation data writing stage, the node control sub-circuit provides a signal of the control signal terminal to the first node under control of the first scan signal terminal.
In the compensation stage, the node control sub-circuit reads a signal of the first node to the control signal terminal under control of the first scan signal terminal.
An embodiment of the present disclosure further provides a display substrate, which includes a display area and a non-display area surrounding at least one side of the display area, wherein the display area is provided with multiple pixels, and a pixel circuit is disposed in the pixel.
The pixel circuit is a pixel circuit according to any one of the foregoing embodiments, and the implementations principle and implementation effects are similar, which will not be repeated here.
The display substrate according to the embodiment of the present disclosure may be applied to display products with any resolution.
In an exemplary embodiment, when the pixel circuit includes a node control sub-circuit, the display substrate further includes a first chip connected with the control signal terminal and a second chip connected with the first data signal terminal. Here, the first chip is configured to provide a signal to the control signal terminal in the display stage, read the signal of the control signal terminal in the non-display stage, and is further configured to obtain a threshold voltage of the first transistor according to the signal of the control signal terminal, generate a control signal according to the threshold voltage of the first transistor, and send the control signal to the second chip, and the second chip provides a signal to the first data signal terminal according to the control signal.
According to the present disclosure, the first data signal terminal can be externally compensated according to the first chip, so that the service life of the display substrate can be prolonged and the display effect of the display substrate can be improved.
An embodiment of the present disclosure further provides a display device including a display substrate.
The display substrate is a display substrate according to any of the aforementioned embodiments, and has similar implementation principles and implementation effects, which will not be repeated here.
In an exemplary embodiment, the display device may be any product or component with a display function, such as a liquid crystal panel, electronic paper, an OLED panel, an Active-Matrix Organic Light Emitting Diode (AMOLED for short) panel, a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital photo frame, or a navigator.
The accompanying drawings of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures may refer to usual designs.
For the sake of clarity, in the accompanying drawings used for describing the embodiments of the present disclosure, a thickness and dimension of a layer or a micro structure is enlarged. It may be understood that when an element such as a layer, a film, a region, or a substrate is described as being “on” or “under” another element, the element may be “directly” located “on” or “under” the other element, or there may be an intermediate element.
Although the embodiments disclosed in the present disclosure are as above, the described contents are only embodiments used for convenience of understanding the present disclosure and are not intended to limit the present disclosure. Any person skilled in the art to which the present disclosure pertains may make any modification and variation to implementation modes and details without departing from the spirit and scope disclosed in the present disclosure. However, the scope of patent protection of the present disclosure is still subject to the scope defined by the appended claims.
The present application is a U.S. National Phase Entry of International Application PCT/CN2022/100175 having an international filing date of Jun. 21, 2022, and entitled “Pixel Circuit, Drive Method Therefor, Display Substrate, and Display Device”. The entire contents of the above-identified applications are hereby incorporated by reference.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2022/100175 | 6/21/2022 | WO |
