Claims
- 1. A programmable logic array (PLA) comprising:
- a plurality of true/complement generators each receiving PLA input signals, wherein at least one of the true/complement generators receives a late-entering input signal;
- an AND array coupled to the true/complement generators;
- a plurality of gap cells coupled to the AND array for transmitting AND array output signals; and
- said at least one of the true/complement generators that receives the late entering input signal bypassing the AND array and coupled directly to at least one of the gap cells.
- 2. The PLA of claim 1 wherein said at least one of the gap cells comprises a gate coupled to the AND array for receiving one of the AND array output signals and to said at least one of the true/complement generators that receives the late-entering input signal for combining said one of the AND array output signals with the late-entering signal from said at least one of the true/complement generators.
- 3. The PLA of claim 2 wherein said gate is coupled to the AND array through an inverter.
- 4. A programmable logic array (PLA) comprising:
- true/complement generators each receiving PLA input signals, wherein at least one of the true/complement generators receives a known late-entering input signal;
- an AND array coupled to a plurality of the true/complement generators;
- an OR array coupled to the AND array through a plurality of gap cells;
- output circuits for outputting OR array outputs; and
- said at least one of the true/complement generators that receives the known late-entering signal, bypassing the AND array and the OR array, coupled directly to at least one of the output circuits.
Parent Case Info
This is a divisional of application Ser. No. 08/603,662 filed on Feb. 20, 1996, now U.S. Pat. No. 5,717,344.
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Divisions (1)
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Number |
Date |
Country |
Parent |
603662 |
Feb 1996 |
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