Patent Application
20120223923
The present invention relates to a plasma display apparatus of the AC surface discharge type and to a driving method for a plasma display panel.
A plasma display panel (hereinafter, simply referred to as “panel”) has a front substrate and a rear substrate opposed to each other. The front substrate has a plurality of display electrode pairs, each including a scan electrode and a sustain electrode, long in the row direction. The rear substrate has a plurality of data electrodes long in the column direction. A discharge cell is formed in a position where a display electrode pair three-dimensionally intersects (hereinafter, simply referred to as “intersects”) a data electrode. A plasma display apparatus is an apparatus that has a scan electrode driver circuit, a sustain electrode driver circuit, and a data electrode driver circuit, each for driving the above panel, and displays an image by applying necessary driving voltage waveforms to the respective electrodes.
A typical driving method for the panel is a subfield method of displaying gradations by dividing one field period into a plurality of subfields and combining the subfields where light is emitted. Each of the subfields has an initializing period, an address period, and a sustain period.
In the initializing period, an initializing operation is performed so as to cause an initializing discharge and to form wall charge necessary for the subsequent address operation. In the address period, an address operation is performed so as to apply an address pulse to the data electrodes corresponding to an image to be displayed and to selectively cause an address discharge in the respective discharge cells. Wall charge is formed in the discharge cells having undergone the address discharge. In the sustain period, a sustain operation is performed so as to generate sustain pulses corresponding in number to the luminance weight and to apply the sustain pulses alternately to the scan electrodes and the sustain electrodes. The sustain operation generates a sustain discharge and causes the phosphor layers to emit light in the discharge cells having undergone the address discharge. Thus, an image is displayed on the panel.
The plasma display apparatus includes electrode driver circuits specific to electrode types that generate driving voltage waveforms to be applied to the respective electrodes of the panel. The data electrode driver circuit is a driver circuit for applying an address pulse corresponding to an image signal to the respective data electrodes and for causing an address discharge in the respective discharge cells. The transition time of the rising edge and the transition time of the falling edge of the address pulse generated by the data electrode driver circuit are shorter than those of a sustain pulse, for example. Thus, a large current instantaneously flows in the generation of the address pulse. This large current is likely to cause unnecessary radiation (the generic term of unnecessary electromagnetic wave noise emitted from an electronic device), e.g. line radiation (electromagnetic noise emitted through the power supply line) and housing radiation (electromagnetic noise emitted from the main unit of the electronic device), of electromagnetic waves.
Such electromagnetic waves, if intensely generated, have adverse effects, such as interference with other electronic devices. In order to prevent such adverse effects, the upper limit of the electromagnetic radiation is legally regulated. Further, in order to suppress the electromagnetic radiation below the regulated values, various proposals are made. For example, Patent Literature 1 discloses a plasma display apparatus structured such that a metallic back cover that has a cutout portion over the shield case is attached to the chassis member, and the metallic back cover is electrically connected to a metallic case via a conductive gasket.
However, with recent increases in the definition and size of the panel, the electric power consumption of the plasma display apparatus tends to increase. This also tends to increase unnecessary radiation, e.g. line radiation and housing radiation, of electromagnetic waves. Thus, it is difficult to sufficiently obtain the advantage of reducing the unnecessary radiation only with the above method.
PTL1
Japanese Patent Unexamined Publication No. 2000-196977
A plasma display apparatus includes the following elements:
This configuration can distribute the generation timings of the address pulses in response to the load capacitance of the data electrode, and thus distribute the timings at which a discharge current flows in the data electrodes. Therefore, this configuration can suppress unnecessary radiation, e.g. line radiation and housing radiation, and generate a stable address discharge.
In a driving method for a panel,
the driving method includes:
This method can distribute the generation timings of the address pulses in response to the load capacitance of the data electrode, and thus distribute the timings at which a discharge current flows in the data electrodes. Therefore, this method can suppress unnecessary radiation, e.g. line radiation and housing radiation, and generate a stable address discharge.
Hereinafter, a plasma display apparatus in accordance with exemplary embodiments of the present invention is described, with reference to the accompanying drawings.
Front substrate 11 and rear substrate 21 face each other such that display electrode pairs 14 intersect data electrodes 22 with a small discharge space sandwiched between the electrodes. The outer peripheries of the substrates are sealed with a sealing material, such as a glass frit. Into the discharge space, a mixture gas of neon and xenon, for example, is sealed as a discharge gas. The discharge space is partitioned into a plurality of compartments by barrier ribs 24. Discharge cells are formed in the intersecting parts of display electrode pairs 14 and data electrodes 22. These discharge cells discharge and emit light so as to display an image on panel 10.
The structure of panel 10 is not limited to the above, and may include barrier ribs in a stripe pattern, for example.
Between the electrodes thus arranged, interelectrode capacitance (capacitance generated between the electrodes, hereinafter being also simply referred to as “capacitance”) is present.
As shown in
In panel 10, one data electrode Dj intersects n scan electrode SC1-scan electrode SCn and n sustain electrode SU1-sustain electrode SUn. Therefore, in panel 10, capacitance (n×Cs) is present between data electrode Dj and all display electrode pairs 14 (n display electrode pairs). Hereinafter, this capacitance (n×Cs) is denoted as capacitance Cg.
Thus, in one data electrode 22, capacitance Cg occurs between the data electrode and all display electrode pairs 14, capacitance Cc occurs between that data electrode and data electrode 22 adjacent on the right side, and capacitance Cc occurs between that data electrode and data electrode 22 adjacent on the left side. That is, the total load capacitance generated in one data electrode 22 amounts to capacitance Cg+2Cc, which occurs in each data electrode 22.
Next, a driving method for panel 10 is described. In this exemplary embodiment, a so-called subfield method is used as the method for displaying gradations. The subfield method is a method for displaying gradations by dividing one field period into a plurality of subfields and controlling the light emission and no light emission in each discharge cell in each subfield. Each subfield has an initializing period, an address period, and a sustain period. In this exemplary embodiment, one field is formed of eight subfields (SF1, SF2 . . . SF8), and the respective subfields have luminance weights of 1, 2, 4, 8, 16, 32, 64, and 128. However, this subfield structure is only an example, and the present invention is not limited to this subfield structure.
In the initializing period of subfield SF1, voltage 0 (V) is applied to data electrode D1-data electrode Dm and sustain electrode SU1-sustain electrode SUn, and a ramp voltage gently rising from voltage Vi1 toward voltage Vi2 is applied to scan electrode SC1-scan electrode SCn. Voltage Vi1 is a voltage equal to or lower than a discharge start voltage with respect to sustain electrode SU1-sustain electrode SUn. Voltage Vi2 is a voltage exceeding the discharge start voltage with respect to sustain electrode SU1-sustain electrode SUn. This voltage application causes a weak initializing discharge between scan electrode SC1-scan electrode SCn and sustain electrode SU1-sustain electrode SUn, and between scan electrode SC1-scan electrode SCn and data electrode D1-data electrode Dm.
Thereafter, voltage Ve1 is applied to sustain electrode SU1-sustain electrode SUn, and a ramp voltage gently falling from voltage Vi3 toward voltage Vi4 is applied to scan electrode SC1-scan electrode SCn. Voltage Vi3 is a voltage equal to or lower than a discharge start voltage with respect to sustain electrode SU1-sustain electrode SUn. Voltage Vi4 is a voltage exceeding the discharge start voltage with respect to sustain electrode SU1-sustain electrode SUn. This voltage application causes a weak initializing discharge between scan electrode SC1-scan electrode SCn and sustain electrode SU1-sustain electrode SUn, and between scan electrode SC1-scan electrode SCn and data electrode D1-data electrode Dm.
In the initializing period, in this manner, a weak initializing discharge occurs in the discharge cells so as to form wall charge necessary for the subsequent address operation on the respective electrodes. As the operation in the initializing period, only the gently falling ramp voltage may be applied to scan electrode SC1-scan electrode SCn, as shown in the initializing period of subfield SF2 of
In the subsequent address period, voltage Ve2 is applied to sustain electrode SU1-sustain electrode SUn, voltage Vc is applied to scan electrode SC1-scan electrode SCn, and voltage 0 (V) is applied to data electrode D1-data electrode Dm. Next, a scan pulse at voltage Va is applied to scan electrode SC1 in the first line, and an address pulse at voltage Vd is applied to data electrode Dk (k=1-m) corresponding to the discharge cell to be lit. In the discharge cell in the first line applied with the scan pulse and the address pulse at the same time, an address discharge occurs, and an address operation for accumulating wall charge on scan electrode SC1 and sustain electrode SU1 is performed. In contrast, in the discharge cells applied with no address pulse, no address discharge occurs and the wall voltage after the completion of the initializing period is maintained.
In the address period, the similar address operation is sequentially performed on each line, starting from the discharge cells in the second line and reaching the discharge cells in the n-th line. Thus, an address discharge is caused selectively in the discharge cells to be lit so as to form wall charge in the discharge cells.
Data electrodes 22 as viewed from the data electrode driver circuit are capacitive loads as shown in
In the subsequent sustain period, voltage 0 (V) is applied to sustain electrode SU1-sustain electrode SUn, and a sustain pulse at voltage Vs is applied to scan electrode SC1-scan electrode SCn. With this application, in the discharge cells having undergone an address discharge, a sustain discharge occurs and the ultraviolet rays generated at this time cause phosphor layers 25 to emit light. Next, voltage 0 (V) is applied to scan electrode SC1-scan electrode SCn, and a sustain pulse at voltage Vs is applied to sustain electrode SU1-sustain electrode SUn. With this application, in the discharge cells having undergone the sustain discharge immediately before, a sustain discharge occurs again and light is emitted. Thereafter, sustain pulses corresponding in number to the luminance weight are generated and applied alternately to scan electrode SC1-scan electrode SCn and sustain electrode SU1-sustain electrode SUn. Thereby, the discharge cells having undergone the address discharge are lit at a luminance corresponding to the luminance weight.
After all the sustain pulses have been generated, a ramp voltage gently rising from voltage 0 (V) toward voltage Vr is applied to scan electrode SC1-scan electrode SCn. This voltage application causes a weak discharge in the discharge cells having undergone a sustain discharge, thereby causing so-called wall charge erasure for erasing a part or the whole of the wall charge. Thus, the sustain period is completed. In this exemplary embodiment, voltage Vr is set to a voltage equal to voltage Vs, but may be set to a voltage different from voltage Vs.
In the subsequent subfields, the operation similar to the operation in the above subfield except for the numbers of sustain pulses is repeated. Thus, the discharge cells are lit at luminances corresponding to the luminance weights in the respective subfields.
Next, a description is provided for a driver circuit for driving panel 10.
panel 10 having a plurality of discharge cells arranged therein, each discharge cell having scan electrode 12, sustain electrode 13, and data electrode 22; and
a driver circuit for driving panel 10.
The driver circuit includes image signal processing circuit 31, data electrode driver circuit 32, scan electrode driver circuit 33, sustain electrode driver circuit 34, timing generation circuit 35, and an electric power supply circuit (not shown) for supplying electric power necessary for each circuit block.
Image signal processing circuit 31 allocates gradation values to each discharge cell, based on an input image signal, and converts the respective gradation values into image data for output. This image data is data where the light emission and no light emission in each discharge cell in each subfield are correlated with “1” and “0”, respectively, in the respective bits of digital signals.
Data electrode driver circuit 32 converts the image data output from image signal processing circuit 31 into address pulses corresponding to data electrode D1-data electrode Dm, and applies the address pulses to respective data electrode D1-data electrode Dm. Data electrode driver circuit 32 is divided into a plurality of circuits such that each circuit drives a predetermined number of data electrodes 22. Each circuit is integrated into one semiconductor integrated circuit (monolithic IC). Hereinafter, this monolithic IC is referred to as “data driver”. That is, data electrode driver circuit 32 is formed of a plurality of data drivers 40. In this exemplary embodiment, the predetermined number is 384, so that a circuit for driving 384 data electrodes 22 is integrated as one data driver 40. Eight data drivers 40 form data electrode driver circuit 32.
Based on a horizontal synchronization signal and a vertical synchronization signal, timing generation circuit 35 generates various timing signals for controlling the operation of each circuit, and supplies the timing signals to each circuit.
In response to the timing signals supplied from timing generation circuit 35, scan electrode driver circuit 33 drives each of scan electrode SC1-scan electrode SCn.
In response to the timing signals supplied from timing generation circuit 35, sustain electrode driver circuit 34 drives each of sustain electrode SU1-sustain electrode SUn.
Next, data driver 40 is described.
Shift register part 141 has a plurality of latches 41. A change in a synchronization signal triggers each latch 41 to output an input signal. Each latch 41 receives clock signal Dck as the synchronization signal. For instance, in synchronization with the timing when clock signal Dck changes from the Lo state to the Hi state, an input signal is output. Clock signal Dck is a signal (clock signal) that repeats the Lo and Hi states in a predetermined cycle. Therefore, each latch 41 operates as a delay circuit for delaying an input signal by one clock period of clock signal Dck and outputting the delayed signal.
In shift register part 141, the plurality of latches 41 is connected in series such that the output of latch 41j is input to latch 41j+1 at the subsequent stage, for example. With this configuration, the input signal is gradually delayed with a delay time corresponding to the period of clock signal Dck in synchronization with clock signal Dck.
Shift register part 141 has latches 41 at least equal in number to data electrodes 22 to be driven by data driver 40. The shift register part gradually delays bit Q corresponding to a subfield in serially transferred image data (hereinafter, simply referred to as “image data Q”) in synchronization with clock signal Dck. The serial transfer is one of data transfer methods, in which data formed of a plurality of bits is transferred on a bit-by-bit basis. For 8-bit data, for example, eight consecutive digital signals (“1” or “0”) are transferred as 1-bit signal.
Therefore, in shift register part 141, serially transferred image data Q is sequentially passed through the plurality of latches 41 connected in series, and thereby the data can be delayed by one clock period of clock signal Dck. (Hereinafter, the serially transferred data is also simply referred to as “serial data”)
Here, for ease of explanation, a description is provided for the operation of one data driver 40 that drives three data electrodes 22, i.e. data electrode Dj−1, data electrode Dj, and data electrode Dj+1.
In image data Q, bit signals that represent light emission and no light emission corresponding to respective data electrodes 22 in each subfield are shown as a serial signal. Thus, in this example, image data Q includes the data that represents light emission and no light emission in respective data electrode Dj−1, data electrode Dj, and data electrode Dj+1.
For instance, suppose, in the address operation on the n-th line in a subfield, the discharge cells corresponding to data electrode Dj−1, data electrode Dj, and data electrode Dj+1 are lit, unlit, and lit, respectively. In this case, the data “1” representing light emission is allocated to data electrode Dj−1, the data “0” representing no light emission is allocated to data electrode Dj, and the data “1” is allocated to data electrode Dj+1. Therefore, image data Q includes the temporally successive data items “1, 0, 1”.
In this manner, image data Q includes data corresponding to each of data electrodes 22 in a temporally successive state. However, an address pulse needs to be applied simultaneously to each of data electrodes 22. In the above example, the data items “1, 0, 1” need to be allocated simultaneously to respective data electrode Dj−1, data electrode Dj, and data electrode Dj+1.
The part that serves to extract the plurality of temporally successive data items at the same timing is shift register part 141. In shift register part 141, image data Q is sequentially delayed in synchronization with clock signal Dck, using the plurality of latches 41 connected in series with each other. Therefore, at an instant, image data Qj−1 corresponding to data electrode Dj−1 is output from latch 41j−1, image data Qj corresponding to data electrode Dj is output from latch 41j, and image data Qj+1 corresponding to data electrode Dj+1 is output from latch 41j+1. In this manner, each latch 41 outputs proper image data Q corresponding to data electrode 22 connected to that latch 41.
However, at the timing of the next change in clock signal Dck, the signal output from each latch 41 changes. For example, at the next timing, image data Qj−2 corresponding to data electrode Dj−2 is output from latch 41j−1, image data Qj−1 corresponding to data electrode Dj−1 is output from latch 41j, and image data Qj corresponding to data electrode Dj is output from latch 41j+1. In this manner, if an appropriate timing is missed, image data Q that does not correspond to data electrodes 22 is output from respective latches 41.
Therefore, data driver 40 needs to perform an operation such that when each latch 41 outputs proper image data Q corresponding to data electrode 22 connected to that latch 41, this image data Q is held. Data latch part 142 performs this operation.
Data latch part 142 has latches 42 equal in number to latches 41 in shift register part 141. Latches 42 correspond to respective data electrodes 22 to be driven by data driver 40, and are connected to respective latches 41. For example, the output from latch 41j−1 is input to latch 42j−1 corresponding to data electrode Dj−1, the output from latch 41j is input to latch 42j corresponding to data electrode Dj, and the output from latch 41j+1 is input to latch 42j+1 corresponding to data electrode Dj+1.
Address timing signal Le is input to each latch 42 as a synchronization signal. In order to obtain this timing signal, in address timing generation part 145, the delay time of address timing signal Le0 generated in timing generation circuit 35 is adjusted. A change in the synchronization signal (e.g. from the Lo state to the Hi state) triggers an input signal to be output.
Address timing signal Le0 is a periodic pulse waveform of positive polarity in the Lo state normally and in the Hi state only in one clock period of clock signal Dck, for example. The cycle in which address timing signal Le0 becomes Hi is equal to the cycle in which the address pulses are generated. Address timing signal Le0 is generated in timing generation circuit 35 so as to change from the Lo state to the Hi state at the timing when each latch 41 outputs proper data corresponding to data electrode 22 connected that latch 41.
Latches 42 hold the output signals in the period during which address timing signal Le is in the Lo state. Thus, in response to address timing signal Le, each latch 42 operates to output the signal output from corresponding latch 41, at an appropriate timing, and to hold the output signal. Therefore, the signal output from each latch 42 is image data DQ corresponding to data electrode 22 connected to that latch 42. For example, when image data Qj is output from latch 41j, latch 42j acquires image data Qj and outputs image data DQj corresponding to data electrode Dj.
In this exemplary embodiment, address timing signal Le input to each latch 42 as the synchronization signal is a signal obtained in the following manner. In address timing generation part 145, the delay time of address timing signal Le0 generated in timing generation circuit 35 is adjusted in response to an image displayed on panel 10. This operation will be detailed later.
Address pulse output part 143 includes address pulse generators 43 equal in number to latches 41 in shift register part 141. Each address pulse generator 43 corresponds to data electrode 22 driven by data driver 40. Address pulse generator 43 generates an address pulse to be applied to corresponding data electrode 22 driven by data driver 40. For example, the address pulse output from address pulse generator 43j is applied to data electrode 22Dj. The address pulse output from address pulse generator 43j+1 is applied to data electrode 22Dj+1.
Address pulse generator 43 has an output buffer. Each output buffer includes switching element Tr1 for outputting voltage Vd on the high voltage side of the address pulse, and switching element Tr2 for outputting voltage 0 (V) on the low voltage side of the address pulse. By outputting voltage Vd on the high voltage side or voltage 0 (V) on the low voltage side, the address pulse at voltage Vd is generated. Each output buffer applies the address pulse to corresponding data electrode 22 by connecting data electrode 22 to voltage Vd or voltage 0 (V), based on image data DQ. In
Each address pulse generator 43 generates an address pulse in response to image data DQ output from corresponding latch 42. When image data DQ is “1” (Hi)”, switching element Tr1 for outputting voltage Vd on the high voltage side is set to ON so as to apply voltage Vd to corresponding data electrode 22. When image data DQ is “0” (Lo)”, switching element Tr2 for outputting voltage 0 (V) on the low voltage side is set to ON so as to apply voltage 0 (V) to corresponding data electrode 22. Image data DQ changes in synchronization with address timing signal Le output from address timing generation part 145. Therefore, the timing when the address pulse is output from address pulse generator 43 is in synchronization with address timing signal Le.
In this exemplary embodiment, the output buffer included in address pulse generator 43 has a current capacity (current supply capability) capable of driving a capacitive load of capacitance (Cg+4Cc), which is the capacitance when the drive load of data electrode 22 is at the maximum. Thus, when the drive load of data electrode 22 is small, the amount of current instantaneously flowing from data driver 40 to data electrodes 22 at the generation of address pulses increases, which increases unnecessary radiation. Then, in this exemplary embodiment, in order to reduce the unnecessary radiation, address timing signal Le is used as the synchronization signal. This address timing signal is obtained by adjusting the delay time of address timing signal Le0 in address timing generation part 145 based on the calculation result in address timing control part 144. This operation will be detailed later.
Address timing control part 144 includes load calculators 44 equal in number to latches 41 in shift register part 141. Load calculators 44 correspond to respective data electrodes 22 to be driven by data driver 40. Control signal C, i.e. the output signal from each load calculator 44, is input to corresponding address timing selector 45. Each load calculator 44 has self-load calculator 50, adjacent-load calculator 60, and control signal output part 70. Based on image data Q, each load calculator calculates the magnitude of the load capacitance in corresponding data electrode 22 to be driven by data driver 40. For example, load calculator 44j has self-load calculator 50j, adjacent-load calculator 60j, and control signal output part 70j, and calculates the magnitude of the load capacitance of data electrode Dj, based on image data Qj. The load calculator outputs control signal Cj based on the result.
Address timing generation part 145 includes a plurality of delay parts, and address timing selectors 45 equal in number to latches 41 in shift register part 141. In this exemplary embodiment, the address timing generation part includes, as a plurality of delay parts, three delay parts, i.e. delay part 46a, delay part 46b, and delay part 46c.
Delay part 46a delays address timing signal Le0 generated in timing generation circuit 35 by “first time T1”, and outputs it as “first address timing signal Le1”. Delay part 46b delays address timing signal Le0 by “second time T2”, and outputs it as “second address timing signal Le2”. Delay part 46c delays address timing signal Le0 by “third time T3”, and outputs it as “third address timing signal Le3”. In this exemplary embodiment, first time T1 is set to 0 nsec (i.e. first address timing signal Le1=address timing signal Le0). Second time T2 is set to 50 nsec. Third time T3 is set to 100 nsec, which is approximately twice the period of second time T2.
Third address timing signal Le3 may be generated by setting the delay time of delay part 46c equal to the delay time of delay part 46b, and passing the output from delay part 46b to delay part 46c.
Address timing selectors 45 correspond to respective data electrodes 22 to be driven by data driver 40, and the output signals from address timing selectors 45 are input to corresponding latches 42 as synchronization signals. For example, data electrode Dj−1 corresponds to address timing selector 45j−1, and the output signal from address timing selector 45j−1 is input to latch 42j−1 as a synchronization signal. Address timing selector 45j corresponds to data electrode Dj, and the output signal from address timing selector 45j is input to latch 42j as a synchronization signal. Address timing selector 45j+1 corresponds to data electrode Dj+1, and the output signal from address timing selector 45j+1 is input to latch 42j+1 as a synchronization signal.
Each address timing selector 45 is formed of a selecting circuit for selecting one of two input signals based on control signal C and outputting the selected signal. To one of the input terminals of address timing selector 45 (the input terminal selected when control signal C is “1”, for example), address timing signal Le0 supplied from timing generation circuit 35 is input. To the other of the input terminals of address timing selector 45 (the input terminal selected when control signal C is “0”, for example), one of first address timing signal Le1 output from delay part 46a, second address timing signal Le2 output from delay part 46b, and third address timing signal Le3 output from delay part 46c is input.
At this time, in this exemplary embodiment, consecutive three address timing selectors 45 (e.g. address timing selector 45j−1, address timing selector 45j, and address timing selector 45j+1) are grouped into one set. In each of one set of address timing selectors 45, address timing signal Le having different delay time is input to the other input terminal. For example, first address timing signal Le1 is input to the other input terminal of address timing selector 45j−1, second address timing signal Le2 is input to the other input terminal of address timing selector 45j, and third address timing signal Le3 is input to the other input terminal of address timing selector 45j+1. Similarly, in each of the other sets of address timing selectors 45, address timing signal Le having different delay time is input to the other input terminal.
With this configuration, in data driver 40, when control signals C output from address timing control part 144 are all “1”, for example, address timing signal Le output from address timing generation part 145 are all equal to address timing signal Le0. Conversely, when control signals C output from address timing control part 144 are all “0”, one third of address timing signals Le output from address timing generation part 145 is first address timing signal Le1, one third is second address timing signal Le2, and one third is third address timing signal Le3.
In this manner, each address timing selector 45 outputs address timing signals Le having different delay time, in response to control signals C output from address timing control part 144. Thus, latch 42 outputs image data DQ at a timing corresponding to address timing signal Le, and address pulse generator 43 outputs an address pulse at a timing corresponding to image data DQ.
In data driver 40, the generation timing of the address pulse to be output from address pulse generator 43 is controlled based on the calculation result in corresponding load calculator 44.
How first address timing signal Le1, second address timing signal Le2, and third address timing signal Le 3 are input to the other input terminals of address timing selectors 45 is not limited to the above configuration. Any configuration can be used as far as when control signals C output from address timing control part 144 are all “0”, one third of the signals output from address timing generator 145 is first address timing signal Le1, one third is second address timing signal Le2, and one third is third address timing signal Le3.
In this exemplary embodiment, in data driver 40, each of the numbers of latches 42, address pulse generators 43, load calculators 44, and address timing selectors 45 is equal to the number of latches 41 in shift register part 141. However, each of the numbers of latches 41, latches 42, address pulse generators 43, load calculators 44 and address timing selectors 45 may be equal to or greater than the number of data electrodes to be driven by data driver 40.
Next, each load calculator 44 is detailed.
In this exemplary embodiment, a description is provided for self-load calculator 50j, adjacent-load calculator 60j, and control signal output part 70j included in load calculator 44j corresponding to data electrode Dj. Each of the other load calculators 44 has an identical configuration.
As shown in
Self-load calculator 50j operates so as to detect how the address operation on the discharge cell in the line one line (one horizontal synchronization period) preceding the line of a focused discharge cell is with respect to the address operation on the focused discharge cell. Here, for instance, when the address operation is performed on the respective discharge cells of panel 10 sequentially from the upper lines to the lower lines, the discharge cell in the line one-line-preceding the line of a focused discharge cell is the discharge cell just above the focused discharge cell. When the address operation is performed on the respective discharge cells of panel 10 sequentially from the lower lines to the upper lines, the discharge cell just under the focused discharge cell is the discharge cell in the line one-line-preceding the line of the focused discharge cell. In the case of so-called interlaced scanning, i.e. when the address operation is performed on odd-numbered lines first and on even-numbered lines next, the discharge cell just above or just under the focused discharge cell via one discharge cell is the one-line-preceding discharge cell.
In this manner, in this exemplary embodiment, the “one-line-preceding discharge cell” is the discharge cell in the line one line (one horizontal synchronization period) preceding the line of a focused discharge cell in the address operation, and is not limited to the discharge cell that is adjacent to the focused discharge cell in the extending direction of data electrode 22 (the discharge cell adjacent just above or just under the focused discharge cell of panel 10).
Self-load calculator 50j compares the address operation on a focused discharge cell (e.g. a discharge cell in a part where data electrode Dj intersects scan electrode SCi and sustain electrode SUi) with the address operation on a one-line-preceding discharge cell (e.g. a discharge cell in a part where data electrode Dj intersects scan electrode SCi−1 and sustain electrode SUi−1). That is, self-load calculator 50j detects a relative change between the address pulse applied to a focused discharge cell on data electrode Dj and the address pulse applied to the one-line-preceding discharge cell of the focused discharge cell on data electrode Dj.
For this purpose, self-load calculator 50j needs to compare image data DQj(i) of the focused discharge cell with image data DQj(i−1) of the one-line-preceding discharge cell of the focused discharge cell.
Image data Qj is serial data as described above, and includes image data Qj(i) corresponding to image data DQj(i) of the focused discharge cell. Therefore, appropriately delaying image data DQj that is output from latch 42j and input to self-load calculator 50j can make an instant when the timing of image data DQj(i−1) of the one-line-preceding discharge cell of the focused discharge cell is matched to the timing of image data Qj(i) corresponding to image data DQj(i) of the focused discharge cell in self-load calculator 50j. In the diagram, the circuit for this delay is omitted. At timings except this timing, unnecessary calculation results, such as that of image data DQj(i−1) and image data DQj−1(i) and that of image data DQj(i−1) and image data DQj+1(i), are output.
Therefore, load calculator 44j needs to perform an operation of holding the calculation result obtained at an appropriate timing when the necessary logic operation is performed in self-load calculator 50j. The part that performs the operation is control signal output part 70j at the subsequent stage. That is, in this exemplary embodiment, control signal output part 70j is operated so as to hold the data obtained at an appropriate timing when the necessary logic operation is performed.
Hereinafter, for ease of explanation, a description is provided for a case where image data DQj input to self-load calculator 50j is image data DQj(i−1) of the one-line-preceding discharge cell of a focused discharge cell, and image data Qj is image data DQj(i) of the focused discharge cell.
Each of logic gate 51j and logic gate 52j is a logic gate for performing an AND operation. Only when the signals input to two input terminals are both “1 (Hi)”, this logic gate outputs “1 (Hi)”, and otherwise outputs “0 (Lo)”. In the diagram, each of logic gate 51j and logic gate 52j has a circular mark on one of the input terminals. This mark represents an inverter, which performs a logic inversion operation (an operation of inverting “1” to “0”, and “0” to “1”). Therefore, image data Qj is logically inverted and input to logic gate 51j, and image data DQj is logically inverted and input to logic gate 52j. That is, when image data DQj is “1” and image data Qj is “0”, logic gate 51j outputs “1”, and otherwise outputs “0”. When image data DQj is “0” and image data Qj is “1”, logic gate 52j outputs “1”, and otherwise outputs “0”.
Logic gate 53j is a logic gate for performing an exclusive OR operation. Only when one of the signals input to the two input terminals is “0” and the other is “1”, the operation result is “1”. When the signals input to the two input terminals are both “0” or are both “1”, the operation result is “0”. Since the output terminal of logic gate 53j has a circular mark in the diagram, the operation result in logic gate 53j is logically inverted for output. Therefore, logic gate 53j outputs “1” only when image data DQj and image data Qj are both “0” or are both “1”, and otherwise outputs “0”.
Therefore, in self-load calculator 50j, when the one-line-preceding discharge cell of a focused discharge cell is lit and the focused discharge cell is unlit, i.e. image data DQj(i−1) is “1” and image data Qj(i) is “0”, output HLj from logic gate 51j is “1” and output LHj and output Xj are both “0”. When the one-line-preceding discharge cell of a focused discharge cell is unlit and the focused discharge cell is lit, i.e. image data DQj(i−1) is “0” and image data DQj(i) is “1”, output LHj from logic gate 52j is “1” and output HLj and output Xj are both “0”. When the one-line-preceding discharge cell of a focused discharge cell is unlit and the focused discharge cell is unlit, i.e. image data DQj(i−1) is “0” and image data DQj(i) is “0”, and when the one-line-preceding discharge cell of a focused discharge cell is lit and the focused discharge cell is lit, i.e. image data DQj(i−1) is “1” and image data DQj(i) is “1”, output Xj from logic gate 53j is “1” and output HLj and output LHj are both “0”.
As shown in
The adjacent-load calculator calculates the magnitude of the load with respect to capacitance Cc between data electrode Dj and data electrode Dj−1 and between data electrode Dj and data electrode Dj+1, based on the output from self-load calculator 50j corresponding to data electrode Dj, the output from self-load calculator 50j−1 corresponding to data electrode Dj−1 adjacent to data electrode Dj, and the output from self-load calculator 50j+1 corresponding to data electrode Dj+1 adjacent to data electrode Dj. That is, the adjacent-load calculator calculates the load capacitance in data electrode 22 corresponding to the focused discharge cell by comparing the image data of the focused discharge cell with the image data of the discharge cells adjacent to the focused discharge cell in the extending direction of display electrode pair 14.
Each of logic gate 61j, logic gate 62j, logic gate 64j, logic gate 66j, logic gate 67j, and logic gate 69j is a logic gate for performing an AND operation. Each of logic gate 63j, logic gate 65j, and logic gate 68j is a logic gate for performing an OR operation. Only when the signals input to the two input terminals are both “0”, the logic gates for performing an OR operation outputs “0”, and otherwise outputs “1”.
Output HLj−1, i.e. the output from self-load calculator 50j−1, and output LHj, i.e. the output from self-load calculator 50j, are input to logic gate 61j. Only when each input is “1”, the logic gate outputs “1”, and otherwise outputs “0”.
Output LHj−1, i.e. the output from self-load calculator 50j−1, and output HLj, i.e. the output from self-load calculator 50j, are input to logic gate 62j. Only when each input is “1”, the logic gate outputs “1”, and otherwise outputs “0”.
Output HLj+1, i.e. the output from self-load calculator 50j+1, and output LHj, i.e. the output from self-load calculator 50j, are input to logic gate 66j. Only when each input is “1”, the logic gate outputs “1”, and otherwise outputs “0”.
Output LHj+1, i.e. the output from self-load calculator 50j+1, and output HLj, i.e. the output from self-load calculator 50j, are input to logic gate 67j. Only when each input is “1”, the logic gate outputs “1”, and otherwise outputs “0”.
Output HLj and output LHj, i.e. the outputs from self-load calculator 50j, are input to logic gate 65j. Only when each input is “0”, the logic gate outputs “0”, and otherwise outputs “1”.
The output from logic gate 61j and the output from logic gate 62j are input to logic gate 63j. Only when each input is “0”, the logic gate outputs “0”, and otherwise outputs “1”.
The output from logic gate 66j and the output from logic gate 67j are input to logic gate 68j. Only when each input is “0”, the logic gate outputs “0”, and otherwise outputs “1”.
Output Xj−1, i.e. the output from self-load calculator 50j−1, and the output from logic gate 65j are input to logic gate 64j. Only when each input is “1”, the logic gate outputs “1”, and otherwise outputs “0”.
Output Xj+1, the output from self-load calculator 50j+1, and the output from logic gate 65j are input to logic gate 69j. Only when each input is “1”, the logic gate outputs “1”, and otherwise outputs “0”.
In this exemplary embodiment, the output from logic gate 63j is output L2j, the output from logic gate 64j is output L1j, the output from logic gate 68j is output R2j, and the output from logic gate 69j is output R1j.
Therefore, in adjacent-load calculator 60j, the following results are obtained. In the case where a change between the lines in image data Qj−1 of data electrode Dj−1 adjacent to data electrode Dj on the left side (a change from image data DQj−1(i−1) to image data DQj−1(i)) is in opposite phase with a change between the lines in image data Qj of data electrode Dj (a change from image data DQj(i−1) to image data DQj(i)), the output from logic gate 61j or logic gate 62j is “1” and output L2j from logic gate 63j is “1”.
In the case where image data Qj of data electrode Dj is changed between the lines (the value of image data DQj(i−1) is different from the value of image data DQj(i)), and image data Qj−1 of data electrode Dj−1 adjacent to data electrode Dj on the left side is not changed between the lines (the value of image data DQj−1(i−1) is equal to the value of image data DQj−1(i)), output L1j from logic gate 64j is “1”.
Similarly, in the case where a change between the lines in image data Qj+1 of data electrode Dj+1 adjacent to data electrode Dj on the right side (a change from image data DQj+1(i−1) to image data DQj+1(i)) is in opposite phase with a change between the lines in image data Qj of data electrode Dj (a change from image data DQj(i−1) to image data DQj(i)), the output from logic gate 66j or logic gate 67j is “1” and output R2j from logic gate 68j is “1”.
In the case where image data Qj of data electrode Dj is changed between the lines (the value of image data DQj(i−1) is different from the value of image data DQj(i)), and image data Qj+1 of data electrode Dj+1 adjacent to data electrode Dj on the right side is not changed between the lines (the value of image data Dj+1(i−1) is equal to the value of image data DQj+1(i)), output R1j from logic gate 69j is “1”.
As shown in
The number of latches in control signal output part 70j is set so as to correspond to the number of output buffers in address pulse generator 43j.
Logic gate 71j is a logic gate for performing an OR operation. Logic gate 72j is a logic gate for performing an AND operation.
Output L1j and output R1j output from adjacent-load calculator 60j are input to logic gate 72j. Only when each input is “1”, the logic gate outputs “1”, and otherwise outputs “0”.
Output L2j and output R2j output from adjacent-load calculator 60j, and the output signal from logic gate 72j are input to logic gate 71j. Only when each output is “0”, the logic gate outputs “0”, and otherwise outputs “1”.
As a synchronization signal, timing signal LE generated in timing generation circuit 35 is input to latch 73j. A change in this synchronization signal (e.g. a change from the Lo state to the Hi state) triggers an input signal to be output. In
Timing signal LE is a periodic pulse waveform of positive polarity in the Lo state normally and in the Hi state only in one clock period of clock signal Dck, for example. The cycle in which timing signal LE becomes Hi is equal to the cycle in which the address pulses are generated. As described above, timing signal LE is generated in timing generation circuit 35 so as to allow latch 73j to hold the above operation results obtained at the instant when the timing of image data DQj(i−1) is matched to the timing of image data Qj(i) corresponding to image data DQj(i). In latch 73j, the timing of the output signals are appropriately adjusted such that control signal Cj is updated in synchronization with the timing at which an address pulse is output from address pulse generator 43j.
With the operation of these respective circuits, control signal Cj output from control signal output part 70j is “0” in pattern A and pattern B as described later. Control signal Cj is “1” in pattern C, pattern D, pattern E, and pattern F as described later.
Load calculator 44j outputs control signals in the following six patterns. For instance, suppose image data Qj of data electrode Dj is changed between the lines (the value of image data DQj(i−1) is different from the value of image data DQj(i)), and a change between the lines in image data Qj−1 of data electrode Dj−1 adjacent to data electrode Dj on the left side and a change between the lines in image data Qj+1 of data electrode Dj+1 adjacent to data electrode Dj on the right side are in phase with the change between the lines in image data Qj (the values of image data DQj−1(i−1) and image data DQj+1(i−1) are equal to the value of image data DQj(i−1), and the values of image data DQj−1(i) and image data DQj+1(i) are equal to the value of image data DQj(i)). In this case, output L2j, output L1j, output R2j, and output R1j from adjacent-load calculator 60j are all “0”, and control signal Cj is “0”. This is pattern A, which will be described later.
For instance, suppose image data Qj of data electrode Dj is changed between the lines (the value of image data DQj(i−1) is different from the value of image data DQj(i)), a change between the lines in the image data of one of data electrode Dj−1 and data electrode Dj+1 adjacent to data electrode Dj is in phase with the change between the lines in image data Qj (e.g. the value of image data DQj−1(i−1) is equal to the value of image data DQj(i−1), and the value of image data DQj−1(i) is equal to the value of image data DQj(i)), and the image data of the other of the data electrodes is not changed between the lines (e.g. the value of image data DQj+1(i−1) is equal to the value of image DQj+1(i)). In this case, only one of output L1j and output R1j from adjacent-load calculator 60j is “1”, and the other of output L1j and output R1j, as well as output L2j and output R2j are “0”. Therefore, control signal Cj is “0”. This is pattern B, which will be described later.
For instance, suppose image data Qj of data electrode Dj is changed between the lines (the value of image data DQj(i−1) is different from the value of image data DQj(i)) and neither image data Qj−1 of data electrode Dj−1 nor image data Qj+1 of data electrode Dj+1 adjacent to data electrode Dj is changed between the lines (the value of image data DQj−1(i−1) is equal to the value of image data DQj−1(i), and the value of image data DQj+1(i−1) is equal to the value of image data DQj+1(i)). Alternatively, suppose image data Qj is changed between the lines, a change between the lines in the image data of one of data electrode Dj−1 and data electrode Dj+1 is in opposite phase with the change between the lines in image data Qj (e.g. the value of image data DQj−1(i−1) is different from the value of image data DQj(i−1), and the value of image data DQj−1(i) is different from the value of image data DQj(i)), and a change between the lines in the image data of the other of the data electrodes is in phase with the change between the lines in image data Qj (e.g. the value of image data DQj+1(i−1) is equal to the value of image data DQj(i−1), and the value of image data DQj+1(i) is equal to the value of image data DQj(i)). In these cases, output L1j and output R1j from adjacent-load calculator 60j are both “1” and the remaining outputs are “0”, or only one of output L2j and output R2j is “1” and the remaining outputs are “0”. Therefore, control signal Cj is “1”. This is pattern C or pattern D, which will be described later.
For instance, suppose image data Qj of data electrode Dj is changed between the lines (the value of image data DQj(i−1) is different from the value of image data DQj(i)), a change between the lines in the image data of one of data electrode Dj−1 and data electrode Dj+1 adjacent to data electrode Dj is in opposite phase with the change between the lines in image data Qj (e.g. the value of image data DQj−1(i−1) is different from the value of image data DQj(i−1), and the value of image data DQj−1(i) is different from the value of image data DQj(i)), and the image data of the other of the data electrodes is not changed between the lines (e.g. the value of image data DQj+1(i−1) is equal to the value of image data DQj+1(i)). In this case, only one of output L2j and output R2j from adjacent-load calculator 60j is “1”. In the case where output L2j is “1”, output R1j is “1”. In the case where output R2j is “1”, output L1j is “1”. Therefore, control signal Cj is “1”. This is pattern E, which will be described later.
For instance, suppose image data Qj of data electrode Dj is changed between the lines (the value of image data DQj(i−1) is different from the value of image data DQj(i)), changes between the lines in image data Qj−1 of data electrode Dj−1 and image data Qj+1 of data electrode Dj+1 adjacent to data electrode Dj are in opposite phase with the change between the lines in image data Qj (the values of image data DQj−1(i−1) and image data DQj+1(i−1) are different from the value of DQj(i−1), and the values of image data DQj−1(i) and image data DQj+1(i) are different from the value of DQj(i)). In this case, output L2j and output R2j from adjacent-load calculator 60j are both “1”. Therefore, control signal Cj is “1”. This is pattern F, which will be described later.
That is, the load capacitance of data electrode Dj is capacitance Cg in pattern A, and is capacitance (Cg+Cc) in pattern B. Therefore, when the load capacitance of data electrode Dj is equal to or lower than capacitance (Cg+Cc), control signal Cj is “0”. The load capacitance of data electrode Dj is capacitance (Cg+2Cc) in pattern C and pattern D, capacitance (Cg+3Cc) in pattern E, and capacitance (Cg+4Cc) in pattern F. Therefore, in the case where the load capacitance of data electrode Dj is equal to or higher than capacitance (Cg+2Cc), control signal Cj is “1”.
As described above, address timing selector 45 included in address timing generation part 145 outputs one of the following address timing signals Le: “address timing signal Le0”, “first address timing signal Le1” obtained by delaying address timing signal Le0 by “first time T1”, “second address timing signal Le2” obtained by delaying address timing signal Le0 by “second time T2”, and “third address timing signal Le3” obtained by delaying address timing signal Le0 by “third time T3”. When control signal C is “1”, address timing signal Le0 is output as address timing signal Le. When control signal C is “0”, one of first address timing signal Le1, second address timing signal Le2, and third address timing signal Le3 is output as address timing signal Le.
Address timing signal Le is input to latch 42 of data latch part 142 as a synchronization signal. In synchronization with address timing signal Le input as the synchronization signal, latch 42 outputs image data DQ, and address pulse generator 43 generates an address pulse in synchronization with image data DQ.
Therefore, address pulse generator 43 outputs an address pulse in synchronization with address timing signal LeO. When control signal C is “0” i.e. the load capacitance of data electrode 22 is equal to or lower than capacitance (Cg+Cc), address pulse generator 43 outputs an address pulse in synchronization with first address timing signal Le1, second address timing signal Le2, or third address timing signal Le3.
With this operation, in data driver 40, when control signals C output from address timing control part 144 are all “0”, one third of the address pulses output from address pulse generator 43 is in synchronization with first address timing signal Le1, one third is in synchronization with second address timing signal Le2, and one third is in synchronization with third address timing signal Le3. Therefore, in one address operation, address pulses having different timings of rising edges are applied to data electrodes 22 from data driver 40.
As described above, the output buffer included in address pulse generator 43 has a current capacity (current supply capability) capable of driving a capacitive load of capacitance (Cg+4Cc) when the drive load of data electrode 22 is at the maximum. For this reason, when the drive load of data electrode 22 is small, the amount of current instantaneously flowing from address pulse generator 43 to data electrode 22 (peak current) in generation of an address pulse is large. At this time, if the timings of the rising edges of the address pulses output from data driver 40 are matched to each other, the timings at which the peak current flows are matched. Thus, an extremely large current instantaneously flows from data driver 40 to data electrodes 22, which can cause large unnecessary radiation.
However, in this exemplary embodiment, when the load capacitance of data electrode 22 is equal to or lower than capacitance (Cg+Cc), control signal C is “0” and address pulse generator 43 outputs an address pulse in synchronization with first address timing signal Le1, second address timing signal Le2, or third address timing signal Le3. That is, in one address operation, data driver 40 outputs an address pulse in synchronization with first address timing signal Le1, an address pulse in synchronization with second address timing signal Le2, and an address pulse in synchronization with third address timing signal Le3 in a mixed state. This distributes the timings of the rising edges of the address pulses to be applied to data electrodes 22 and distributes the timings at which the peak current flows. Thereby, the maximum value of the current instantaneously flowing from data driver 40 to data electrodes 22 can be reduced, and thus unnecessary radiation can be reduced.
When the drive load of data electrode 22 is large, the amount of current instantaneously flowing from address pulse generator 43 to data electrode 22 (peak current) in generation of the address pulse is suppressed. Thus, even if the timings of the rising edges of the address pulses output from data driver 40 are matched to each other, large unnecessary radiation is unlikely to occur.
In this exemplary embodiment, driving in this manner can distribute the timings at which address pulses are generated appropriately for the display image, cause an address discharge stably, and suppress unnecessary radiation. Hereinafter, a description is provided for the reason.
Latch 73 can be omitted when the timing at which address timing signal Le0 is generated, the timing at which control signal C is output from control signal output part 70, and the timing of image data Q are adjusted so as to be matched appropriately to each other.
As described above, capacitance Cg is present between data electrode Dj and whole display electrode pairs 14, capacitance Cc (hereinafter, referred to as “capacitance Ccl”) is present between data electrode Dj and data electrode Dj−1 adjacent to data electrode Dj on the left side, and capacitance Cc (hereinafter, referred to as “capacitance Ccr”) is present between data electrode Dj and data electrode Dj+1 adjacent to data electrode Dj on the right side.
When image data Qj of data electrode Dj is changed from “0” to “1” between the lines, address pulse generator 43j needs to charge capacitance Cg. At this time, in the case where a change between the lines in image data Qj−1 of data electrode Dj−1 is in phase with the change between the lines in image data Qj, that is, the change is from “0” to “1”, capacitance Ccl does not need to be charged. Therefore, capacitance Ccl is substantially 0. Similarly, in the case where a change between the lines in image data Qj+1 of data electrode Dj+1 is in phase with the change between the lines in image data Qj, that is, the change is from “0” to “1”, capacitance Ccr does not need to be charged. Therefore, capacitance Ccr is also substantially 0. As a result, the load capacitance (equivalent capacitance) generated in data electrode Dj at this time is capacitance Cg. This is “pattern A” shown in
For instance, suppose when image data Qj of data electrode Dj is changed from “0” to “1” between the lines, a change between the lines in image data Qj+1 of data electrode Dj+1 is in phase with the change between the lines in image data Qj, and image data Qj−1 of data electrode Dj−1 is not changed between the lines (from “0” to “0”, or from “1” to “1”). In this case, capacitance Ccr is substantially 0 but capacitance Ccl occurs. For this reason, address pulse generator 43j needs to charge capacitance Ccl in addition to capacitance Cg. Therefore, the load capacitance (equivalent capacitance) generated in data electrode Dj at this time is capacitance (Cg+Cc) (where capacitance Ccl=capacitance Cc). In the case where image data Qj+1 is not changed between the lines and a change between the lines in image data Qj−1 is in phase with the change between the lines in image data Qj, the same result is obtained. This is “pattern B” shown in
For instance, suppose when image data Qj of data electrode Dj is changed from “0” to “1” between the lines, image data Qj−1 of data electrode Dj−1 and image data Qj+1 of data electrode Dj+1 are not changed between the lines (from “0” to “0”, or from “1” to “1”). In this case, both capacitance Ccl and capacitance Ccr occur. Therefore, the load capacitance (equivalent capacitance) generated in data electrode Dj at this time is capacitance (Cg+2Cc) (where capacitance Ccl=capacitance Ccr=capacitance Cc). This is “pattern C” shown in
For instance, suppose when image data Qj of data electrode Dj is changed from “0” to “1” between the lines, a change between the lines in image data Qj+1 of data electrode Dj+1 is in phase with the change between the lines in image data Qj, and a change between the lines in image data Qj−1 of data electrode Dj−1 (from “1” to “0”) is in opposite phase with the change between the lines in image data Qj. In this case, capacitance Ccr is substantially 0, but address pulse generator 43j needs to charge capacitance Ccl against the change in image data Qj−1 in opposite phase. Thus, the current necessary for charging data electrode Dj is twice as large as that when image data Qj−1 is not changed between the lines. This is equivalent to the case where capacitance 2Ccl, which is twice as high as capacitance Ccl, is connected as a load. Therefore, the load capacitance (equivalent capacitance) generated in data electrode Dj at this time is capacitance (Cg+2Cc) (where capacitance Ccl=capacitance Cc). Also in the case where a change between the lines in image data Qj−1 is in phase with the change between the lines in image data Qj, and a change between the lines in image data Qj+1 is in opposite phase with the change between the lines in image data Qj, the same result is obtained. This is “pattern D” shown in
For instance, suppose when image data Qj of data electrode Dj is changed from “0” to “1” between the lines, image data Qj+1 of data electrode Dj+1 is not changed between the lines (from “0” to “0”, or from “1” to “1”), and a change in image data Qj−1 of data electrode Dj−1 (from “1” to “0”) is in opposite phase with the change between the lines in image data Qj. In this case, address pulse generator 43j needs to charge capacitance Ccr and capacitance 2Ccl. Therefore, the load capacitance (equivalent capacitance) generated in data electrode Dj at this time is capacitance (Cg+3Cc) (where capacitance Ccl=capacitance Ccr=capacitance Cc). Also in the case where image data Qj−1 is not changed between the lines and a change between the lines in image data Qj+1 is in opposite phase with the change between the lines in image data Qj, the same result is obtained. This is “pattern E” shown in
For instance, suppose when image data Qj of data electrode Dj is changed from “0” to “1” between the lines, a change between the lines in image data Qj−1 of data electrode Dj−1 and a change between the lines in image data Qj+1 of data electrode Dj+1 (from “1” to “0”) are in opposite phase with the change between the lines in image data Qj. In this case, address pulse generator 43j needs to charge capacitance 2Ccr and capacitance 2Ccl. Therefore, the load capacitance (equivalent capacitance) generated in data electrode Dj at this time is capacitance (Cg+4Cc) (where capacitance Ccl=capacitance Ccr=capacitance Cc). This is “pattern F” shown in
In this manner, depending on the image data, the magnitude of the load of data electrode Dj changes in five steps.
For instance, suppose when the drive load of data electrode 22 increases and thus a large amount of current needs to be supplied to data electrode 22, the amount of current that can be supplied from address pulse generator 43 is insufficient. In this case, the rising edge of the address pulse becomes gentle, which makes it difficult to cause an address discharge stably.
In order to address this problem, the output buffer in address pulse generator 43 is set in the following manner. Even when the drive load of data electrode 22 is at the maximum, i.e. the load capacitance of data electrode 22 is capacitance (Cg+4Cc), the address pulse rises with an appropriate transition time and thereby causes an address discharge stably, while the generation of unnecessary radiation is suppressed.
In this manner, the current supply capability of the output buffer in address pulse generator 43 is set appropriately for the maximum drive load of data electrode 22. Thus, as shown in
However, when the synchronization signals to be input to latches 42 in data latch part 142 are delayed adaptively to an image displayed on panel 10, i.e. the drive load of data electrodes 22, the timings of the rising edges of the address pulses output from address pulse output part 143 can be distributed under a small drive load. This operation can distribute the timings at which the peak current flows from data driver 40 to data electrodes 22, reduce the maximum value of the current flowing from data driver 40 to data electrodes 22, and prevent an increase in unnecessary radiation.
Then, in this exemplary embodiment, the synchronization signals input to latches 42 in data latch part 142 are delayed adaptively to the capacitance of the drive load of data electrode 22. That is, when the drive load of data electrode 22 is equal to or higher than capacitance (Cg+2Cc), timing signal Le input to latch 42 is timing signal LeO. When the drive load of data electrode 22 is equal to or lower than capacitance (Cg+Cc), timing signal Le input to latch 42 is one of first address timing signal Le1, second address timing signal Le2, and third address timing signal Le3. Thus, excessive current supply to data electrodes 22 is prevented in the generation of address pulses.
With this operation, the timings at which the address pulse is generated are changed adaptively to the drive load of data electrode 22. As shown in
In this exemplary embodiment, a description has been provided for the rising edge of an address pulse. The above description is also applicable to the falling edge of the address pulse.
In the configuration described in this exemplary embodiment, the timings at which address pulses are generated are distributed when the drive load of data electrode 22 is equal to or lower than capacitance (Cg+Cc). However, the present invention is not limited to this configuration. The capacitance of the drive load of data electrode 22 when timings at which address pulses are generated may be set depending on the magnitude of unnecessary radiation, the characteristics of panel 10, the specifications of plasma display apparatus 30, or the like.
In the configuration described in this exemplary embodiment, a time interval of 100 nsec is provided from first address timing signal Le1 to third address timing signal Le3. However, preferably, the time interval between the earliest address timing signal Le and the last address timing signal Le is set appropriately in the range where one address operation can be performed stably. Examples of this guideline include the time taken for the rising edge or the falling edge of the address pulse (shown “time t” in
In the configuration described in this exemplary embodiment, the timings at which address pulses are generated are distributed into three at time intervals of 50 nsec, by first address timing signal Le1, second address timing signal Le2, and third address timing signal Le3. Preferably, the number of parts into which the timings of the address pulses are distributed, and the time intervals at which the address pulses are generated are set depending on whether one address operation can be caused stably or not, the magnitude of unnecessary radiation, the characteristics of panel 10, the specifications of plasma display apparatus 30, or the like. For instance, the timings at which the address pulses are generated may be distributed into at least four. Alternatively, when the generation of unnecessary radiation is suppressed within the range of a predetermined standard on unnecessary radiation, the timings at which address pulses are generated may be distributed into two (e.g. first address timing signal Le1 and second address timing signal Le2). Thereby, the timings at which address pulses are generated can be distributed into two, so that the data driver can be formed with a simplified circuit configuration.
Hereinafter, a description is provided for a configuration where the timings at which address pulses are generated are distributed to the parts more than those of the above configuration.
Data driver 49 includes shift register part 141, data latch part 142, address pulse output part 143, address timing control part 144, and address timing generation part 148. In data driver 49, the circuit blocks operating in a manner similar to those of data driver 40 of
Address timing generation part 148 includes delay parts 48 and address timing selectors 45 equal in number to latches 41 in shift register part 141. Delay parts 48 are connected in series with each other and sequentially delays address timing signal Le0. In this exemplary embodiment, the delay time in one delay part 48 is set to 0.3 nsec. Therefore, address timing signal Le0j output from the j-th delay part 48j in the plurality of series-connected delay parts 48 is a signal obtained by delaying address timing signal Le0 by (0.3×j) nsec.
To one of the input terminals of address timing selector 45 (the input terminal selected when control signal C is “1”, for example), address timing signal Le0 supplied from timing generation circuit 35 is input. To the other of the input terminals of address timing selector 45 (the input terminal selected when control signal C is “0”, for example), a signal output from delay part 48 is input. For instance, address timing signal LeOj−1 output from delay part 48j−1 is input to the other input terminal of address timing selector 45j−1, and address timing signal Le0j output from delay part 48j is input to the other input terminal of address timing selector 45j. The operation of address timing selector 45 is similar to address timing selector 45 of
For example, data driver 49 has the following settings: when the load capacitance of data electrode 22 is equal to or higher than capacitance (Cg+2Cc), control signal C is “1”; and when the load capacitance of data electrode 22 is equal to or lower than capacitance (Cg+Cc), control signal C is “0”. In this case, as shown in
In the configuration described in the exemplary embodiments, shift register part 141 has one shift register, and one set of serial image data Q is input to shift register part 141. However, the present invention is not limited to this configuration. For example, the following configuration may be used. The shift register part includes three shift registers corresponding to image data Qr of red primary color signals, image data Qg of green primary color signals, and image data Qb of blue primary color signals. Further, image data Qr, image data Qg, and image data Qb are rearranged in accordance with the order of the arrangement of data electrodes 22, as image data Q.
The specific circuit configurations of the exemplary embodiments are shown as examples of circuit configurations, and the present invention is not limited to these circuit configurations. As long as the above functions are implemented, other circuit configurations may be used. Each latch in the exemplary embodiments may be operated in response to a negative synchronization signal, and the synchronization signal to be input to each latch may be a negative pulse signal.
The specific numerical values in the exemplary embodiments of the present invention simply show examples, and the present invention is not limited to these numerical values. Preferably, each numerical value is set optimally for the characteristics of the panel, the specifications of the plasma display apparatus, or the like.
The present invention is capable of causing a stable address discharge while suppressing unnecessary radiation, e.g. line radiation and housing radiation, and thus is useful as a plasma display apparatus and a driving method for a panel.
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP2010/006626 | 11/11/2010 | WO | 00 | 5/11/2012 |
