Plasma display device

Abstract

A plasma display device which changes, in accordance with an average luminance level of a video signal, the length of a pause period between a sustain pulse application end point at which one sustain pulse is applied in a sustain period of each of subfields and a sustain pulse application starting point at which the next sustain pulse is applied.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a plasma display device using a plasma display panel.

2. Description of the Related Art

Currently, as a thin display device, an AC type (alternating discharge type) plasma display panel becomes commercially available. In the plasma display panel, two substrates, that is, a front glass substrate and a rear glass substrate are disposed with a predetermined space as faced to each other. On the inner surface (the surface facing the rear glass substrate) of the front glass substrate as a display surface, multiple row electrode pairs are formed as sustain electrode pairs, which are paired with each other and extended in parallel. On the rear glass substrate, multiple column electrodes are extended and formed as address electrodes as intersecting with the row electrode pairs, and are coated with a fluorescent material. When seen from the display surface side, a display cell corresponding to a pixel is formed at the intersection part of the row electrode pair with the column electrode. To the plasma display panel, gray scale addressing using a subfield method is implemented in order to obtain halftone display brightness as corresponding to input video signals.

In gray scale addressing based on the subfield method, a plurality of subfields are provided. In each of the subfields to which the number of times (or periods) to do light emission is assigned, display addressing is implemented to one field of video signals. Further, in each of the subfields, an address stage and a sustain stage are in turn implemented. In the address stage, in accordance with input video signals, selective discharge is selectively generated between the row electrode and the column electrode in each of the display cells to form a predetermined amount of wall electric charge (or remove it). In the sustain stage, only a display cell where a predetermined amount of wall electric charge is formed is repeatedly discharged, and a light emission state in association with that discharge is maintained. Furthermore, at least at the starting subfield, prior to the address stage, an initializing stage is implemented. In the initializing stage, in all the display cells, reset discharge is generated between the paired row electrodes to implement the initializing stage which initializes the amount of wall electric charge remaining in all the display cells.

In the sustain stage, in the case where many display cells are set in the lighting state and a sustain pulse is applied to generate discharge in many cells almost at the same time, a large amount of current is carried momentarily, and distortion occurs in the voltage waveform of the sustain pulse. Consequently, in accordance with a slight shift in a time point to start discharge, the voltage value being applied in discharge is varied in each of the display cells, variation occurs in discharge intensity, and thus display quality might be deteriorated.

Moreover, in the plasma display panel, although luminous efficiency is improved by increasing the proportion of xenon gas contained in discharge gas, a sustain discharge voltage in the sustaining stage increases. As a result, the level of luminance increases, so that residual image effect might become large.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a plasma display device capable of improving a residual image caused by increase of a luminance level while preventing variation in discharge intensity in each display cell.

A plasma display device according to the present invention is a device for displaying an image on a plasma display panel in accordance with an input video signal, said plasma display panel having a plurality of row electrode pairs, and a plurality of column electrodes intersecting with said plurality of row electrode pairs, so as to form display cells at the intersections, respectively, and a display period for one field of the input video signal being configured of a plurality of subfields each formed of an address period and a sustain period for the image display, said plasma display device comprising: an addressing portion which selectively generates address discharge in each of said display cells in accordance with pixel data based on the video signal in the address period; and a sustaining portion which applies a sustain pulse between row electrodes forming each of said row electrode pairs in said sustain period; wherein said sustaining portion changes, in accordance with an average luminance level of the video signal, the length of a pause period between a sustain pulse application end point at which one sustain pulse is applied in the sustain period of each of the subfields and a sustain pulse application starting point at which the next sustain pulse is applied.

In the plasma display device of the present invention, the pause period between the sustain pulse application end point at which one sustain pulse is applied in the sustain period of each of the subfields and the sustain pulse application starting point at which the next sustain pulse is applied is changed in accordance with an average luminance level of the video signal. Accordingly, deterioration of a residual image caused by increase of a luminance level can be prevented while preventing variation in discharge intensity in each display cell.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating an outline configuration of a plasma display device according to the invention;

FIG. 2 is a front view schematically illustrating the internal configuration of PDP seen from the display surface side of the device shown in FIG. 1;

FIG. 3 is a diagram illustrating a cross section on line V3-V3 shown in FIG. 2;

FIG. 4 is a diagram illustrating a cross section on line W2-W2 shown in FIG. 2;

FIG. 5 is a diagram illustrating magnesium oxide monocrystals having a cubic polycrystal structure;

FIG. 6 is a diagram illustrating a magnesium oxide monocrystal having a cubic polycrystal structure;

FIG. 7 is a diagram illustrating a form when magnesium oxide monocrystal powder is attached to the surface of a dielectric layer and an increased dielectric layer to form a magnesium oxide layer;

FIG. 8 is a diagram illustrating an exemplary light emission addressing sequence adopted in the plasma display device;

FIG. 9 is a diagram illustrating light emission patterns of the plasma display device;

FIG. 10 is a diagram illustrating various drive pulses to be applied to PDP and application timing thereof in accordance with the light emission addressing sequence shown in FIG. 8;

FIG. 11 is a graph illustrating the relationship between the particle diameter of magnesium oxide monocrystal powder and the wavelength of CL light emission;

FIG. 12 is a graph illustrating the relationship between the particle diameter of magnesium oxide monocrystal powder and the intensity of CL light emission at 235 nm;

FIG. 13 is a diagram illustrating a discharge probability when no magnesium oxide layer is constructed in a display cell, a discharge probability when a magnesium oxide layer is constructed by traditional vapor deposition, and a discharge probability when a magnesium oxide layer of a polycrystal structure is constructed;

FIG. 14 is a diagram illustrating the correspondence between CL light emission intensity at a 235-nm peak and discharge delay time;

FIG. 15 is a circuit diagram illustrating a specific configuration of an X-row electrode drive circuit and a Y-row electrode drive circuit in the device shown in FIG. 1;

FIG. 16 is a diagram illustrating switching operations and voltage waveforms of each electrode in the drive circuit shown in FIG. 15;

FIG. 17A and FIG. 17B are waveform diagrams each showing a sustain pulse, discharge intensity, and discharge timing of before and after burn-in;

FIG. 18A and FIG. 18B are waveform diagrams each showing a sustain pulse, discharge intensity, and discharge timing in the case where a pause period is changed; and

FIG. 19 is a figure showing an example of setting the pause period for a light emission load of a PDP and an APL value.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, an embodiment according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram illustrating an outline configuration of a plasma display device according to the invention.

As shown in FIG. 1, the plasma display device is configured of a PDP 50 as a plasma display panel, an X-row electrode drive circuit 51, a Y-row electrode drive circuit 53, a column electrode drive circuit 55, a drive control circuit 56, and an average luminance level detection circuit 57.

In the PDP 50, column electrodes D₁ to D_m are extended and arranged in the longitudinal direction (vertical direction) of a two-dimensional display screen, and row electrodes X₁ to X_n and row electrodes Y₁ to Y_n are extended and arranged in the lateral direction (the horizontal direction) thereof. The row electrodes X₁ to X_n and row electrodes Y₁ to Y_n form row electrodes pairs (Y₁, X₁), (Y₂, X₂), (Y₃, X₃), . . . , (Y_n, X_n) which are paired with those adjacent to each other and which serve as the first display line to the nth display line in the PDP 50. In each intersection part of the display lines with the column electrodes D₁ to D_m (areas surrounded by dashed lies in FIG. 1), a display cell PC which serves as a pixel is formed. More specifically, in the PDP 50, the display cells PC_1,1 to PC_1,m belonging to the first display line, the display cells PC_2,1 to PC_2,m belonging to the second display line, and the display cells PC_n,1 to PC_n,m belonging to the nth display line are each arranged in a matrix.

Each of the column electrodes D₁ to D_m of the PDP 50 is connected to the column electrode drive circuit 55, each of the row electrodes X₁ to X_n is connected to the X-row electrode drive circuit 51, and each of the row electrodes Y₁ to Y_n is connected to the Y-row electrode drive circuit 53.

FIG. 2 is a front view schematically illustrating the internal configuration of the PDP 50 seen from the display surface side. FIG. 2 depicts each of the intersection parts of each of the column electrodes D₁ to D₃ with the first display line (Y₁, X₁) and the second display line (Y₂, X₂) in the PDP 50. FIG. 3 depicts a diagram illustrating a cross section of the PDP 50 at a line V3-V3 in FIG. 2, and FIG. 4 depicts a diagram illustrating a cross section of the PDP 50 at a line W2-W2 in FIG. 2.

As shown in FIG. 2, each of the row electrodes X is configured of a bus electrode Xb (main portion) extended in the horizontal direction in the two-dimensional display screen and a T-shaped transparent electrode Xa (projected portion) formed as contacted with the position corresponding to each of the display cells PC on the bus electrode Xb. Each of the row electrodes Y is configured of a bus electrode Yb extended in the horizontal direction of the two-dimensional display screen and a T-shaped transparent electrode Ya formed as contacted with the position corresponding to each of the display cells PC on the bus electrode Yb. The transparent electrodes Xa and Ya oppose each other via a discharge gap g1 which has a predetermined length. The transparent electrodes Xa and Ya are formed of a transparent conductive film such as ITO, and the bus electrodes Xb and Yb are formed of a metal film, for example. As shown in FIG. 3, for the row electrode X formed of the transparent electrode Xa and the bus electrode Xb, and for the row electrode Y formed of the transparent electrode Ya and the bus electrode Yb, the front sides thereof are formed on the rear side of a front transparent substrate 10 to be the display surface of the PDP 50. The transparent electrodes Xa and Ya in each row electrode pair (X, Y) are extended to the counterpart row electrode side to be paired, and each have a wide portion near the discharge gap g1, and a narrow portion connecting between the wide portion and the bus electrode. The flat tops of the wide portions of the transparent electrodes Xa and Ya are faced to each other through the discharge gap g1. Moreover, on the rear side of the front transparent substrate 10, a black or dark light absorbing layer (shade layer) 11 extended in the horizontal direction of the two-dimensional display screen is formed between a pair of the row electrode pair (X₁, Y₁) and the row electrode pair (X₂, Y₂) adjacent to this row electrode pair. Furthermore, on the rear side of the front transparent substrate 10, a dielectric layer 12 is formed so as to cover the row electrode pair (X, Y). On the rear side of the dielectric layer 12 (the surface opposite to the surface to which the row electrode pair is contacted), an increased dielectric layer 12A is formed at the portion corresponding to the area where a light absorbing layer 11 and the bus electrodes Xb and Yb adjacent to the light absorbing layer 11 are formed as shown in FIG. 3. On the surface of the dielectric layer 12 and the increased dielectric layer 12A, a magnesium oxide layer 13 including vapor phase magnesium oxide (MgO) monocrystal powder, described later, is formed.

On the other hand, on a rear substrate 14 disposed in parallel with the front transparent substrate 10, each of the column electrodes D is formed as extended in the direction orthogonal to the row electrode pair (X, Y) at the position facing the transparent electrodes Xa and Ya in each row electrode pair (X, Y). On the rear substrate 14, a white column electrode protective layer 15 which covers the column electrode D is further formed. On the column electrode protective layer 15, partition 16 is formed. The partition 16 is formed in a ladder shape of a lateral wall 16A extended in the lateral direction of the two-dimensional display screen at the position corresponding to the bus electrodes Xb and Yb of each row electrode pair (X, Y), and of a vertical wall 16B extended in the longitudinal direction of the two-dimensional display screen at the middle between the column electrodes D adjacent to each other. In addition, the partition 16 in a ladder shape as shown in FIG. 2 are formed at every display line of the PDP 50, and a space SL exists between the partitions 16 adjacent to each other as shown in FIG. 2. Besides, the partitions 16 in a ladder shape partition the display cells PC including a discharge space S, and the transparent electrodes Xa and Ya, each of them is separated. In the discharge space S, discharge gas including xenon gas is filled. The discharge gas contains 10% by volume or more of xenon gas sealed within the discharge space S. On the side surface of the lateral wall 16A, the side surface of the vertical wall 16B, and the surface of the column electrode protective layer 15 in each of the display cells PC, a fluorescent material layer 17 is formed so as to cover the entire surfaces thereof as shown in FIG. 3. The fluorescent material layer 17 is actually formed of three types of fluorescent materials: a fluorescent material for red light emission, a fluorescent material for green light emission, and a fluorescent material for blue light emission. The discharge space S and the space SL in each of the display cells PC are closed to each other by abutting the magnesium oxide layer 13 against the lateral wall 16A as shown in FIG. 3. On the other hand, as shown in FIG. 4, since the vertical wall 16B is not abutted against the magnesium oxide layer 13, a space r1 exists therebetween. More specifically, the discharge spaces S of each of the display cells PC adjacent to each other in the lateral direction of the two-dimensional display screen communicate with each other through the space r1.

Here, magnesium oxide crystals forming the magnesium oxide layer 13 contain monocrystals obtained by vapor phase oxidation of magnesium steam that is generated by heating magnesium, such as vapor phase magnesium oxide crystals that are excited by irradiating electron beams to do CL light emission having a peak within a wavelength range of 200 to 300 nm (particularly, near 235 nm within 230 to 250 nm). The vapor phase magnesium oxide crystals contain a magnesium monocrystal having a particle diameter of 2000 angstrom or greater with a polycrystal structure in which cubic crystals are fit into each other in a SEM photo image as shown in FIG. 5, or with a cubic monocrystal structure in a SEM photo image as shown in FIG. 6. The magnesium monocrystal has features of higher purity, finer particles and less particle coagulation than magnesium oxides generated by other methods, which contributes to improved discharge properties in discharge delay, etc. In addition, in the embodiment, the vapor phase magnesium oxide monocrystals, which are used, have an average particle diameter of 500 angstrom or greater measured by the BET method, preferably 2000 angstrom or greater. Then, as shown in FIG. 7, the magnesium oxide monocrystals are attached to the surface of the dielectric layer 12 by spraying or electrostatic coating to form the magnesium oxide layer 13. Moreover, the magnesium oxide layer 13 may be formed in which a thin magnesium oxide layer is formed on the surface of the dielectric layer 12 and the increased dielectric layer 12A by vapor deposition or sputtering and vapor phase magnesium oxide monocrystals are attached thereon.

The drive control circuit 56 supplies various control signals that drive the PDP 50 having the structure in accordance with the light emission addressing sequence adopting a subfield method (subframe method) as shown in FIG. 8 to the X-row electrode drive circuit 51, the Y-row electrode drive circuit 53, and the column electrode drive circuit 55. The X-row electrode drive circuit 51, the Y-row electrode drive circuit 53, and the column electrode drive circuit 55 generate various drive pulses to be supplied to the PDP 50 in accordance with the light emission addressing sequence as shown in FIG. 8 and supply them to the PDP 50. The average luminance level detection circuit 57 detects an average luminance level (which corresponds to APL) of a video signal. The data of the detected average luminance level is supplied to the drive control circuit 56 and a pause period between sustain pulse application periods in a sustain period is adjusted in accordance with the average luminance level, as described hereinafter. The average luminance level may be detected for each frame of a video signal or individually for each line.

In the light emission addressing sequence shown in FIG. 8, a display period for one field (one frame) has subfields SF1 to SF12, and the address stage W and the sustain stage I are implemented in each of the subfields SF1 to SF12. Furthermore, only in the starting subfield SF1, a rest stage R is implemented prior to the address stage W. The period of the sustain stage I for the subfields SF1 to SF12 is prolonged in order of SF1 to SF12. Moreover, the period where the address stage W is implemented is an address period, and the period where the sustain stage I is implemented is a sustain period.

FIG. 9 depicts a diagram illustrating all the patterns of light emission addressing implemented based on the light emission addressing sequence as shown in FIG. 8. 13 gray scales are formed by the light emission addressing sequence of the subfields SF1 to SF12. As shown in FIG. 9, in the address stage W in one subfield in the subfields SF1 to SF12, selective erasure discharge is implemented for each of the display cells for each of the gray scales (depicted by a black circle). More specifically, wall electric charge formed in all the display cells of the PDP 50 by implementing the reset stage R remains until selective erasure discharge is implemented, and prompts discharge and light emission in the sustain stage I in each subfield SF that is included during that remaining period (depicted by a white circle). Each of the display cells becomes a light emission state while selective erasure discharge is being done for one field period, and 13 gray scales can be obtained by the length of the light emission state.

FIG. 10 depicts a diagram illustrating the application timing of various drive pulses to be applied to the column electrodes D, and the row electrodes X and Y of the PDP 50, extracting SF1 and SF2 from the subfields SF1 to SF12.

In the reset stage R implemented prior to the address stage W only in the starting subfield SF1, the X-row electrode drive circuit 51 simultaneously applies a negative reset pulse RP_X to the row electrodes X₁ to Y_n as shown in FIG. 10. The reset pulse RP_X has a pulse waveform that the voltage value is slowly increased to reach a peak voltage value over time. Furthermore, at the same time when the application of the reset pulse RP_X, the Y-row electrode drive circuit 53 simultaneously applies to the row electrodes Y₁ to Y_n a positive reset pulse RP_Y having a waveform that the voltage value is slowly increased to reach a peak voltage value over time as similar to the reset pulse RP_X as shown in FIG. 10. By the simultaneous application of the reset pulse RP_X and the reset pulse RP_Y, reset discharge is generated between the row electrodes X and Y in each of all the display cells PC_1,1 to PC_n,m. After the reset discharge is terminated, a predetermined amount of wall electric charge is formed on the surface of the magnesium oxide layer 13 in the discharge space S in each of the display cells PC. More specifically, it is the state that a so-called wall electric charge is formed in which positive electric charge is formed near the row electrode X and negative electric charge is formed near the row electrode Y on the surface of the magnesium oxide layer 13.

In a panel on which the vapor phase magnesium oxide layer 13 is provided as a protective layer, since discharge probability is significantly high, weak reset discharge is stably generated. By combining a bump, particularly a T-shaped electrode in a broad tip end, reset discharge is localized near the discharge gap, and thus a possibility to generate sudden reset discharge such as discharge being generated in all the row electrodes is further suppressed. Therefore, discharge is hardly generated between the column electrode and the row electrode, and stable, weak reset discharge can be generated for a short time.

Furthermore, in the configuration that the vapor phase magnesium oxide layer 13 is provided, since the discharge probability is significantly improved, the application of a single reset pulse, that is, even a one-time reset discharge allows priming effect to be continued. Thus, the reset operation and the selective erasure operation can be further stabilized. Moreover, the number of times to do reset discharge is minimized to enhance contrast.

In addition, the effect of provision of the vapor phase magnesium oxide layer 13 will be described later.

Next, in the address stage W in each of the subfields SF1 to SF12, the Y-row electrode drive circuit 53 applies positive voltages to all the row electrodes Y₁ to Y_n, and sequentially applies a scanning pulse SP having a negative voltage to each of the row electrodes Y₁ to Y_n. While this is being done, the X-electrode drive circuit 51 changes the potentials of the electrodes X₁ to X_n, to 0 V. The column electrode drive circuit 55 converts each data bit in a pixel drive data bit group DB1 corresponding to the subfield SF1 to a pixel data pulse DP having a pulse voltage corresponding to its logic level. For example, the column electrode drive circuit 55 converts the pixel drive data bit of a logic level of 0 to the pixel data pulse DP of a positive high voltage, while converts the pixel drive data bit of a logic level of 1 to the pixel data pulse DP of a low voltage (0 volt). Then, it applies the pixel data pulse DP to the column electrodes D₁ to D_m for each display line in synchronization with the application timing of a scanning pulse SP. More specifically, the column electrode drive circuit 55 first applies the pixel data pulse group DP1 formed of m pulses of the pixel data pulses DP corresponding to the first display line to the column electrodes D₁ to D_m, and then applies the pixel data pulse group DP2 formed of m pulses of the pixel data pulses DP corresponding to the second display line to the column electrodes D₁ to D_m. Between the column electrode D and the row electrode Y in the display cell PC to which the scanning pulse SP of the negative voltage and the pixel data pulse DP of the high voltage have been simultaneously applied, selective erasure discharge is generated to eliminate wall electric charge formed in the display cell PC. On the other hand, in the display cell PC to which the scanning pulse SP has been applied as well as the pixel data pulse DP of the low voltage (0 Volt), the selective erasure discharge as above is not generated. Therefore, the state to form wall electric charge is maintained in the display cell PC. More specifically, wall electric charge remains as it is when it exists in the display cell PC, whereas the state not to form wall electric charge is maintained when wall electric charge does not exist.

In this manner, in the address stage W based on the selective erasure addressing method, selective erasure addressing discharge is selectively generated in each of the display cells PC in accordance with each data bit in the pixel drive data bit group corresponding to the subfield, and then wall electric charge is removed. Thus, the display cell PC in which wall electric charge remains is set in the lighting state, and the display cell PC in which wall electric charge is removed is set in the unlighted state.

Subsequently, in the sustain stage I in each of the subfields, the X-row electrode drive circuit 51 and the Y-row electrode drive circuit 53 alternately, repeatedly apply positive sustain pulses IP_X and IP_Y to the row electrodes X₁ to X_n, and Y₁ to Y_n. The number of times to apply the sustain pulses IP_X and IP_Y depends on weighting brightness in each of the subfields. At each time that the sustain pulses IP_X and IP_Y are applied, only the display cells PC in the lighting state do sustain discharge, the cells in which a predetermined amount of wall electric charge is formed, and the fluorescent material layer 17 emits light in association with this discharge to form an image on the panel surface.

As described above, the vapor phase magnesium monocrystals contained in the magnesium oxide layer 13 formed in each of the display cells PC are excited by irradiating electron beams to do CL light emission having a peak within a wavelength range of 200 to 300 nm (particularly, near 235 nm within 230 to 250 nm) as shown in FIG. 11. As shown in FIG. 12, the greater the particle diameter of each of the vapor phase magnesium oxide crystals is, the greater the peak intensity of CL light emission is. More specifically, when magnesium is heated at temperature higher than usual in generating the vapor phase magnesium oxide crystals, vapor phase magnesium oxide monocrystals having the average particle diameter of 500 angstrom are formed as well as relatively large monocrystals having the particle diameter of 2000 angstrom or greater as shown in FIG. 5 or FIG. 6. Since temperature to heat magnesium is higher than usual, the length of flame generated by reacting magnesium with oxygen also becomes longer. Thus, the difference between a temperature of the flame and an ambient temperature becomes great, and therefore a group of vapor phase magnesium oxide monocrystals having a greater particle diameter particularly contain many monocrystals of high energy level corresponding to 200 to 300 nm (particularly near 235 nm).

FIG. 13 is a diagram illustrating discharge probabilities: the discharge probability when no magnesium oxide layer was provided in the display cell PC; the discharge probability when the magnesium oxide layer is constructed by traditional vapor deposition; and the discharge probability when the magnesium oxide layer was provided which contained vapor phase magnesium oxide monocrystals to generate CL light emission having a peak at 200 to 300 nm (particularly near 235 nm within 230 to 250 nm) by irradiating electron beams. In addition, in FIG. 13, the horizontal axis is dwell time of discharge, that is, a time interval from discharge being generated to next discharge being generated.

In this manner, when the magnesium oxide layer 13 is formed which contains the vapor phase magnesium oxide monocrystals that do CL light emission having a peak at 200 to 300 nm (particularly near 235 nm within 230 to 250 nm) by irradiating electron beams as shown in FIG. 5 or FIG. 6 in the discharge space S in each of the display cells PC, the discharge probability is higher than the case where the magnesium oxide layer is formed by traditional vapor deposition. In addition, as shown in FIG. 14, for the vapor phase magnesium oxide monocrystals described above, those of greater CL light emission intensity having a peak particularly at 235 nm in irradiating electron beams can shorten discharge delay generated in the discharge space S.

Therefore, even though voltage transition of the reset pulse to be applied to the row electrode is made smooth to weaken reset discharge as shown in FIG. 10 in order to suppress light emission in association with reset discharge that relates to no display image and to improve contrast, this weak reset discharge can be stabilized for a short time to be generated. Particularly, since each of the display cells PC adopts the structure in which local discharge is generated near the discharge gap between the T-shaped transparent electrodes Xa and Ya, a strong, sudden reset discharge that might be discharged in all the row electrodes can be suppressed as well as error discharge between the column electrode and the row electrode can be suppressed.

Furthermore, since the increased discharge probability (shortened discharge delay) allows a long, continuous priming effect by reset discharge in the reset stage R, address discharge generated in the address stage W and sustain discharge generated in the sustain stage I are high speed. Therefore, the pulse widths of the pixel data pulse DP and the scanning pulse SP to be applied to the column electrode D and the row electrode Y in order to generate address discharge as shown in FIG. 10 can be shortened. By that amount, processing time for the address stage W can be shortened. Moreover, the pulse width of the sustain pulse IP_Y to be applied to the row electrode Y in order to generate sustain discharge as shown in FIG. 10 can be shortened. By that amount, processing time for the sustain stage I can be shortened.

Accordingly, by the amount of the shortened processing time for each of the address stage W and the sustain stage I, the number of subfields to be provided in one field (or one frame) display period can be increased, and the number of gray scales can be intended to increase.

FIG. 15 depicts a specific configuration of the X-row electrode drive circuit 51 and the Y-row electrode drive circuit 53 on electrodes X_j and Y_j. The electrode X_j is the electrode at the jth line in electrodes X₁ to X_n, and the electrode Y_j, is the electrode at the jth line in the electrodes Y₁ to Y_n. The portion between the electrodes X_j and Y_j serves as a capacitor CO.

In the X-row drive circuit 51, two power sources B1 and B2 are provided. The power source B1 outputs a voltage V_s (for example, 170 V), and the power source B2 outputs a voltage V_r (for example, 190 V). A positive terminal of the power source B1 is connected to a connection line 21 for the electrode X_j through a switching element S3, and a negative terminal thereof is grounded. Between the connection line 21 and the ground, a switching element S4 is connected, as well as a series circuit formed of a switching element S1, a diode D1 and a coil L1, and a series circuit formed of a coil L2, a diode D2 and a switching element S2 are connected to the ground side commonly through a capacitor C1. In addition, the diode D1 has an anode on the capacitor C1 side, and the diode D2 is connected as the capacitor C1 side is a cathode. Furthermore, a negative terminal of the power source B2 is connected to the connection line 21 through a switching element S8 and a resistor R1, and a positive terminal of the power source B2 is grounded.

In the Y-row electrode drive circuit 53, four power sources B3 to B6 are provided. The power source B3 outputs a voltage V_s, (for example, 170 V), the power source B4 outputs a voltage V_r (for example, 190 V), the power source B5 outputs a voltage V_off (for example, 140 V), and the power source B6 outputs a voltage v_h (for example, 160 V, v_h>V_off). A positive terminal of the power source B3 is connected to a connection line 22 for a switching element S15 through a switching element S13, and a negative terminal thereof is grounded. Between the connection line 22 and the ground, a switching element S14 is connected as well as a series circuit formed of a switching element S11, a diode D3 and a coil L3, and a series circuit formed of a coil L4, a diode D4 and a switching element S12 are connected to the ground side commonly through a capacitor C2. In addition, the diode D3 has an anode on the capacitor C2 side, and the diode D4 is connected as the capacitor C2 side is a cathode.

The connection line 22 is connected to a connection line 23 for a negative terminal of the power source B6 through the switching element S15. A negative terminal of the power source B4 and a positive terminal of the power source B5 are grounded. A positive terminal of the power source B4 is connected to the connection line 23 through a switching element S16 and a resistor R2, and a negative terminal of the power source B5 is connected to the connection line 23 through a switching element S17.

A positive terminal of the power source B6 is connected to a connection line 24 for the electrode Y_j through a switching element S21, and the negative terminal of the power source B6 connected to the connection line 23 is connected to the connection line 24 through a switching element S22. The diode D5 is connected in parallel to the switching element S21, and the diode D6 is connected in parallel to the switching element S22. The diode D5 has an anode on the connection line 24 side, and the diode D6 is connected as the connection line 24 side is a cathode.

The drive control circuit 56 controls turning on and off the switching elements S1 to S4, S8, S11 to S17, S21 and S22.

In the X-row electrode drive circuit 51, the resistor R1, the switching elements S8 and the power source B2 configure a resetting portion, and the remaining elements configure a sustaining portion. In addition, in the Y-row electrode drive circuit 53, the power source B3, the switching elements S11 to S15, the coils L3 and L4, the diodes D3 and D4, and the capacitor C2 configure a sustaining portion, the power source B4, the resistor R2, and the switching element S16 configure a resetting portion, and the remaining power sources B5 and B6, the switching elements S13, S17, S21, S22, and the diodes D5 and D6 configure an addressing portion.

Next, the operations of the X-row electrode drive circuit 51 and the Y-row electrode drive circuit 53 in this configuration will be described with reference to a time chart shown in FIG. 16.

First, in the reset stage, the switching element S8 of the X-row electrode drive circuit 51 is turned on, and the switching elements S16 and S22 of the Y-row electrode drive circuit 53 are both turned on. The other switching elements are off. Turning on the switching elements S16 and S22 carries current from the positive terminal of the power source B4 to the electrode Y_j through the switching element S16, the resistor R2 and the switching element S22, and turning on the switching element S8 carries current from the electrode X_j through the resistor R1, and the switching element S8 to the negative terminal of the power source B2. The potential of the electrode X_j is gradually decreased by the time constant of the capacitor CO and the resistor R1, and is the reset pulse RP_X, whereas the potential of the electrode Y_j is gradually increased by the time constant of the capacitor CO and the resistor R2, and is the reset pulse PR_Y. The reset pulse RP_X finally becomes a voltage −V_r, and the reset pulse PR_Y finally becomes a voltage V_r. The reset pulse RP_X is applied to all the electrodes X₁ to X_n at the same time, and the reset pulse PR_Y is generated for each of the electrodes Y₁ to Y_n and is applied to all the electrodes Y₁ to Y_n.

The simultaneous application of the reset pulses RP_X and RP_Y, all the display cells of the PDP 1 are discharge excited to generate charged particles, and after terminating the discharge, a predetermined amount of wall electric charge is evenly formed on the dielectric layer of all the display cells.

After the levels of the reset pulses RP_X and RP_Y are saturated, the switching elements S8 and S16 are turned off before the reset stage is ended. Furthermore, the switching elements S4, S14 and S15 are turned on at this time, and the electrodes X_j and Y_j are both grounded. Thus, the reset pulses RP_X and RP_Y disappear.

Subsequently, when the address stage is started, the switching elements S14, S15 and S22 are turned off, the switching element S17 is turned on, and the switching element S21 is turned on at the same time. Thus, since the power source B6 is serially connected to the power source B5, the potential of the positive terminal of the power source B6 is V_h−V_off. The positive potential is applied to the electrode Y_j through the switching element S21.

In the address stage, the column electrode drive circuit 55 converts pixel data for each pixel based on the video signal to the pixel data pulses DP₁ to DP_n having a voltage value corresponding to its logic level, and sequentially applies them to the column electrodes D₁ to D_m for each one display line. As shown in FIG. 16, the pixel data pulses DP_j, DP_j+1 with respect to the electrodes Y_j, Y_j+1 are applied to the column electrode D_i.

The Y-row electrode drive circuit 53 sequentially applies the scanning pulse SP of the negative voltage to the row electrodes Y₁ to Y_n in synchronization with the timing of each of the pixel data pulse groups DP₁ to DP_n.

In synchronization with the application of the pixel data pulse DP_j from the column electrode drive circuit 55, the switching element S21 is turned off, and the switching element S22 is tuned on. Thus, the negative potential −V_off of the negative terminal of the power source B5 is applied to the electrode Y_j as the scanning pulse SP through the switching element S17 and the switching element S22. Then, in synchronization with the stop of the application of the pixel data pulse DP_j from the column electrode drive circuit 55, the switching element S21 is turned on, the switching element S22 is turned off, and the potential V_h−V_off of the positive terminal of the power source B6 is applied to the electrode Y_j through the switching element S21. After that, as shown in FIG. 16, the scanning pulse SP is applied to the electrode Y_j+1 as similar to the electrode Y_j in synchronization with the application of the pixel data pulse DP_j+1 from the column electrode drive circuit 55.

In the display cells belonging to the row electrode to which the scanning pulse SP has been applied, discharge is generated in the display cell to which the pixel data pulse of the positive voltage has been further applied at the same time, and most of its wall electric charge are lost. On the other hand, since discharge is not generated in the display cell to which the scanning pulse SP has been applied but the pixel data pulse of the positive voltage has not been applied, the wall electric charge still remains. The display cell in which the wall electric charge remains is in the lighting state, and the display cell in which the wall electric charge has disappeared is in the unlighted state.

In switching from the address stage to the sustain stage, the switching elements S17 and S21 are turned off, and the switching elements S14, S15 and S22 are instead turned on. The ON-state of the switching element S4 continues.

In the sustain stage, in the X-row electrode drive circuit 51, turning on the switching element S4 turns the potential of the electrode X_j to nearly 0 V of the ground potential (first potential). Subsequently, when the switching element S4 is turned off and the switching element S1 is turned on, current reaches the electrode X_j through the coil L1, the diode D1, and the switching element S1 by electric charge charged in the capacitor C1 to flow into the capacitor CO, and then the capacitor CO is charged. At this time, the time constant of the coil L1 and the capacitor CO gradually increases the potential of the electrode Xas shown in FIG. 16, thus effecting a resonant transition.

Then, the switching element S3 is turned on. Thus, the potential V_s (second potential) of the positive terminal of the power source B1 is applied to the electrode X_j, and the potential of the electrode X_j is clamped to V_s.

After that, the switching elements S1 and S3 are turned off, the switching element S2 is turned on, and current is carried from the electrode X_j into the capacitor C1 through the coil L2, the diode D2, and the switching element S2 by electric charge charged in the capacitor CO. At this time, the time constant of the coil L2 and the capacitor C1 gradually decreases the potential of the electrode X_j as shown in FIG. 16, thus effecting a resonant transition. When the potential of the electrode X_j reaches nearly 0V, the switching element S2 is turned off, and the switching element S4 is turned on.

In the X-row electrode drive circuit 51, the period from the time when the switching element S1 is turned on to right before the switching element S3 is turned on is a period for the first step. The ON-period of the switching element S3 is a period for the second step. The ON-period for the switching element S2 is a period for the third step. The ON-period for the switching element S4 is a period for the fourth step.

By this operation, the X-row electrode drive circuit 51 applies the sustain pulse IP_X of the positive voltage to the electrode X_j as shown in FIG. 16.

In the Y-row electrode drive circuit 53, at the same time when turning on the switching element S4 where the sustain pulse IP_X goes out, the switching element S11 is turned on, and the switching element S14 is turned off. The potential of the electrode Y_j is the ground potential of nearly 0 V when the switching element S14 is on. However, when the switching element S14 is turned off and the switching element S11 is turned on, current reaches the electrode Y_j through the coil L3, the diode D3, the switching element S11, the switching element S15, and the diode D6 by electric charge charged in the capacitor C2 to flow into the capacitor CO, and then the capacitor CO is charged. At this time, the time constant of the coil L3 and the capacitor CO gradually increases the potential of the electrode Y_j as shown in FIG. 16.

Subsequently, the switching element S13 is turned on. Thus, the potential V_s of the positive terminal of the power source B3 is applied to the electrode Y_j through the switching element S13, the switching element S15, and the diode D6.

After that, the switching elements S11 and S13 are turned off, the switching element S12 is turned on, the switching element S22 is turned on, and current flows from the electrode Y_j into the capacitor C2 through the switching element S22, the switching element S15, the coil L4, the diode D4, and the switching element S12 by electric charge charged in the capacitor CO. At this time, the time constant of the coil L4 and the capacitor C2 gradually decreases the potential of the electrode Y_j as shown in FIG. 16. When the potential of the electrode Y_j reaches nearly 0 V, the switching elements S12 and S22 are turned off, and the switching element S14 is turned on.

Also in the Y-row electrode drive circuit 53, it is a period for the first step from the time when turning on the switching element S11 to right before turning on the switching element S13. The ON-period of the switching element S13 is a period for the second step. The ON-period of the switching element S12 is a period for the third step. The ON-period of the switching element S14 is a period for the fourth step.

By this operation, the Y-row electrode drive circuit 53 applies the sustain pulse IP_Y of the positive voltage to the electrode Y_j as shown in FIG. 16.

In this manner, in the sustain stage, since the sustain pulse IP_X and the sustain pulse IP_Y are alternately generated and alternately applied to the electrodes X₁ to X_n and the electrodes Y₁ to Y_n, the display cell in which the wall electric charge still remains repeats discharge light emission to maintain its lighting state.

In the sustain stage, a pause period during which the sustain pulse is not applied is provided between the application period of the sustain pulse IP_X and the application period of the sustain pulse IP_Y. The pause period is changed in accordance with the APL (average picture level, or average luminance level) value by the drive control circuit 56. Accordingly, not only a residual image by high luminance is improved but also variation in luminance can be improved.

Here, the luminance variation and the residual image by high luminance are explained. After displaying a fixed pattern such as a static image on the PDP 50 for a while, when switching from the fixed pattern to other display pattern to display the other display pattern, a complementary color of a burn-in color of the area where the fixed pattern has been displayed become deep, and then the area remain as a residual image. Especially in the case of white burn-in, the luminance of the edge of the abovementioned area becomes high and stands out. When the PDP has no burn-in, there is a relationship between a sustain pulse, and a time point and intensity of a discharge obtained by application of the sustain pulse, as shown in FIG. 17A. When a small number of cells emit light as compared with the case where a large number of cells emit light, the discharge timing is deviated, causing variation in luminance. In a cell after that burn-in has occurred, as shown in FIG. 17B, the discharge timing comes earlier by a time t as compared with other cells in which burn-in does not occur, thus a discharge is performed at a high applied voltage in the cell of the burn-in without receiving an influence of voltage drop caused by discharges of the other cells of no burn-in, and whereby the discharge intensity increases. Therefore, the larger the voltage drop which is determined by a light emission load of the panel after the burn-in is, the worse the display quality of the residual image becomes. Furthermore, the degree at which the discharge is performed early is significantly related to the number of times the light emission is performed at the time of burn-in.

Therefore, in a cell in which burn-in has occurred, the greater the APL value is, the longer the pause period is. FIG. 18A shows discharge timing and discharge intensity in the case where a pause period A between sustain pulses is short. In this case, as described in FIG. 17B, a temporal difference B of the discharge timing becomes large between a cell in which burn-in is performed and other cells in each of which no burn-in is performed, and thus the discharge timing comes early. Therefore, a discharge is performed at a high applied voltage in the cell of the burn-in without receiving an influence of voltage drop caused by discharges of the abovementioned other cells of no burn-in, and whereby the discharge intensity increases. On the other hand, FIG. 18B shows discharge timing and discharge intensity in the case where a pause period A between sustain pulses is long. In this case, a temporal difference B of the discharge timing is large between a cell in which burn-in is performed and other cells in each of which no burn-in is performed, that is, the degree at which a discharge is performed early is decreased, thus the discharge is performed at a low applied voltage, compared to the case shown in FIG. 18A, and the discharge intensity becomes low. Therefore, a residual image occurred by a high luminance level can be improved. However, when the length of the pause period is extended, the luminance variation may become worse depending on the state of the light emission load, thus the pause period is changed in accordance with the APL value.

The drive control circuit 56 changes a pause period between application periods of the sustain pulses IP_X and IP_Y in the sustain stage of each subfield, in accordance with the light emission load of each frame, that is, in accordance with the APL value. As the APL value is greater, possibility that a residual image based on a luminance level occurs is higher, thus the length of the pause period is increased. The light emission load of the PDP 50 is the minimum when the whole black is displayed and the maximum when the whole white is displayed, thus, as shown in FIG. 19, the pause period is set to a [ns] with respect to an APL value of 0% at the time of the whole black display, and the pause period is set to a+b [ns] with respect to an APL value of 100% at the time of the whole white display. Specifically, the pause period is set to APL value×(a+b) [ns]. The value of a is, for example, 10 and the value of b is, for example, 20.

It should be noted that the pause period may be set so that the APL value is a predetermined value or more or lower. Specifically, when the APL value is the predetermined value or more, the pause period may be set longer than the case where the APL value is lower than the predetermined value.

By changing the pause period in accordance with the APL value as described above, an residual image occurred by a high luminance level can be reduced and the luminance variation can be improved.

In the aforementioned embodiment, although the plasma display panel using specific vapor phase magnesium is applied to the display device, the present invention is not limited thereto. The invention is also applicable to a plasma display panel with reduced discharge delay and reduced discharge variations, also providing the same effects.

In addition, for the PDP 50 in the embodiments, the structure is adopted in which the display cell PC is formed between the row electrodes X and the row electrodes Y that are paired with each other as (X₁, Y₁), (X₂, Y₂), (X₃, Y₃), . . . , (Y_n, Y_n). However, the structure may be adopted in which the display cell PC is formed between all the row electrodes. More specifically, the structure may be adopted in which the display cell PC is formed between the row electrodes X₁ and Y₁, the row electrode Y₁ and X₂, the row electrode X₂ and Y₂, . . . , the row electrode Y_n−1 and Y_n, the row electrode X_n and Y_n.

Furthermore, for the PDP 50 in the embodiments, the structure is adopted in which the row electrodes X and Y are formed in the front transparent substrate 10 and the column electrode D and the fluorescent material layer 17 are formed in the rear substrate 14. However, the structure may be adopted in which the column electrodes D as well as the row electrodes X and Y are formed in the front transparent substrate 10 and the fluorescent material layer 17 is formed in the rear substrate 14.

As described above, according to the present invention, the length of the pause period between a sustain pulse application end point at which one sustain pulse is applied in the sustain period of each subfield and a sustain pulse application starting point at which the next sustain pulse is applied is changed in accordance with the average luminance level of a video signal. Therefore, deterioration of an residual image occurred by increase of a luminance level can be prevented, while preventing variation in discharge intensity in each display cell.

This application is based on Japanese Patent Application Ser. No. 2005-260453 which is hereby incorporated by reference.

Claims

1. A plasma display device for displaying an image on a plasma display panel in accordance with an input video signal, said plasma display panel having a plurality of row electrode pairs, and a plurality of column electrodes intersecting with said plurality of row electrode pairs, so as to form display cells at the intersections, respectively, and a display period for one field of the input video signal being configured of a plurality of subfields each formed of an address period and a sustain period for the image display, said plasma display device comprising: an addressing portion which selectively generates address discharge in each of said display cells in accordance with pixel data based on the video signal in the address period; and a sustaining portion which applies a sustain pulse between row electrodes forming each of said row electrode pairs in said sustain period; wherein said sustaining portion changes, in accordance with an average luminance level of the video signal, the length of a pause period between a sustain pulse application end point at which one sustain pulse is applied in the sustain period of each of the subfields and a sustain pulse application starting point at which the next sustain pulse is applied.

2. The plasma display device according to claim 1, wherein the sustaining portion has a first transition portion which resonantly transits a potential on one row electrodes of the row electrode pairs from a first potential to a second potential, a first clamping portion which clamps the potential on the one row electrodes to the second potential, a second transition portion which resonantly transits the potential on the one row electrodes from the second potential to the first potential, and a second clamping portion which clamps the potential on the one row electrodes at the first potential, and wherein the sustain pulse is caused by sequentially executing a first step for transiting from the first potential to the second potential, a second step for clamping to the second potential, a third step for transiting from the second potential to the first potential, and a fourth step for clamping to the first potential.

3. The plasma display device according to claim 1, wherein the length of the pause period is increased as the average luminance level of the video signal increases.

4. The plasma display device according to claim 1, wherein when the average luminance level of the video signal is not less than a predetermined value, the length of the pause period is made longer as compared with the case in which the average luminance level of the video signal is less than the predetermined value.

5. The plasma display device according to claim 1, comprising a magnesium oxide layer containing magnesium oxide monocrystals which are excited by irradiating an electron beam in each of said display cells to emit cathode luminescence light having a peak within a wavelength range of 200 to 300 nm.

6. The plasma display device according to claim 1, wherein each row electrode forming the row electrode pairs includes a main portion extending in a row direction, and a projected portion projected from the main portion in a column direction so as to oppose each other via a discharge gap.

7. The plasma display device according to claim 6, wherein the projected portion of the row electrode has a wide portion near the discharge gap, and a narrow portion connecting between the wide portion and the main portion.

8. The plasma display device according to claim 5, wherein said magnesium oxide layer contains the magnesium oxide monocrystals generated by vapor phase oxidation of magnesium steam that is generated by heating magnesium.

9. The plasma display device according to claim 5, wherein said magnesium oxide layer contains the magnesium oxide monocrystals having a particle diameter of 2000 angstrom or greater.

10. The plasma display device according to claim 5, wherein said magnesium oxide crystals emit cathode luminescence light having a peak within a wavelength range of 230 to 250 nm.

11. The plasma display device according to claim 1, wherein the plasma display panel has discharge gas containing 10% by volume or more of xenon gas sealed within a discharge space.