Plasma display device

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to plasma display devices.

[0003] 2. Description of Related Art

[0004] In recent years, as the size of display devices has increased, there has been a demand for a thinner display device, and consequently various thin display devices have become commercially available. The AC (alternating current discharge) type plasma display panel (hereinafter simply as “PDP”), a thin display device, has attracted much attention.

[0005] The PDP includes a matrix of discharge cells corresponding to pixels. The discharge cell is allowed to emit light by the discharge phenomenon. There are only two states for the cell, i.e., the “light emitting” state in the maximum luminance and the “non-light emitting” state in the minimum luminance. Gradation driving is performed based on a subfield drive method in order to allow the discharge cell to display the intermediate level luminance corresponding to an input video signal.

[0006] In the gradation driving based on the subfield drive method, one field in a display period consists of a plurality of subfields, and each subfield is allocated with a light emission number (light emitting periods) corresponding to the weight of the subfield.

[0007]
FIG. 1 is a diagram showing a light emission driving format when one field in the display period is divided into four subfields, SF1 to SF4.

[0008] In FIG. 1, the subfields SF1 to SF4 are allocated the light emission numbers as follows:

[0009] SF1: 1

[0010] SF2: 2

[0011] SF3: 4

[0012] SF4: 8

[0013] Depending upon the luminance level of an input video signal, light is emitted in one or a combination of the subfields SF1 to SF4. If for example the luminance level of the input video signal is “4”, only the subfield SF3 among the subfields SF1 to SF4 is used for emitting light. At the time, light is emitted four times in the subfield SF3. Therefore, light emission is performed four times during the display period for one field, and the luminance corresponding to the luminance level “4” is observed. If the luminance level of the input video signal is “13”, light emission is performed in the subfields SF1, SF2 and SF4. At the time, light emission is performed once in the subfield SF1, twice in the subfield SF2, and eight times in the subfield SF4. Therefore, light emission is performed thirteen times altogether during the display period for one field, and the luminance corresponding to the luminance level “13” is observed.

[0014] In this case, in order to increase the luminance of the entire screen, the number of light emission (light emitting periods) allocated to each subfield may be increased. However, the display period for one field is limited, and therefore such a method will not improve the luminance as desired.

SUMMARY OF THE INVENTION

[0015] It is an object of the present invention to provide a plasma display device capable of high luminance display by gradation driving according to the subfield drive method.

[0016] A plasma display device, according to the present invention, performs gradation driving to a plasma display panel based on a video signal. The plasma display panel has discharge cells formed at the intersections of a plurality of row electrodes corresponding to display lines and a plurality of column electrodes arranged so that they intersect the row electrodes. The plasma display device includes a driving portion and a non-selected line detection portion. The driving portion performs pixel data writing scanning for scanning each of the discharge cells on each display line according to pixel data corresponding to the video signal, and causes selective discharge. As a result this sets each of the discharge cells to one of a light emitting state and a non-light emitting state in each of a plurality of subfields constituting a display period for one field in the video signal. The driving portion also performs light emission sustaining driving for causing sustaining discharge. As a result this allows only the discharge cells in the light emitting state to emit light as many times as the number of light emissions allocated corresponding to the weight of each subfield. The non-selected line detection portion detects a non-selected line to be a display line on which all the discharge cells are not subjected to the selective discharge based on the pixel data. The driving portion performs the pixel data writing scanning only to each of the display lines excluding the non-selected line.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017]
FIG. 1 is a light emission driving format based on a subfield drive method;

[0018]
FIG. 2 is a diagram of the general configuration of a plasma display device according to the present invention;

[0019]
FIG. 3 is a diagram showing the internal structure of a non-selected line detection circuit 5;

[0020]
FIG. 4 is a diagram of the structure of a display line status register 51;

[0021]
FIGS. 5A to 5C are a light emission driving format used in the plasma display device shown in FIG. 2;

[0022]
FIG. 6 is a timing chart showing various driving pulses applied to the PDP 10 according to the light emission driving format shown in FIG. 5A, and the application timings of the pulses;

[0023]
FIG. 7 is a table of light emission patterns for pixel data PD;

[0024]
FIG. 8 is a timing chart showing various driving pulses applied to the PDP 10 according to the light emission driving format shown in FIG. 5B, and the application timings of the pulses (by selective erasure addressing); and

[0025]
FIG. 9 is a timing chart showing various driving pulses applied to the PDP 10 according to the light emission driving format shown in FIG. 5B and the application timings of the pulses (by selective writing addressing).

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] Embodiments of the present invention will be now described in conjunction with the accompanying drawings.

[0027]
FIG. 2 is a diagram of the general configuration of a plasma display device according to the present invention.

[0028] As shown in FIG. 2, the plasma display device includes a PDP (plasma display panel) 10, and various functional modules to drive the PDP. Note that according to the embodiment as will be described, the display period for one field is divided into periods corresponding to four subfields SF1 to SF4 as shown in FIG. 1 based on the subfield drive method, and gradation driving is performed.

[0029] In FIG. 2, the PDP 10 includes m column electrodes D1 to Dm as address electrodes, n row electrodes X1 to Xn and n row electrodes Y1 to Yn. The row electrodes are arranged so that they intersect the column electrodes. One pair of row electrodes, X and Y, forms a row electrode corresponding to one display line in the PDP 10. The discharge spaces, with discharge gas enclosed, are provided between the column electrodes D, and the row electrodes X and Y. A discharge cell is formed at each intersection of the row electrode pairs and the column electrodes including the discharge spaces. More specifically, there are m discharge cells on one display line, and there are m×n discharge cells on one screen page region.

[0030] A synchronization detection circuit 1 detects a vertical synchronization signal in an input video signal and generates a vertical synchronization detection signal V. The signal is supplied to a driving control circuit 2, an average luminance level calculation circuit 3, a spare time operation circuit 4, and a non-selected line detection circuit 5. The synchronization detection circuit 1 also detects a horizontal synchronization signal in the input video signal and generates a horizontal synchronization detection signal H which is supplied to the driving control circuit 2 and the non-selected line detection circuit 5. An A/D converter 6 samples and converts the input video signal into 4-bit pixel data PD on a pixel basis for example, and supplies the data to the average luminance level calculation circuit 3, the non-selected line detection circuit 5 and a memory 7. The average luminance level calculation circuit 3 calculates the average luminance level of the input video signal for each field based on the pixel data PD supplied from the A/D converter 6, and supplies the resultant average luminance level to a light emission number setting circuit 8.

[0031] The non-selected line detection circuit 5 detects, for each subfield, a display line on which all the discharge cells are not subjected to selective discharge which will be described based on the pixel data PD. In other words the circuit detects a non-selected line. The non-selected line detection circuit 5 supplies the result of detection as non-selected line information NLI1 to NLI4 for subfields SF1 to SF4 respectively, to the driving control circuit 2 and the spare time operation circuit 4.

[0032]
FIG. 3 is a diagram of the internal structure of the non-selected line detection circuit 5.

[0033] In FIG. 3, an SF1 non-selected line detection circuit 501 sequentially takes only the first bit data in the 4-bit pixel data PD (hereinafter referred to as “pixel data bit DB1”). The SF1 non-selected line detection circuit 501 determines whether or not all the m pixel data bits DB1 corresponding to each display line have a value representing a “non-selected” state such as a logical level “0”. Note that the “non-selected” state refers to the state in which selective erasure discharge is not caused in the case of selective erasure addressing, whereas the term refers to the state in which selective writing discharge is not caused in the case of selective writing addressing. Then, the SF1 non-selected line detection circuit 501 supplies a non-selected line detection signal NL1 in a logical level “1” to a display line status register 511 if all the m pixel data bits DB1 have a value representing the “non-selected” state. The signal in this logical level indicates that the display line is a non-selected line in the subfield SF1. Meanwhile, the SF1 non-selected line detection circuit 501 supplies the non-selected line detection signal NL1 in a logical level “0” to the display line status register 511 if all the pixel data bits DB1 do not have a value representing the “non-selected” state.

[0034] More specifically, the SF1 non-selected line detection circuit 501 sequentially obtains the non-selected line detection signal NL1 corresponding to each of the first to nth display lines for each horizontal synchronization detection signal H, and supplies the signal to the display line status register 511.

[0035] As shown in FIG. 4, the display line status register 511 includes status registers SR1 to SRn corresponding to the first to nth display lines respectively, in the PDP 10. The display line status register 511 sequentially writes the value of the non-selected line detection signal NL1 supplied from the SF1 non-selected line detection circuit 501 to a status register SR corresponding to the display line. The display line status register 511 reads out the values written in the status registers SR1 to SRn in response to the vertical synchronization detection signal V. It then supplies the values to the driving control circuit 2 and the spare time operation circuit 4 as the non-selected line information NLI1, indicating a non-selected line in the subfield SF1.

[0036] An SF2 non-selected line detection circuit 502 sequentially takes only the second bit data in the 4-bit pixel data PD (hereinafter referred to as “pixel data bit DB2”). The SF2 non-selected line detection circuit 502 determines whether or not all the m pixel data bits DB2 corresponding to each display line have a value representing the “non-selected” state such as a logical level “0”. Then, if all the m pixel data bits DB2 have a value representing the “non-selected” state, the SF2 non-selected line detection circuit 502 supplies a non-selected line detection signal NL2 in a logical level “1” to a display line status register 512 The signal in the logical level indicates that the display line is a non-selected line in the subfield SF2. Meanwhile, the SF2 non-selected line detection circuit 502 supplies the non-selected line detection signal NL2 in a logical level “0” to the display line status register 512 if all the pixel data bits DB2 do not have such a value representing the “non-selected” state.

[0037] More specifically, the SF2 non-selected line detection circuit 502 sequentially obtains the non-selected line detection signal NL2 corresponding to the first to nth display lines for each horizontal synchronization detection signal H, and supplies the obtained signal to the display line status register 512.

[0038] As shown in FIG. 4, the display line status register 512 includes status registers SR1 to SRn corresponding to the first to nth display lines respectively, in the PDP 10. The display line status register 512 sequentially writes the value of the non-selected line detection signal NL2 to a status register SR corresponding to the display line. The display line status register 512 reads the values written in the status registers SR1 to SRn in response to the vertical synchronization detection signal V, and supplies the values to the driving control circuit 2 and the spare time operation circuit 4 as non-selected line information NLI2 representing a non-selected line in the subfield SF2.

[0039] An SF3 non-selected line detection circuit 503 sequentially takes only the third bit data in the 4-bit pixel data PD (hereinafter referred to as “pixel data bit DB3”). The SF3 non-selected line detection circuit 503 determines whether or not all the m pixel data bits DB3 corresponding to each display line have a value representing the “non-selected” state such as a logical level “0”. Then, if all the m pixel data bits DB3 have a value representing the “non-selected” state, the SF3 non-selected line detection circuit 503 supplies a non-selected line detection signal NL3 in a logical level “1” to a display line status register 513. The signal in the logical state indicates that the display line is a non-selected line in the subfield SF3. Meanwhile, the SF3 non-selected line detection circuit 503 supplies a non-selected line detection signal NL3 in a logical level “0” to the display line status register 513 if all the pixel data bits DB3 do not have such a value representing the “non-selected” state.

[0040] More specifically, SF3 non-selected line detection circuit 503 sequentially obtains the non-selected line detection signal NL3 corresponding to the first to nth display lines for each horizontal synchronization detection signal H, and supplies the obtained signal to the display line status register 513.

[0041] As shown in FIG. 4, the display line status register 513 includes status registers SR1 to SRn corresponding to the first to nth display lines respectively, in the PDP 10. The display line status register 513 sequentially writes the value of the non-selected line detection signal NL3 to a status register SR corresponding to the display line. The display line status register 513 reads the values written in the status registers SR1 to SRn in response to the vertical synchronization detection signal V, and supplies the values to the driving control circuit 2 and the spare time operation circuit 4 as non-selected line information NLI3 representing a non-selected line in the subfield SF3.

[0042] An SF4 non-selected line detection circuit 504 sequentially takes only the fourth bit data in the 4-bit pixel data PD (hereinafter referred to as “pixel data bit DB4”). The SF4 non-selected line detection circuit 504 determines whether or not all the m pixel data bits DB4 corresponding to each display line have a value representing the “non-selected” state such as a logical level “0”. Then, if all the m pixel data bits DB4 have a value representing the “non-selected” state, the SF4 non-selected line detection circuit 504 supplies a non-selected line detection signal NL4 in a logical level “1” to a display line status register 514. The signal in this level indicates that the display line is a non-selected line in the subfield SF4. Meanwhile, the SF4 non-selected line detection circuit 504 supplies the non-selected line detection signal NL4 in a logical level “0” to the display line status register 514 if all the pixel data bits DB4 do not have such a value representing the “non-selected” state.

[0043] More specifically, the SF4 non-selected line detection circuit 504 sequentially obtains the non-selected line detection signal NL4 corresponding to the first to nth display lines for each horizontal synchronization detection signal H, and supplies the obtained signal to the display line status register 514.

[0044] As shown in FIG. 4, the display line status register 514 includes status registers SR1 to SRn corresponding to the first to nth display lines in the PDP 10. The display line status register 514 sequentially writes the value of the non-selected line detection signal NL4 to a status register SR corresponding to the display line. The display line status register 514 reads out the values written in the status registers SR1 to SRn in response to the vertical synchronization detection signal V. It then supplies the values to the driving control circuit 2 and the spare time operation circuit 4 as non-selected line information NLI4 representing a non-selected line in the subfield SF4.

[0045] The spare time operation circuit 4 obtains the total number of non-selected lines in each of the subfields SF1 to SF4 indicated by the non-selected line information NLI1 to NLI4 supplied from the non-selected line detection circuit 5, and supplies the total number to the light emission number setting circuit 8 as spare time TE.

[0046] The light emission number setting circuit 8 sets a luminance magnification K within the range satisfying the following relation:

K
·(a1+a2+a3+a4)−(a1+a2+a3+a4)=TE

[0047] where a1 to a4 are reference light emission numbers allocated to the subfields SF1 to SF4 respectively, and TE is spare time.

[0048] If for example an externally applied, luminance adjusting instruction directs a reduction in the luminance, the luminance magnification K is set to a value smaller than “1”. Meanwhile, if the luminance adjusting instruction directs an increase in the luminance, the luminance magnification K is set to a value larger than “1” within the range satisfying the above expression. The light emission number setting circuit 8 sets the luminance magnification K to a value larger than “1” within the range satisfying the above expression if an average luminance level supplied from the average luminance level calculation circuit 3 is smaller than a prescribed level. If the average luminance level is higher than the prescribed level, the luminance magnification K is set to a value smaller than “1”.

[0049] The light emission number setting circuit 8 multiplies each of the reference light emission numbers a1 to a4 by the luminance magnification K to produce the final light emission numbers A1 to A4, allocated to the subfields SF1 to SF4 as follows:

[0050] A1=K·a1 the number of light emission in SF1

[0051] A2=K·a2 the number of light emission in SF2

[0052] A3=K·a3 the number of light emission in SF3

[0053] A4=K·a4 the number of light emission in SF4

[0054] Then, these numbers and the luminance magnification K are supplied to the driving control circuit 2.

[0055] The memory 7 is sequentially written with the pixel data PD supplied from the A/D converter 6 in response to a writing signal supplied from the driving control circuit 2. When data for one screen page, in other words n×m pixel data pieces from pixel data PD11 corresponding to the pixel in the first row and the first column to PDnm corresponding to the pixel in the nth row and the mth column, has been written, the memory 7 performs the following reading operation.

[0056] The first bit data of the pixel data PD11 to PDnm is read out from the memory 7 as driving pixel data bits DB111 to DB1nm on a display line basis in response to a reading address supplied from the driving control circuit 2 and supplied to the address driver 60. Then, the second bit data of the pixel data PD11 to PDnm is read out from the memory 7 as driving pixel data bits DB211 to DB2nm on a display line basis in response to a reading address supplied from the driving control circuit 2. The read out data is supplied to the address driver 60. Then, the third bit data of the pixel data PD11 to PDnm is read out from the memory 7 as driving pixel data bits DB311 to DB3nm on a display line basis in response to a reading address supplied from the driving control circuit 2. The read out data is supplied to the address driver 60. Then, the fourth bit data of the pixel data PD11 to PDnm is read out from the memory 7 as driving pixel data bits DB411 to DB4nm on a display line basis in response to a reading address supplied from the driving control circuit 2. The read out data is supplied to the address driver 60.

[0057] Note, however, that during the period the driving control circuit 2 does not produce a reading address for a driving pixel data bit DB corresponding to a non-selected line indicated by the non-selected line information NLI1 to NLI4. More specifically, a driving pixel data bit DB corresponding to a non-selected line is not read out from the memory 7.

[0058] The driving control circuit 2 operates in a light emission driving format based on the luminance magnification K, the light emission numbers A1 to A4 supplied from the light emission number setting circuit 8, and the non-selected line information NLI1 to NLI4. According to the light emission driving format, various timing signals used for gradation driving of the PDP 10 are supplied to the address driver 60, and the first and second sustain drivers 70 and 80.

[0059] The driving control circuit 2, for example, operates in a light emission driving format, shown in FIG. 5A, when the non-selected line information NLI1 to NLI4 indicate the absence of a non-selected line in any of the subfields SF1 to SF4, and the luminance magnification K is “1”.

[0060] As shown in FIG. 5A, according to the light emission driving format, the simultaneous reset step Rc, the pixel data writing step Wc, the light emission sustaining step Ic and the erasure step E are executed in each subfield.

[0061]
FIG. 6 shows various driving pulses applied by the address driver 60 and the first and second sustain drivers 70 and 80 to the column electrodes and the row electrode pairs in the PDP 10 in the light emission driving format shown in FIG. 5A. Note that FIG. 6 shows only the timings in one subfield in FIG. 5A.

[0062] In the simultaneous reset step Rc, the first and second sustain drivers 70 and 80 at a certain time apply a reset pulse RPX of negative polarity and a reset pulse RPY of positive polarity respectively, to the row electrodes X and Y in the PDP 10. In response to the application of these reset pulses RPX and RPy; all the discharge cells in the PDP 10 are reset-discharged, and a prescribed quantity of wall charges are homogeneously formed in each discharge cell. Thus, all the discharge cells at once are initialized to the “light emitting” state to emit light.

[0063] Then in the pixel data writing step Wc, the address driver 60 produces a pixel data pulse having a voltage corresponding to the logical level of a driving pixel data bit DB read out from the memory 7. At the same time, all the driving pixel data bits DB belonging to the first to nth display lines are read out from the memory 7. As shown in FIG. 6, the address driver 60 applies the pixel data pulses to the column electrodes D1 to Dm as pixel data pulse groups DP1 to DPn. These are grouped on a display line basis sequentially from the pulse belonging to the first display line to the one belonging to the nth display line. Note that the address driver 60 produces a high voltage pixel data pulse when the logical level of the driving pixel data bit DB is “1”, and a low voltage (0V) pixel data pulse when the logical level is “0”.

[0064] In the pixel data writing step Wc, the driving control circuit 2 supplies the second sustain driver 80 with a timing signal used to apply a scanning pulse SP only to display lines other than non-selected lines. In this case, since there is no non-selected line in any of the subfields SF1 to SF4, the driving control circuit 2 supplies the second sustain driver 80 with the timing signal used to apply the scanning pulse SP to all the display lines. As a result, as shown in FIG. 6, the second sustain driver 80 sequentially applies the scanning pulse SP of negative polarity to the row electrodes Y1 to Yn the same timings as the application timings to all the pixel data pulse groups DP1 to DPn.

[0065] In the pixel data writing step Wc, only a discharge cell located at the intersection of a “row” provided with the scanning pulse SP and a “column” provided with a high voltage pixel data pulse is discharged (selective erasure discharge), so that wall charges formed in the discharge cell are removed. By the selective erasure discharge, a discharge cell which has been initialized to the “light emitting” state in the simultaneous reset step Rc attains a “non-light emitting” state which allows no light emission. Meanwhile, a discharge cell provided with a low voltage pixel data pulse is not subjected to the selective erasure discharge as described above, and the initialized state in the simultaneous reset step Rc. In other words, the “light emitting” state is maintained.

[0066] In the following light emission sustaining step Ic, as shown in FIG. 6, the first and second sustain drivers 70 and 80 alternately apply sustain pulses IPX and IPY of positive polarity to the row electrodes X1 to Xn and Y1 to Yn. In this case, in the light emission sustaining step Ic in each of the subfields SF1 to SF4, the number of sustain pulses applied by the first and second sustain drivers 70 and 80 is as follows. The light emission numbers A1 to A4 are supplied from the light emission number setting circuit 8.

[0067] A1: SF1

[0068] A2: SF2

[0069] A3: SF3

[0070] A4: SF4

[0071] By the light emission sustaining step Ic, a discharge cell with remaining wall charges, in other words a “light emitting” cell, is subjected to sustaining discharge each time the sustain pulses IPX and IPY are applied, and the light emitting state by the sustaining discharge is maintained for the above number of times (periods).

[0072] In the erasure step E at the end of each subfield, the second sustain driver 80 applies an erasure pulse EP, as shown in FIG. 6, to the row electrodes Y1 to Yn, so that all the discharge cells are simultaneously erasure-discharged. Thus, all the wall charges remaining in each of the discharge cells are removed.

[0073] The series of operations i.e., the simultaneous reset step Rc, the pixel data writing step Wc, the light emission sustaining step Ic and the erasure step E are similarly performed in each subfield.

[0074]
FIG. 7 is a table showing light emission patterns for the pixel data PD by the driving operation as described above.

[0075] In FIG. 7, when for example a video signal (corresponding to pixel data “1110”) having a luminance level corresponding to the ninth gradation is input, light is emitted only in the light emission sustaining step Ic in the subfield SF4 among the subfields SF1 to SF4. More specifically, in the pixel data writing step Wc in each of the subfields SF1 to SF3, selective erasure discharge is caused to remove wall charges in discharge cells. Meanwhile, in the pixel data writing step Wc in the subfield SF4, the selective erasure discharge is not caused, and therefore wall charges remain. As a result, only by the light emission sustaining step Ic in the subfield SF4, sustaining discharge with light emission is performed as many times (periods) as the number of application of the sustaining pulses IPX and IPY. In other words the sustaining discharge is performed “a4” times (periods). Thus, during the display period for one field, light is emitted “a4” times (periods), and the display in the luminance level corresponding to the ninth gradation is provided.

[0076] When a video signal in a luminance level corresponding to the sixth gradation (corresponding to pixel data “0101”) is input, light is emitted only in the light emission sustaining step Ic in each of the subfields SF1 and SF3 among the subfields SF1 to SF4. Therefore, sustaining discharge with light emission is caused “a1” times (periods) in the light emission sustaining step Ic in the subfield SF1, and “a3” times (periods) in the light emission sustaining step Ic in the subfield SF3. As a result, light is emitted “(a1+a3)” times (periods) during the display period for one field, so that the display in the luminance level corresponding to the sixth gradation is provided.

[0077] Meanwhile, the driving control circuit 2 operates in a light emission driving format, shown in FIG. 5B, if the non-selected line information NLI1 to NLI4 indicates the presence of a non-selected line in any of the subfields SF1 to SF4, and the luminance magnification K is “1”.

[0078] Note that FIG. 5B shows an example of a light emission format employed when the non-selected line in each subfield corresponds to the following:

[0079] SF1: the first display line to (h−1)th display line

[0080] SF2: the ith display line to (j−1)th display line

[0081] SF3: the jth display line to nth display line

[0082] SF4: all the display lines

[0083]
FIG. 8 is a chart showing the application timings of various driving pulses to the column electrodes and the row electrode pairs in the PDP 10 by the address driver 60, and the first and second sustain drivers 70 and 80 based on the light emission driving format shown in FIG. 5B.

[0084] Note that in FIG. 8, the operations in the simultaneous reset step Rc, the light emission sustaining step Ic and the erasure step E are the same as those shown in FIG. 6, and therefore only the operation in the pixel data writing step Wc will now be described.

[0085] In FIG. 8, in the pixel data writing step Wc in the subfield SF1, the address driver 60 produces a pixel data pulse having voltage corresponding to the logical level of a driving pixel data bit DB read out from the memory 7. Note that the address driver 60 produces a high voltage pixel data pulse when the logical level of the driving pixel data bit DB is “1”, and a low voltage (0V) pixel data pulse when the logical level is “0”. In this case, as described above, in the subfield SF1, the first to (h−1)th display lines are non-selected lines among the first to nth display lines, and therefore only driving pixel data bits DB belonging to the hth to nth display lines are read out from the memory 7. As a result, as shown in FIG. 8, the address driver 60 sequentially applies pixel data pulse group DPh, consisting of m pixel data pulses belonging to the hth display line, to pixel data pulse group DPn, belonging to the nth display line, to the column electrodes D1 to Dm. The second sustain driver 80 sequentially applies a scanning pulse SP of negative polarity, as shown in FIG. 8, to the row electrodes Yh to Yn in the same application timings as the pixel data pulse groups DPh to DPn, respectively. Thus, only discharge cells at the intersections of the “rows” provided with the scanning pulse SP and the “columns” provided with the high voltage pixel data pulses are discharged (selective erasure discharge), and wall charges formed in the discharge cells are removed. More specifically, only the discharge cells subjected to the selective erasure discharge attain a “non-light emitting” state, and the discharge cells not subjected to the selective erasure discharge maintain the “light emitting” state.

[0086] As described above, in the pixel data writing step Wc in the subfield SF1, pixel data writing scanning is performed as shown in FIG. 8 only to the hth to nth display lines excluding the non-selected, first to (h−1)th display lines. In this case, the scanning pulse SP and the pixel data pulse group DP are not provided to the non-selected, first to (h−1)th display lines, so that these lines are skipped in the writing scanning.

[0087] In the pixel data writing step Wc in the subfield SF2, as shown in FIG. 8, the address driver 60 produces a pixel data pulse having a voltage corresponding to the logical level of a driving pixel data bit DB read out from the memory 7. Note that the address driver 60 produces a high voltage pixel data pulse when the logical level of the driving pixel data bit DB is “1” and a low voltage (0V) pixel data pulse when the logical level is “0”. In this case, as described above, in the subfield SF2, the ith to (j−1)th display lines among the first to nth display lines are non-selected lines. Therefore, only the driving pixel data bits DB belonging to the first to (i−1)th display lines and the jth to nth display lines are read out from the memory 7. As a result, as shown in FIG. 8, the address driver 60 sequentially applies pixel data pulse group DP1, belonging to the first display line, to pixel data pulse group DPi−1, belonging to the (i−1)th display line, to the column electrodes D1 to Dm. Then, the address driver 60 skips the ith to (j−1)th display lines and sequentially applies pixel data pulse group DPj, belonging to the jth display line, to pixel data pulse group DPn, belonging to the nth display line, to the column electrodes D1 to Dm as shown in FIG. 8. Here, the second sustain driver 80 sequentially applies the scanning pulse SP of negative polarity, as shown in FIG. 8, to the row electrodes Yh to Yn in the same application timings as those of the pixel data pulse groups DP1 to DPi−1 and the pixel data pulse groups DPj to DPn. Thus, only the discharge cells at the intersections of the “rows” provided with the scanning pulse SP and the “columns” provided with the high voltage pixel data pulses are discharged (selective erasure discharge), and wall charges formed in the discharge cells are removed. More specifically, only the discharge cells subjected to the selective erasure discharge attain a “non-light emitting” state, and the discharge cells not subjected to the selective erasure discharge maintain the “light emitting” state.

[0088] As described above, in the pixel data writing step Wc in the subfield SF2, the pixel data writing scanning as shown in FIG. 8 is performed only to display lines excluding the non-selected ith to (j−1)th display lines. At the same time, the non-selected ith to (j−1)th display lines are not provided with the scanning pulse SP and the pixel data pulse group DP and thus skipped in the writing scanning. In the pixel data writing step Wc in the subfields SF3 and SF4, similar to the operations described above, pixel data writing scanning is performed only to the display lines excluding the non-selected lines. In the embodiment shown in FIG. 8, since all the display lines are non-selected lines in the subfield SF4, the pixel data writing scanning, as described above, is not performed. The non-selected lines are not provided with the scanning pulse SP and the pixel data pulse group DP and thus skipped in the writing scanning.

[0089] As described above, according to the present invention, non-selected lines are detected for each subfield and pixel data writing scanning is performed only to the display lines other than the non-selected lines. As a result, the time required for each pixel data writing step Wc is reduced by the time saved by skipping the non-selected lines in the pixel data writing scanning, and spare time TE as shown in FIG. 5B is produced. According to the present invention, the luminance magnification K can be set to a value larger than “1” using the spare time TE. Therefore, when the luminance level of the entire screen is automatically adjusted based on the average luminance level of one screen page, a light emission number larger than the preset reference light emission numbers a1 to a4 can be set for each subfield.

[0090]
FIG. 5C shows a light emission driving format for the driving control circuit 2 when the luminance magnification K is set to a value larger than “1” under the condition of the light emission driving format shown in FIG. 5B.

[0091] By driving as shown in FIG. 5C, the number of light emissions performed in the light emission sustaining step Ic in each of the subfields SF1 to SF4 is produced by multiplying the reference light emission numbers a1 to a4 by K (K>1), and therefore a higher luminance display than the driving, as shown in FIG. 5B, is provided. More specifically, according to the present invention, using the spare time TE created within the display period for one field, the number of light emissions (light emission periods) to be allocated to each light emission sustaining step can be increased, so that a higher luminance display can be provided on the entire screen.

[0092] Note that in the above described embodiment, wall charges are previously formed in all the discharge cells and selectively erased based on pixel data, in other words, a so-called selective erasure addressing method is employed as a pixel data writing method.

[0093] However, according to the present invention, a so-called selective writing addressing method may be applied as a pixel data writing method and wall charges can selectively be formed based on pixel data.

[0094]
FIG. 9 is a chart showing the application timings of various driving pulses to the column electrodes and the row electrode pairs in the PDP 10 by the address driver 60, and the first and second sustain driver 70 and 80 when the selective writing addressing method is employed. FIG. 9 shows various driving pulses applied when gradation driving based on the light emission driving format shown in FIG. 5B is performed, and the application timings of the pulses.

[0095] In FIG. 9, at a certain time during the simultaneous reset step Rc performed at the head of the subfields SF1 to SF4, the first sustain driver 70 applies a reset pulse RPX of negative polarity to all the row electrodes X1 to Xn in the PDP 10. At the same time, the second sustain driver 80 applies a reset pulse RPY of positive polarity to all the row electrodes Y1 to Yn. In response to the application of these reset pulses RPX and RPY, all the discharge cells in the PDP 10 are reset-discharged, and a prescribed quantity of wall charges are equally formed in the discharge cells. Immediately after this, the second sustain driver 80 simultaneously applies an erasure pulse EP to the row electrodes Y1 to Yn. The application of the erasure pulse EP causes erasure discharge and as a result the wall charges formed in all the discharge cells are removed. More specifically, in the simultaneous reset step Rc when the selective writing addressing method, as shown in FIG. 9, is employed, all the discharge cells in the PDP 10 are initialized to the “non-light emitting” state.

[0096] In the pixel data writing step Wc in the subfields SF1 to SF4, the address driver 60 produces a pixel data pulse with a voltage corresponding to the logical level of a driving pixel data bit DB read out from the memory 7. Note that the address driver 60 produces a high voltage pixel data pulse when the logical level of the driving pixel data bit DB is “1” whereas it produces a low voltage (0V) pixel data pulse when the logical level is “0”. At the time, in the subfield SF1, for example, the first to (h−1)th display lines are non-selected lines among the first to nth display lines. Therefore, only the driving pixel data bits DB belonging to the hth to nth display lines are read out from the memory 7. As a result, in the pixel data writing step Wc in the subfield SF1, as shown in FIG. 9, the address driver 60 sequentially applies pixel data pulse group DPh of m pixel data pulses, belonging to the hth display line, to pixel data pulse group DPn, belonging to the nth display line, to the column electrodes D1 to Dm. During the operation, the second sustain driver 80 sequentially applies the scanning pulse SP of negative polarity, as shown in FIG. 9, to the row electrodes Yh to Yn in the same application timings as those of the pixel data pulse groups DP. Thus, only the discharge cells at the intersections of the “rows” provided with the scanning pulse SP and the “columns” provided with the high voltage pixel data pulses are discharged (selective writing discharge), and wall charges are formed in the discharge cells. More specifically, only the discharge cells subjected to the selective writing discharge are set to the “light emitting” state, and the discharge cells not subjected to the selective writing discharge maintain the “non-light emitting” state.

[0097] Then, in the light emission sustaining step Ic in the subfields SF1 to SF4, similar to the case of the selective erasure addressing method, the first and second sustain drivers 70 and 80 alternately apply the sustain pulses IPX and IPY of positive polarity to the row electrodes X1 to Xhn and Y1 to Yn, as shown in FIG. 8. At the same time, in the light emission sustaining step Ic in the subfields SF1 to SF4, the number of sustain pulses applied by the first and second sustain drivers 70 and 80 is based on the light emission numbers A1 to A4 supplied from the light emission number setting circuit 8, as follows.

[0098] A1: SF1

[0099] A2: SF2

[0100] A3: SF3

[0101] A4: SF4

[0102] The light emission sustaining step Ic allows the discharge cells having the remaining wall charges, in other words the “light emitting cells”, to be discharged every time the sustain pulses IPX and IPY are applied. The light emitting state associated with the sustaining discharge is maintained for as many times (periods) as the number of applications.

[0103] At a certain time in the erasure step E at the end of each subfield, the first sustain driver 70 applies the erasure pulse EP, as shown in FIG. 9, to the row electrodes X1 to Xn. Thus, all the discharge cells are simultaneously erasure-discharged, and all the wall charges remaining in the discharge cells are removed.

[0104] As described above, by the selective writing addressing method, pixel data writing scanning is performed only to the display lines other than the non-selected lines for each field. As a result the time required for each pixel data writing step is shortened.

[0105] Note that when the selective writing addressing method is employed, and there are a plurality of light emitting lines with discharge cells all in the “light emitting” state, these lines may simultaneously be subjected to selective writing discharge. Consequently the pixel data writing period is shortened. More specifically, there is a spare time period created corresponding to the reduction in the display period for one field. Similarly, note that when the selective erasure addressing method is employed, and there are a plurality of non-light emitting lines with discharge cells all in the “non-light emitting” state, these lines may simultaneously be subjected to selective erasure discharge. Consequently the pixel data writing period is shortened. More specifically, there is a spare time period created corresponding to the reduction in the display period for one field. Therefore, similar to the above embodiment, the number of light emissions to be performed in the light emission sustaining step in each subfield can be changed using the spare time period.

[0106] As in the foregoing, according to the present invention, non-selected lines are detected in each subfield, and only the display lines other than the non-selected lines are subjected to pixel data writing scanning. As a result, the time required for each pixel data writing step can be shortened by the time period otherwise used for the pixel data writing scanning to the non-selected lines. As a result, according to the invention, the spare time created by the reduction in the time period can be used for increasing the number of light emission (light emitting periods) to be allocated in each light emission sustaining step and high luminance display on the entire screen can be achieved.

[0107] The present application is based on Japanese Patent Application No. 2000-199899 which is hereby incorported by reference.

Plasma display device

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