PLD architecture for flexible placement of IP function blocks

Information

  • Patent Grant
  • 8201129
  • Patent Number
    8,201,129
  • Date Filed
    Wednesday, May 13, 2009
    15 years ago
  • Date Issued
    Tuesday, June 12, 2012
    12 years ago
Abstract
In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.
Description
TECHNICAL FIELD

The present invention is in the field of programmable logic devices (PLD's) and, more particularly, relates to a flexible architecture by which logic elements (LE's) of a PLD having an array of logic elements are replaced with intellectual property (IP) function blocks.


BACKGROUND

Conventional programmable logic devices (PLD's) comprise one or more arrays of logic elements (LE's), and the base signal routing architecture between LE's is designed such that LE-to-LE routing (typically performed by software programs that convert hardware design language program instructions into such routing) is optimized. Examples of PLD's having more than one array include PLD's in the APEX family of devices, by Altera Corporation of San Jose, Calif. It is sometimes desired to add one or more IP function blocks among an LE array. For the purposes of this disclosure, an LE is considered to be a basic—or most common—logic element that functions, for example, with respect to look-up table or macrocell logic. The LE's of an array are nominally connected by a base signal routing architecture. An IP function block is a functional block that is not constrained by the function of the most common logic element. For example, by way of illustration and not by limitation, an IP function block may be a high-speed serial interface (HSSI), a digital signal processor or other microprocessor, ALU, memory, or a multiplier.


Conventionally, when an IP function block is added to an LE array, the IP function block is placed at an edge of the LE array and spanning the entire edge of the LE array. This minimizes the disruption in the base routing. Furthermore, by placing the IP function block at an edge of the array, the performance degradation that would otherwise be caused by routing over the IP function block is minimized. A disadvantage of placing the IP function block at an edge of the LE array, however, is that the input/output (I/O) cells (for communication off the LE array) are conventionally located at the edge of the LE array. The IP function block may not even require access to the I/O cells at that edge but, nonetheless, impedes access by other elements (LE's, or even other IP function block) to the I/O cells at the edge where the IP function block is placed. In some cases, such as is described in U.S. Pat. No. 5,550,782, a block such as an embedded array block (EAB) completely replaces a logic array block (LAB) of LE's. In this case, the routing connects to the EAB in much the same way that the routing interfaces with the conventional logic block and, thus, there is no corresponding performance degradation.


Clearly, placement of an IP function block within an LE array of a PLD has commonly been an afterthought such that, typically, an IP function block was merely placed where it could best fit to minimize the disruption to the base signal routing architecture. What is desired is a PLD architecture by which the placement of an IP function block is not dictated by the goal of minimizing the disruption to the base signal routing architecture.


SUMMARY

In accordance with one aspect of the invention, a “hole” is formed within an LE array of a PLD by interrupting the base signal routing architecture such that a hole is left for the IP function block to be incorporated. An interface region is provided for interfacing the remaining base signal routing to the IP function block. This provides for flexible placement of IP function block within the regular LE-routing structure of the PLD.





BRIEF DESCRIPTION OF FIGURES


FIG. 1 illustrates possible placements of “big” IP function blocks within a PLD and not adjacent to an edge of the LE array, for a “big” IP function block such as a memory for which direct I/O access is not a requirement.



FIGS. 2A, 2B and 2C illustrate possible placements of big IP function blocks within a PLD and adjacent to an edge of the LE array such that direct I/O access is provided.



FIG. 3 illustrates a “donut hole” within the context of a PLD, for placement of a “big” IP function block within a PLD and not adjacent to an edge of the LE array.



FIG. 4 illustrates, in greater detail, a “big block” interface region as used in FIGS. 1, 2 and 3.



FIG. 5 illustrates the horizontal interface to a “big block” that is a large random access memory (“MRAM”).



FIG. 6 illustrates the vertical interface to the MRAM.



FIG. 7 is a table illustrating connectivity details of the MRAM_LIM



FIG. 8 is a table illustrating the MegaRAM_Out signal connections.



FIG. 9 is a table illustrating the Mega-RAM interface specifications.



FIG. 10 illustrates an embodiment of a staggered routing architecture, in which the partial lines at the boundary of the staggered routing architecture are driven.





DETAILED DESCRIPTION


FIGS. 1 and 2 illustrate possible floorplans for a PLD architecture in accordance with an aspect of the invention. The illustrations in FIG. 1 are examples only, and the invention is not limited to the examples shown in FIG. 1. In accordance with the invention, a method of creating the FIG. 1 floorplans (and other floorplans within the scope of the invention) is now described.


The base signal routing architecture is defined and optimized for LE's. For example, an array of LE's is created for a particular target die size. For variants of the created LE array, as discussed in the Background, it is desired to place the IP function block within the LE array. In some embodiments, the IP function block is added as IP function blocks at some desired uniform density, although the density of IP function blocks need not be uniform. For IP function blocks added to the LE array, LE's are replaced. Thus, there is a tradeoff between LE's and the amount of IP added to the die. The array of LE's for which a particular base signal routing architecture is optimized may occupy substantially an entire target die. Alternately, a base signal routing architecture may be optimized for an array of LE's that coexists on a die with other circuitry, including other LE's.



FIGS. 1A, 1B and 1C illustrate IP function block 110 incorporated within the interior of an LE array, for an IP function block that does not require direct I/O pad 112 access. FIGS. 2A and 2B illustrate an IP function block 120 incorporated at the edge of the LE array but not spanning the entire edge of the LE array, such that I/O pad 112 access is provided to the IP function block 120. Furthermore, while not shown in FIGS. 2A and 2B, the IP function block can even displace I/O pads 112, if desired.



FIG. 3 illustrates how an IP function block is incorporated as a “donut hole” 302 as applied to the FIG. 1 examples. That is, within the region where the IP function block is incorporated, the base signal routing architecture is interrupted, and a hole 302 is left (at least in one layer of the metal) for the IP function block to be incorporated. In addition, an interface region 304 is provided completely surrounding the hole 302 for interfacing the remaining base signal array routing to the IP function block. A very specific example of one such interface block is described later with reference to FIGS. 5 and 6. It should be noted that some of the lines of the base signal routing architecture may be routed around the hole 302 by being raised from the interface region 304 at one side of the hole 302 to a different layer of the metal not occupied by the hole 302 and lowered back into the interface region 304 at another side of the hole 302, typically the opposite side of the hole 302. To generalize, signal routing lines for driving shorter distances are terminated, and routing lines for driving longer distances are raised to a different layer of metal, buffered across the hole, and lowered into the interface region at the opposite side of the donut hole. What is “shorter” and “longer” is variable for any particular embodiment and is discussed later with respect to the size of the interruption—“small” or “large.” Typically, those routing lines buffered across a hole do so without being connected to the IP function block in the hole region.


An interface region is provided even when the IP function block is not to be bordered on all four sides by the base signal routing architecture as illustrated in the FIG. 3 embodiment but, rather, is to be bordered on two sides (an example of which is shown in FIG. 2A), three sides (an example of which is shown in FIG. 2B), or even one side (an example of which is shown in FIG. 2C). The interface region is typically provided on each side of the hole that borders the base signal routing architecture.



FIG. 4 illustrates an embodiment of the interface region 304. That is, in accordance with the FIG. 4, it is shown that, for some level of granularity, the interface region 408 includes up to 24 signal lines into the hole 402 and up to 12 signal lines out of the hole 402. The interface region 408 is built modularly, at a particular level of granularity. In one embodiment, the particular level of granularity is one width or height of the logic array block (LAB) of the LE array.


A design consideration for the placement of a hole is the number of signal lines in and out of a hole that would result from a particular placement, primarily as a result of the extent to which the hole would border the base signal routing architecture. This can be seen with reference again to FIGS. 2A and 2B.



FIGS. 5 and 6 illustrate a situation where the IP function block is a RAM block (designated in FIGS. 5 and 6 as a “Mega-RAM” 502). FIG. 5 illustrates the situation from the horizontal routing perspective, and FIG. 6 illustrates the situation from the vertical routing perspective. The Mega-RAM block 502 spans multiple columns and multiple rows of the LE array, and therefore interfaces with many lines (“channels”) of routing. The general routing does not cross the Mega-RAM 502. Rather, the general routing “dead ends” at the Mega-RAM Interface (a specific instance of the FIG. 3 interface region) to form the donut hole for the Mega-RAM. The H24 (FIG. 5) and V16 (FIG. 6) routing lines are buffered across the Mega-RAM block. The Mega-RAM horizontal interface 504 (FIG. 5) allows the Mega-RAM to interface to logic to the left or to the right of the Mega-RAM. The Mega-RAM vertical interface 604 (FIG. 6) allows the Mega-RAM to interface to logic above and below the Mega-RAM. In the Mega-RAM vertical interface (FIG. 6), there are two groups of fifteen MRAM_LIM's (Not all are shown). Each of the two groups is fed by a different V-Channel. One Mega-RAM interface is provided on each of the left and right hand edges of the MegaRAM for every LAB row it spans, and one Mega-RAM interface is provided on each of the top and bottom edges of the Mega-Ram for every pair of LAB columns it spans.


Driving into the Mega-RAM 502 is now described. H and V routing lines in a typical embodiment connect into MRAM_LIM's 506, 606a and 606b (LAB input multiplexers). The MRAM_LIM 506, 606a and 606b is a two stage 4-way sharing multiplexer. Of the portion of the routing that terminates at the boundaries of the Mega-RAM 502, only the routing able to carry signals toward the Mega-RAM 502 feeds the MRAM_LIM's 506, 606a and 606b. Therefore, if the routing is unidirectional (i.e., each line can carry a signal in one direction), then routing able to carry signals away from the MRAM will not be coupled to the input interface. In another embodiment, bi-directional lines are used in addition to, or in place of, unidirectional lines.


Connectivity details of the MRAM_LIM 506, 606a and 606b are listed in the table of FIG. 7. Briefly, FIG. 7 lists the number of “ways in per line” and the number of “connections per MRAM_LIM” for each of the Horizontal MegaRAM interface (FIG. 5) and the Vertical MegaRAM interface (FIG. 6). At the bottom of the FIG. 7 table, the listed totals include the total number of MRAM_LIM fan in signals, and the total number of MRAM_LIM multiplexers, for each of the Horizontal MegaRAM interface and the Vertical MegaRAM interface.


Clock inputs 524 are taken into the Mega-RAM block 502 from the global clock network at the side of the Mega-RAM block 502 through the Mega-RAM horizontal interface 504 in (FIG. 5). The MRAM_CLOCK MUX 526 chooses one of the eight LABCLK's that are feeding through the adjacent LABs. There is one clock input to the Mega-RAM 502 per row, although the Mega-RAM 502 typically would not use every clock input available to it.


The Mega-RAM input mux (“MRIM”) is a fully populated 4-way mux-sharing mux that connects thirty LAB lines onto twenty-four I/O block inputs.


Driving out of the Mega-RAM 502 is now described. At the edge of the Mega-RAM, routing lines driving into the core do not have LAB's to drive them and are left as partial length lines. The Mega-RAM interface uses the full-length and partial length (i.e., length four and length eight lines, in this embodiment) to connect to the core via the MRAM_DIM. The Mega-RAM interface provides similar resources as are provided for a LAB to drive onto the core routing. For example, H4 lines extending four LAB's into the core are driven, and H4 lines extending three LAB's in or less are not driven. These partial length lines are driven to Vcc. In another embodiment, the partial length lines connect to the MRAM_LIM's as described below with reference to FIG. 10.


The Mega-RAM horizontal interface can also drive signals out onto the adjacent V-channel routing. Ten partial length sneak paths (H4, H8, V16, H24) (e.g., as collectively designated by line 528) are driven directly into adjacent LAB's by ten of the twelve MegaRAM_Out signals for a “quick” path to logic.


Each MRAM driver input multiplexer (“MRAM DIM”) 612a, 612b supports the V-channel at the edge of the core and the half H-channel able to carry signals from the MRAM in the direction of the core. The Mega-RAM vertical interface 604 drives the full-length routing resources of two full V-channels. These drivers are dedicated to the MegaRAM_Out signals and do not support turns from other routing resources. The DIM's 612a and 612b associated with the V-line drivers in the Mega-RAM vertical interface 604 are used to choose between MegaRAM_Out signals. Each DIM 612a, 612b in the vertical interface is a 4:1 mux that can be implemented in one or more stages, and each input to the DIM is a MegaRAM_Out signal. The connection pattern from the MegaRAM_Out signals to the DIM 612a, 612b is typically spread equally between the two V-channels.


The number of MegaRAM_Out signal connections per DIM for each of the Mega_RAM Horizontal Interface (FIG. 5) and the Mega_RAM Vertical Interface (FIG. 6) are set forth in FIG. 8. FIG. 9 is a summary of the Mega_RAM interface specifications for each of the Mega_RAM Horizontal Interface and the Mega_RAM Vertical Interface, and lists the total number of the various interface components described above.


It is noted that, typically, not all IP function blocks need be incorporated into an LE array using the hole concept. For example, the IP function block may be of two types—small and large. In general, the terms small and large as used here can be thought of as indicating size. One actual design consideration, however, in determining whether to consider particular IP function block as small or large is a consideration of how much disruption to the timing of signal routing is to be tolerated. For example, in accordance with one embodiment, a small block is an IP function block whose layout can be drawn at a width on the order of an LE width. In accordance with this embodiment, the width of small blocks may be wider than an LE so long as the timing of signal routing over the block does not get significantly larger than for routing over an LE. For example, in one 0.13 μm architecture, it has been deemed that the timing of the signal routing over a block of roughly 5 LE widths does not get significantly larger than for routing over an LE. Typically, additional inputs and/or outputs may be added that exceed the width of an LE, so long as the base signal routing architecture across the IP function block is maintained with the LE's surrounding the small block. Another consideration for determining whether an IP function block is large (implemented using the hole concept) or small is the size of the IP function block relative to the overhead associated with employing an interface region. In one embodiment, small blocks include MEAB's (medium sized embedded array blocks), SEAB's (small sized embedded array blocks) and a DSP block. By contrast, large blocks are IP function blocks that typically have dimensions much larger than that of an LE. Extending the base signal routing architecture across these blocks without modification would cause routing over these blocks to be significantly larger than routing over an LE, forming a boundary in the PLD timing model. Such large blocks may be inserted into the LE array as holes in the base signal routing architecture, as described above. In some sense, what occurs at the boundary between the base signal routing architecture and a hole is similar to the base signal routing architecture ending at the edge of an LE array.


In some embodiments, shown with reference to FIG. 10, the LE routing lines are part of a staggered, uni-directional routing architecture. As a result of the staggering, as can be seen from FIG. 10, there are partial lines 1002 at boundaries formed by, for example, the I/O interface 1008 at the edge of the PLD 1001 or by an inserted IP function block (designated by reference numeral 1004). In accordance with some such staggered architecture embodiments, routing drivers 1006 are included in the interface region 1008 (whether the I/O interface region or the hole interface region) to drive both the full and partial lines. The output ports 1010 of the logic block 1004 connect to the drivers of both the “full” lines and the “partial” lines. Signal selection muxes may be used in front of the drivers to add routing flexibility. As described above, the routing may also be implemented with segmented bi-directional lines.


The partial lines 1002 driving out of the PLD core 1001 feed an input selection mux 1012 to drive into the logic block 1004. These partial lines 1002 impose a smaller load on the drivers 1014 than do full lines 1016, and having a small load makes the partial line 1002 a faster path into the PLD core 1001. If area is a concern, drivers 1018 for partial lines 1002 may be smaller than drivers 1020 for full lines 1016, and still not be at a speed disadvantage due to the smaller load.


Furthermore, by driving even the partial lines 1002, additional routing flexibility is provided for signals from the PLD core 1001 to the PLD boundaries. Allowing the partial lines 1002 headed out of the PLD 1001 to drive into an IP function block 1004 increases the routability from the PLD core 1001 to the logic block 1004. In addition, the additional drivers 1018 may be used to provide the core 1001 access to more signals, or the signals may be used to provide more paths into the PLD core 1001 for a given signal. Thus, quite simply, lines that would have otherwise been unused are utilized to provide needed access to the PLD core 1001.


While the present invention has been particularly described with respect to the illustrated embodiments, it will be appreciated that various alterations, modifications and adaptations may be based on the present disclosure, and are intended to be within the scope of the present invention. While the invention has been described in connection with what are presently considered to be the most practical and preferred embodiments, it is to be understood that the present invention is not limited to the disclosed embodiment but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the scope of the claims. For example, the techniques described herein may be applied to other types of fixed blocks or routing structures.

Claims
  • 1. A programmable logic device, comprising: a plurality of logic elements arranged in a predetermined pattern;a base signal routing architecture including a plurality of signal routing lines to route signals among the logic elements;at least one IP function block inserted into the predetermined pattern in place of a two-dimensional portion of the logic elements, the insertion of the IP function block interrupting, at least in part, the base signal routing architecture; andan interface region existing between the logic elements and the IP function block, the interface region comprising interfacing circuitry operative to selectively apply signals to and from the IP function block.
  • 2. The programmable logic device of claim 1, wherein the interfacing circuitry selectively applies a signal provided by the base signal routing architecture to the IP function block as a function block input signal.
  • 3. The programmable logic device of claim 1, wherein the interfacing circuitry selectively applies a signal provided by a logic element immediately adjacent to the interface region to the IP function block as a function block input signal.
  • 4. The programmable logic device of claim 1, wherein the interfacing circuitry selectively applies an IP function block output signal provided by the IP function block to the base signal routing architecture.
  • 5. The programmable logic device of claim 1, wherein the interfacing circuitry selectively applies an IP function block output signal provided by the IP function block to a logic element immediately adjacent to the interface region.
  • 6. The programmable logic device of claim 1, further comprising a plurality of memory blocks that are included within the predetermined pattern of logic elements, wherein the interface region exists between the memory blocks and the IP function block, the interface region comprising interfacing circuitry operative to route signals to and from the IP function block.
  • 7. The programmable logic device of claim 6, wherein the interfacing circuitry selectively applies a signal provided by a memory block immediately adjacent to the interface region as a function block input signal.
  • 8. The programmable logic device of claim 6, wherein the interfacing circuitry selectively applies an IP function block output signal provided by the IP function block to a memory block immediately adjacent to the interface region.
  • 9. The programmable logic device of claim 1, wherein the interfacing circuitry comprises at least one multiplexer.
  • 10. The programmable logic device of claim 1, wherein the interfacing circuitry comprises interfacing logic.
  • 11. The programmable logic device of claim 1, further comprising a plurality of input/output pads, wherein the function block is incorporated into the predetermined pattern of logic elements such that the interfacing region has direct access to at least one of the input/output pads.
  • 12. The programmable logic device of claim 1, further comprising a plurality of input/output pads, wherein the function block is incorporated into the predetermined pattern of logic elements such that it displaces at least one of the input/output pads.
  • 13. The programmable logic device of claim 1, wherein the base signal routing architecture comprises short lines and long lines, wherein a first subset of the short lines connect to the IP function block and second subset of the short lines terminate at the IP function block while at least one long line is buffered over the IP function block.
  • 14. The programmable logic device of claim 1, wherein the IP function block is selected from the group consisting of high-speed serial interface, a digital signal processor, a microprocessor, arithmetic logic unit, memory, random access memory, and a multiplier.
  • 15. A semiconductor integrated circuit, comprising: a plurality of components arranged in a multi-dimensional array with at least one IP function block inserted into the array; anda base signal routing architecture connected to the components and at least partially interrupted by the IP function block, such that a first portion of the base routing architecture is coupled to the IP function block and a second portion of the base signal routing architecture is selectively applied over the IP function block.
  • 16. The semiconductor integrated circuit of claim 15, wherein at least a subset of the first portion is terminated at the IP function block.
  • 17. The programmable logic device of claim 16, wherein the IP function block is selected from the group consisting of high-speed serial interface, a digital signal processor, a microprocessor, arithmetic logic unit, memory, random access memory, and a multiplier.
  • 18. The semiconductor integrated circuit of claim 15, wherein: the semiconductor integrated circuit further comprises an interface portion, whereinthe first portion of the base signal routing architecture is coupled to the IP function block via the interface portion.
  • 19. The semiconductor integrated circuit of claim 15, wherein the base signal routing architecture includes long routing lines and short routing lines, wherein at least some of the long routing lines are routed across the IP function block and at least some of the short routing lines terminate or connect to the IP function block.
  • 20. The semiconductor integrated circuit of claim 15, wherein the components comprise logic elements.
  • 21. The semiconductor integrated circuit of claim 15, wherein the components comprise memory blocks.
  • 22. The semiconductor integrated circuit of claim 15, wherein the multi-directional array is a three-dimensional array comprising rows and columns of the components that exist in layers in a plurality of layers.
  • 23. The semiconductor integrated circuit of claim 22, wherein the first portion of the base signal routing architecture and the IP function block reside in a subplurality of the layers and wherein the second portion of the base signal routing architecture resides in layers other than the subplurality of layers.
  • 24. The semiconductor integrated circuit of claim 15 wherein the IP function block is a first IP function block, the semiconductor integrated circuit further comprising: a second IP function block inserted into the multi-dimensional array of components, wherein the base signal routing architecture is at least partially interrupted by the second IP function block, such that a third portion of the base signal routing architecture is terminated at the second IP function block and a fourth portion of the base signal routing architecture is routed across the second IP function block.
  • 25. The semiconductor integrated circuit of claim 15, wherein the timing of the second portion of the base signal routing architecture is delayed by less than a predetermined threshold as compared to the timing of a portion of the base signal routing architecture that is not interrupted by the IP function block and that spans approximately the same distance as the second portion.
  • 26. A semiconductor integrated circuit, comprising: a plurality of components arranged in a multi-dimensional array with at least one IP function block inserted into the array; anda base signal routing architecture connected to the components and at least partially interrupted by the IP function block, such that a first portion of the base routing architecture is terminated at the IP function block and a second portion of the base signal routing architecture is selectively applied across the IP function block.
  • 27. The semiconductor integrated circuit of claim 26, wherein: the semiconductor integrated circuit further comprises an interface portion, whereinsignals existing on the first portion of the base signal routing architecture are selectively routed to the IP function block via the interface portion.
  • 28. The semiconductor integrated circuit of claim 26, wherein the components comprise logic elements.
  • 29. The semiconductor integrated circuit of claim 26, wherein the components comprise memory elements.
  • 30. The programmable logic device of claim 26, wherein the IP function block is selected from the group consisting of high-speed serial interface, a digital signal processor, a microprocessor, arithmetic logic unit, memory, random access memory, and a multiplier.
RELATED APPLICATIONS

This is a division of commonly-assigned U.S. patent application Ser. No. 11/202,616, filed Aug. 12, 2005, now U.S. Pat. No. 7,584,447, which is a continuation of application Ser. No. 10/460,685, filed Jun. 11, 2003, now U.S. Pat. No. 7,058,920, which was a division of application Ser. No. 10/057,442, filed Jan. 25, 2002, now U.S. Pat. No. 6,605,962, which claimed the benefit of U.S. Provisional Patent Application No. 60/289,311, filed May 6, 2001. Each of these prior applications is hereby incorporated by reference herein in its respective entirety.

US Referenced Citations (180)
Number Name Date Kind
4758985 Carter Jul 1988 A
4855669 Mahoney Aug 1989 A
4870302 Freeman Sep 1989 A
4871930 Wong et al. Oct 1989 A
5072418 Boutaud et al. Dec 1991 A
5121006 Pedersen Jun 1992 A
5142625 Nakai Aug 1992 A
5206529 Mine Apr 1993 A
RE34363 Freeman Aug 1993 E
5241224 Pedersen et al. Aug 1993 A
5243238 Kean Sep 1993 A
5260611 Cliff et al. Nov 1993 A
5274570 Izuma et al. Dec 1993 A
5311114 Sambamurthy et al. May 1994 A
5339262 Rostoker et al. Aug 1994 A
5347181 Ashby et al. Sep 1994 A
5361373 Gilson Nov 1994 A
5414638 Verrheyen et al. May 1995 A
5424589 Dobbelaere et al. Jun 1995 A
5455525 Ho et al. Oct 1995 A
5457410 Ting Oct 1995 A
5469003 Kean Nov 1995 A
5473267 Stansfield Dec 1995 A
5485103 Pedersen et al. Jan 1996 A
5500943 Ho et al. Mar 1996 A
5504738 Sambamurthy et al. Apr 1996 A
5537057 Leong et al. Jul 1996 A
5537601 Kimura et al. Jul 1996 A
5541530 Cliff et al. Jul 1996 A
5543640 Sutherland et al. Aug 1996 A
5550782 Cliff et al. Aug 1996 A
5552722 Kean Sep 1996 A
5557217 Pedersen Sep 1996 A
5574930 Halverson, Jr. et al. Nov 1996 A
5574942 Colwell et al. Nov 1996 A
5581199 Pierce et al. Dec 1996 A
5581745 Muraoka Dec 1996 A
5592106 Leong et al. Jan 1997 A
5600845 Gilson Feb 1997 A
5652904 Trimberger Jul 1997 A
5654650 Gissel Aug 1997 A
5671355 Collins Sep 1997 A
5682107 Tavana et al. Oct 1997 A
5689195 Cliff et al. Nov 1997 A
5701091 Kean Dec 1997 A
5705938 Kean Jan 1998 A
5705939 McClintock et al. Jan 1998 A
5732250 Bates et al. Mar 1998 A
5737631 Trimberger Apr 1998 A
5740404 Baji Apr 1998 A
5742179 Sasaki Apr 1998 A
5742180 DeHon et al. Apr 1998 A
5748979 Trimberger May 1998 A
5752035 Trimberger May 1998 A
5760604 Pierce et al. Jun 1998 A
5760607 Leeds et al. Jun 1998 A
5787007 Bauer Jul 1998 A
5801546 Pierce et al. Sep 1998 A
5801547 Kean et al. Sep 1998 A
5804986 Jones Sep 1998 A
5809517 Shimura Sep 1998 A
5825202 Tavana et al. Oct 1998 A
5831448 Kean et al. Nov 1998 A
5835405 Tsui et al. Nov 1998 A
5847579 Trimberger Dec 1998 A
5874834 New et al. Feb 1999 A
5880598 Duong Mar 1999 A
5889411 Chaudhry Mar 1999 A
5889788 Pressly et al. Mar 1999 A
5892961 Trimberger Apr 1999 A
5903165 Jones et al. May 1999 A
5907248 Bauer et al. May 1999 A
5909126 Cliff et al. Jun 1999 A
5914616 Young et al. Jun 1999 A
5914902 Lawrence et al. Jun 1999 A
5933023 Young Aug 1999 A
5942913 Young et al. Aug 1999 A
5970254 Cooke et al. Oct 1999 A
5977793 Reddy et al. Nov 1999 A
6011407 New Jan 2000 A
6020755 Andrews et al. Feb 2000 A
6026481 New et al. Feb 2000 A
6054873 Laramie Apr 2000 A
6057707 Schleicher et al. May 2000 A
6081473 Agarwal et al. Jun 2000 A
6084429 Trimberger Jul 2000 A
6096091 Hartmann Aug 2000 A
6107824 Reddy et al. Aug 2000 A
6137308 Nayak Oct 2000 A
6150837 Beal et al. Nov 2000 A
6154051 Nguyen et al. Nov 2000 A
6154873 Takahashi Nov 2000 A
6163166 Bielby et al. Dec 2000 A
6172990 Deb et al. Jan 2001 B1
6178541 Joly et al. Jan 2001 B1
6181160 Lee Jan 2001 B1
6181163 Agrawal et al. Jan 2001 B1
6184706 Heile Feb 2001 B1
6184712 Wittig et al. Feb 2001 B1
6204689 Percey et al. Mar 2001 B1
6204690 Young et al. Mar 2001 B1
6211697 Lien et al. Apr 2001 B1
6218859 Pedersen Apr 2001 B1
6242945 New Jun 2001 B1
6242947 Trimberger Jun 2001 B1
6255849 Mohan Jul 2001 B1
6265895 Schleicher et al. Jul 2001 B1
6271679 McClintock et al. Aug 2001 B1
6272451 Mason et al. Aug 2001 B1
6278291 McClintock et al. Aug 2001 B1
6279045 Muthujumaraswathy et al. Aug 2001 B1
6282627 Wong et al. Aug 2001 B1
6289412 Yuan et al. Sep 2001 B1
6292018 Kean Sep 2001 B1
6300793 Ting et al. Oct 2001 B1
6300794 Reddy et al. Oct 2001 B1
6301696 Lien et al. Oct 2001 B1
6329839 Pani et al. Dec 2001 B1
6343207 Hessel et al. Jan 2002 B1
6346824 New Feb 2002 B1
6353331 Shimanek Mar 2002 B1
6356108 Rangasayee Mar 2002 B2
6356987 Aulas Mar 2002 B1
6370140 Nayak Apr 2002 B1
6389558 Herrmann et al. May 2002 B1
6417690 Ting et al. Jul 2002 B1
6427156 Chapman et al. Jul 2002 B1
6429681 Hutton Aug 2002 B1
6434735 Watkins Aug 2002 B1
6448808 Young et al. Sep 2002 B2
6460172 Insenser Farre et al. Oct 2002 B1
6463576 Tomoda Oct 2002 B1
6467009 Winegarden et al. Oct 2002 B1
6476636 Lien et al. Nov 2002 B1
6484291 Amiya et al. Nov 2002 B1
6507942 Calderone et al. Jan 2003 B1
6510548 Squires Jan 2003 B1
6518787 Allegrucci et al. Feb 2003 B1
6519753 Ang Feb 2003 B1
6522167 Ansari et al. Feb 2003 B1
6532572 Tetelbaum Mar 2003 B1
6539508 Patrie et al. Mar 2003 B1
6541991 Horncheek et al. Apr 2003 B1
6570404 Norman et al. May 2003 B1
6573138 Pass et al. Jun 2003 B1
6573749 New et al. Jun 2003 B2
6577160 Reddy et al. Jun 2003 B2
6587995 Duboc et al. Jul 2003 B1
6588006 Watkins Jul 2003 B1
6593772 Ngai et al. Jul 2003 B2
6601227 Trimberger Jul 2003 B1
6604228 Patel et al. Aug 2003 B1
6604230 Khalid et al. Aug 2003 B1
6608500 Lacey et al. Aug 2003 B1
6611951 Tetelbaum et al. Aug 2003 B1
6634008 Dole Oct 2003 B1
6662285 Douglass et al. Dec 2003 B1
6744278 Liu et al. Jun 2004 B1
6771094 Langhammer et al. Aug 2004 B1
6864710 Lacey et al. Mar 2005 B1
6904527 Parlour et al. Jun 2005 B1
7236008 Cliff et al. Jun 2007 B1
20010033188 Aung et al. Oct 2001 A1
20010049813 Chun et al. Dec 2001 A1
20020008541 Young et al. Jan 2002 A1
20020011871 Pani et al. Jan 2002 A1
20020070756 Ting et al. Jun 2002 A1
20020089348 Langhammer Jul 2002 A1
20020101258 Ting Aug 2002 A1
20020130681 Cliff et al. Sep 2002 A1
20020163358 Johnson et al. Nov 2002 A1
20020190751 Lee et al. Dec 2002 A1
20030062922 Donblass et al. Apr 2003 A1
20030188287 Park Oct 2003 A1
20030201794 Reddy et al. Oct 2003 A1
20040017222 Betz et al. Jan 2004 A1
20040032282 Lee et al. Feb 2004 A1
20040088672 Ting May 2004 A1
20040150422 Wong Aug 2004 A1
20040196066 Ting Oct 2004 A1
Foreign Referenced Citations (25)
Number Date Country
0 079 127 May 1983 EP
0 315 275 May 1989 EP
0 415 542 Mar 1991 EP
0 486 248 May 1992 EP
0 806 836 Nov 1997 EP
0 905 906 Mar 1999 EP
0 919 916 Jun 1999 EP
0 734 573 Apr 2002 EP
1 235 351 Aug 2002 EP
2 300 951 Nov 1996 GB
58-087644 May 1983 JP
61-097849 May 1986 JP
2-205342 Aug 1990 JP
5-040804 Feb 1993 JP
07-142583 Jun 1995 JP
10-074840 Mar 1998 JP
10-092943 Apr 1998 JP
2000-150894 May 2000 JP
2000-315731 Nov 2000 JP
2001-005858 Jan 2001 JP
2003-023083 Jan 2003 JP
WO9325968 Dec 1993 WO
WO9428475 Dec 1994 WO
WO9956394 Nov 1999 WO
WO0044095 Jul 2000 WO
Related Publications (1)
Number Date Country
20090224800 A1 Sep 2009 US
Provisional Applications (1)
Number Date Country
60289311 May 2001 US
Divisions (2)
Number Date Country
Parent 11202616 Aug 2005 US
Child 12465464 US
Parent 10057442 Jan 2002 US
Child 10460685 US
Continuations (1)
Number Date Country
Parent 10460685 Jun 2003 US
Child 11202616 US