Patent Application
20200098500
The present embodiments relate generally inductors, and specifically to point-symmetric on-chip inductors.
Inductors may be used in many types of circuits including, for example, radio-frequency (RF) circuits, voltage-controlled oscillators (VCOs), low-noise amplifiers (LNAs), and passive-element filters. In general, an inductor is a passive electrical component that stores energy in a magnetic field. The inductor may produce a magnetic field when electric current flows through the conductor or produce an electric current in the conductor in response to a changing magnetic field.
An inductor may be formed using one or more turns of an electrical conductor, such as a metal (aluminum, copper, and the like) or a heavily doped semiconductor material. A planar inductor may be formed on any feasible plane surface including, but not limited to, integrated circuits and printed circuit boards. Some RF circuits use differential signal processing techniques to achieve enhanced linearity, dynamic range, and output power. Using non-symmetric electrical components, such as a non-symmetric inductor, in differential circuits may reduce circuit performance
This Summary is provided to introduce in a simplified form a selection of concepts that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.
One innovative aspect of the subject matter described herein may be implemented as an apparatus that may include a first spiral inductor configured to loop in a first direction, a second spiral inductor configured to loop in a second direction, opposite to the first direction, and a crossover conductor configured to connect the first spiral inductor to the second spiral inductor. In some implementations, the first spiral inductor and the second spiral inductor may form a twin-spiral inductor. The apparatus may also include a first terminal disposed on an end of an inner loop of the first spiral inductor proximal to the crossover conductor and a second terminal disposed on an end of an inner loop of the second spiral inductor proximal to the crossover conductor, wherein each portion of the first spiral inductor has a corresponding portion in the second spiral inductor that is an identical distance, in an opposite direction, from a central point of the twin-spiral inductor.
Another aspect of the subject matter of this disclosure may be implemented as a circuit. The circuit may include a first spiral inductor configured to loop in a first direction, a second spiral inductor configured to loop in a second direction, opposite to the first direction, and a crossover conductor configured to connect the first spiral inductor to the second spiral inductor. In some implementations, the first spiral inductor and the second spiral inductor may form a twin-spiral inductor. The circuit may also include a first terminal disposed on an end of an inner loop of the first spiral inductor proximal to the crossover conductor and a second terminal disposed on an end of an inner loop of the second spiral inductor proximal to the crossover conductor, wherein each portion of the first spiral inductor has a corresponding portion in the second spiral inductor that is an identical distance, in an opposite direction, from a central point of the circuit. The circuit may also include a drain terminal coupled to the first terminal of the first spiral inductor; and a second transistor comprising a drain terminal coupled to the second terminal of the second spiral inductor, wherein the first transistor and the second transistor are disposed on a second side of the substrate within a crossover area of the twin-spiral inductor.
Aspects of the present disclosure are illustrated by way of example and are not intended to be limited by the figures of the accompanying drawings. Like numbers reference like elements throughout the drawings and specification.
In the following description, numerous specific details are set forth such as examples of specific components, circuits, and processes to provide a thorough understanding of the disclosure. The term “coupled” as used herein means coupled directly to or coupled through one or more intervening components or circuits. Also, in the following description and for purposes of explanation, specific nomenclature is set forth to provide a thorough understanding of the example embodiments. However, it will be apparent to one skilled in the art that these specific details may not be required to practice the example embodiments. In other instances, well-known circuits and devices are shown in block diagram form to avoid obscuring the disclosure. Any of the signals provided over various buses described herein may be time-multiplexed with other signals and provided over one or more common buses. Additionally, the interconnection between circuit elements or software blocks may be shown as buses or as single signal lines. Each of the buses may alternatively be a single signal line, and each of the single signal lines may alternatively be buses, and a single line or bus might represent any one or more of a myriad of physical or logical mechanisms for communication between components. The example embodiments are not to be construed as limited to specific examples described herein but rather to include within their scope all embodiments defined by the appended claims.
The techniques described herein may be implemented in hardware, software, firmware, or any combination thereof, unless specifically described as being implemented in a specific manner Any features described as modules or components may also be implemented together in an integrated logic device or separately as discrete but interoperable logic devices. If implemented in software, the techniques may be realized at least in part by a non-transitory computer-readable storage medium comprising instructions that, when executed, performs one or more of the methods described below. The non-transitory computer-readable storage medium may form part of a computer program product, which may include packaging materials.
The first spiral inductor 102 may include an inner terminal 106 and an outer terminal 108. Interconnect lines 110 and 112 may be connected to the inner terminal 106 and the outer terminal 108, respectively, to enable current to flow through first spiral inductor 102. Current flow through the first spiral inductor 102 may be controlled by a first transistor 115. Similarly, the second spiral inductor 104 may include an inner terminal 116 and an outer terminal 118. Interconnect lines 120 and 122 may be connected to the inner terminal 116 and the outer terminal 118, respectively, to enable current to flow through second spiral inductor 104. Current flow through the second spiral inductor 104 may be controlled by a second transistor 125. The dashed lines may indicate that the interconnect lines 110, 112, 120, 122 and transistors 115125 may be disposed on a layer of the substrate other than the first layer of the substrate.
Also shown in
The twin-spiral inductor 201 may include a first terminal 204 and a second terminal 208. A first interconnect line 210 may be coupled to the first terminal 204, and a second interconnect line 212 may be coupled to the second terminal 208. The dashed lines indicate that the interconnect lines 210 and 212 may be disposed on a layer other than the first layer of the substrate. The first interconnect line 210 and the second interconnect line 212 extend outward from the inductor 201 (e.g., outward from the central point 225), where they may be connected to other electrical components, such as resistors, capacitors and transistors, and other circuits or devices not shown for simplicity.
The twin-spiral inductor 303 may include a first spiral inductor 310 that spirals outward in a first direction from the first terminal 305, and may include a second spiral inductor 311 that spirals outward in a second direction (opposite to the first direction) from the second terminal 308. As shown, the first spiral inductor 310 spirals clockwise from the first terminal 305, and the second spiral inductor 311 spirals counter-clockwise from the second terminal 308. In another implementation, the first spiral inductor 310 may spiral counter-clockwise from the first terminal 305, and the second spiral inductor 311 may spiral clockwise from the second terminal 308. The twin-spiral inductor 303 may also include a crossover conductor 313 disposed midway between the first terminal 305 and the second terminal 308 that couples the first spiral inductor 310 to the second spiral inductor 311. In some implementations, the first spiral inductor 310 and the second spiral inductor 311 may each have a generally octagonal shape. In other implementations, the first spiral inductor 310 and the second spiral inductor 311 may each have other suitable shapes.
The twin-spiral inductor 303 may be point-symmetric about a central point 330, which may be an origin of a reference coordinate system including X and Y axes. As shown in
The differential circuit 300 may include a crossover area 320 (shown as a dotted line) that includes at least a portion of the crossover conductor 313 and one or more adjacent loops from the first spiral inductor 310 and the second spiral inductor 311. The crossover area 320 may be projected normal to the plane containing the twin-spiral inductor 303. In some implementations, one or more electronic devices and/or components may be disposed within the crossover area 320 projected onto other layers or sides of the substrate. For example, electronic devices and/or components such as transistors, resistors and capacitors may be disposed on a layer within the projected crossover area 320 and “beneath” the crossover conductor 313 and associated adjacent loops of the first spiral inductor 310 and the second spiral inductor 311. In some implementations, a device may be considered to be beneath another device when a line that is normal to the plane of the substrate intersects both devices. The electronic devices and/or components beneath the crossover area 320 may be coupled to the inductor 303 to form a voltage-controlled oscillator (VCO), a low-noise amplifier (LNA), or any other feasible electronic circuit.
The first terminal 305 and the second terminal 308 may be coupled to conductive vias and/or traces, not shown for simplicity, to couple the twin-spiral inductor 303 to the electronic devices and/or components beneath the crossover area 320. Locating the first terminal 305 and the second terminal 308 proximal to the crossover area 320 may help minimize interference between the twin-spiral inductor 303 and any electronic devices and/or components disposed beneath the crossover area 320.
In some implementations, a degradation or change of inductive characteristics of the twin-spiral inductor 303 may be avoided by careful placement of the electronic devices and/or components, for example, in a manner that avoids current loops beneath the inductor and thereby generates little or no Eddy currents (which may adversely affect the characteristics of the twin-spiral inductor 303. Advantageously, the point of symmetry and the crossover conductor 313 may operate at virtual ground potential. Therefore, any parasitic capacitance between the inductor and the other devices that are disposed beneath the crossover conductor 313 does not load (e.g., affect the characteristics of) the twin-spiral inductor 303.
In some implementations, the electronic devices and/or components that are beneath the crossover area 320 may be arranged in minor symmetry about the X axis. Alternatively, the electronic devices and/or components that are beneath the crossover area 320 may be arranged to be in minor symmetry about the Y axis. In either case, the symmetry between the two halves of an associated differential circuit that includes the twin-spiral inductor 303 may be maintained.
The twin-spiral inductor 404 may be point-symmetric about a central point 440, which may be an origin of a reference coordinate system comprising X and Y axes. As shown in
In this example, the first spiral inductor 410 and the second spiral inductor 411 each include a single conductive loop, coupled together by a crossover conductor 414 beneath which other electronic devices and/or components may be arranged or positioned. The twin-spiral inductor 404 may include a first terminal 405 and a second terminal 408. The first terminal 405 and the second terminal 408 may be located at ends of inner loops of the first spiral inductor 410 and the second spiral inductor 411, respectively. Similar to the twin-spiral inductor 303 of
The differential circuit 400 may include a crossover area 420 (denoted with a dotted line) which in turn includes at least portion of the crossover conductor 414. Some electronic devices and/or components such as transistors, resistors and capacitors may be located beneath the crossover area 420 and placed on other layers of the substrate. Placing electronic devices and/or components beneath the crossover area 420 may have adverse effects on the characteristics of the twin-spiral inductor 404. Minor symmetry of the electronic devices and/or components disposed beneath the crossover area 420 may be accomplished, for example, by having conductive lines such as interconnect lines (not shown for simplicity) for terminals 405 and 408 extend in a direction parallel to the X axis or the Y axis by an amount that is symmetric about the other axis.
The twin-spiral inductor 505 may be point-symmetric about a central point 516, which may be an origin of a reference coordinate system comprising X and Y axes. As shown in
In this example, the first spiral inductor 508 and second spiral inductor 510 may have more loops compared to the twin-spiral inductor 303 of
The twin-spiral inductor 505 may include a first terminal 512 and a second terminal 514. The first terminal 512 and the second terminal 514 may be located at ends of inner loops of the first spiral inductor 508 and the second spiral inductor 510. Similar to the twin-spiral inductor 303 of
The differential circuit 500 may include a crossover area 520 (shown as a dotted line) that includes at least a portion of the crossover conductor 515 and one or more adjacent loops from the first spiral inductor 508 and the second spiral inductor 510. The crossover area 520 may be projected normal to the plane containing the twin-spiral inductor 505. In some implementations, one or more electronic devices and/or components may be disposed within the crossover area 520 projected onto other layers of the substrate.
The crossover area 520 may be larger than the crossover area 320 of
In some implementations, the twin-spiral inductor 505 may include a third terminal 517 approximately midway between the first terminal 512 and the second terminal 514. The third terminal 517 may be located at the origin of the X and Y axes, and therefore located at a point of symmetry of the twin-spiral inductor 505. In some implementations, the third terminal 517 may be associated with the first spiral inductor 508 and/or the second spiral inductor 510. Further, for some implementations, the third terminal 517 may function as a virtual ground within the differential circuit 500.
One or more of the devices within the crossover area 601 may be coupled to an embodiment of a twin-spiral inductor (e.g., the twin-spiral inductor 303 of
The first transistor 620, the second transistor 625, the first capacitor 610, the second capacitor 615, and the third capacitor 617 may be arranged in a minor symmetry about the X axis. Electrical conductors 650 may provide input, output, and power supply lines for the first transistor 620, the second transistor 625, the first capacitor 610, the second capacitor 615, and/or the third capacitor 617. Although only eight electrical conductors 650 are shown, in other implementations, the layout 600 may include any feasible number of electrical conductors.
One or more of the devices within the crossover area 701 may be coupled to an embodiment of a twin-spiral inductor (e.g., the twin-spiral inductor 404 of
In some implementations, the first transistor 720, the second transistor 725, the first capacitor 710, the second capacitor 712, the third capacitor 714, the fourth capacitor 716, the first resistor 730, and the second resistor 732 may be arranged in a minor symmetry about the Y axis. Electrical conductors 750 may provide input, output, and power supply lines for the first transistor 720, the second transistor 725, the first capacitor 710, the second capacitor 712, the third capacitor 714, the fourth capacitor 716, the first resistor 730, and/or the second resistor 732. Although only four electrical conductors 750 are shown, in other implementations, the layout 700 may include any feasible number of electrical conductors.
In the foregoing specification, the example embodiments have been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader scope of the disclosure as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.
This application claims the benefit of co-pending and commonly owned U.S. Provisional Patent Application No. 62/733,864 entitled “POINT-SYMMETRIC ON-CHIP INDUCTOR” filed on Sep. 20, 2018, the entirety of which is hereby incorporated by reference.
| Number | Date | Country | |
|---|---|---|---|
| 62733864 | Sep 2018 | US |
