Claims
- 1. A method of chemically modifying a wafer suited for fabrication of semiconductor devices, said method comprising:a) contacting a surface of the wafer with an article comprising a plurality of unit cells repeating across the surface of said article, the individual unit cells comprising at least a portion of a three-dimensional structure and being characterized by a unit cell parameter as follows: [[V1−Vs]/Aas]/Auc>5 where V1 is the volume defined by the area of said unit cell and the height of said structure of said unit cell, Vs is the volume of said structure of said unit cell, Aas is the apparent contact area of said structure of said unit cell, and Auc is the area of said unit cell; and b) moving at least one of the wafer and said article relative to each other in the presence of a polishing composition, said polishing composition being chemically reactive with the surface of the wafer and being capable of either enhancing or inhibiting the rate of removal of at least a portion of the surface of the wafer.
- 2. The method of claim 1, wherein said portion of the wafer comprises a chemically distinct phase of the wafer.
- 3. The method of claim 1, wherein said unit cell comprises a plurality of three-dimensional structures.
- 4. The method of claim 1 wherein said unit cell comprises one three-dimensional structure.
- 5. The method of claim 1 wherein said unit cell comprises a portion of a plurality of three-dimensional structures.
- 6. The method of claim 1, wherein [[V1−Vs]/Aas]/Auc≧10.
- 7. The method of claim 1, wherein [[V1−Vs]/Aas]/Auc≧15.
- 8. The method of claim 1, wherein [[V1−Vs]/Aas]/Auc≧20.
- 9. The method of claim 1, wherein at least one dimension that defines said apparent contact area of said structure is from 1 μm to no greater than 500 μm.
- 10. The method of claim 1, wherein at least one dimension that defines said apparent contact area of said structure is from 1 μm to no greater than 200 μm.
- 11. The method of claim 1, wherein the height of said structure is from 10 μm to 500 μm.
- 12. The method of claim 1, wherein 15 μm≧Auc≧2000 μm.
- 13. The method of claim 1 wherein the apparent area of contact of an individual structure is from 1 μm2 to 200,000 μm2.
- 14. The method of claim 1, wherein said article comprises a fixed abrasive article suitable for modifying the surface of a wafer suited for fabrication of semiconductor devices, said article further comprising:a plurality of fixed abrasive structures located in a predetermined arrangement in a region of said article, said region being of a dimension sufficient to planarize the surface of a wafer suited for fabrication of semiconductor devices.
- 15. The method of claim 14, wherein said region comprises at least about 10 structures/linear cm.
- 16. The method of claim 14, wherein said region comprises at least about 50 structures/linear cm.
- 17. The method of claim 14, wherein said region comprises at least about 500 structures/linear cm.
- 18. The method of claim 14, wherein said three-dimensional structures are uniformly distributed in said region.
- 19. The method of claim 1, wherein said three-dimensional structures are arranged in a pattern having a repeating period.
- 20. The method of claim 1, wherein said three-dimensional structures are located in clusters.
- 21. The method of claim 1, wherein said three-dimensional structures further comprise a binder and abrasive particles disposed in said binder.
- 22. The method of claim 1, wherein said three-dimensional structures are essentially free of inorganic abrasive particles.
- 23. The method of claim 1, wherein said three-dimensional structures are essentially free of components reactive with a wafer suited for fabrication of semiconductor devices.
- 24. The method of claim 1, wherein said three-dimensional structures comprise a form selected from the group consisting of cubic posts, cylindrical posts, rectangular posts, prismatic, pyramidal, truncated pyramidal, conical, truncated conical, cross, hemispherical and combinations thereof.
- 25. The method of claim 1, wherein said three-dimensional structures comprise a pyramidal form having sides of varying slope relative to the base of the pyramid.
- 26. The method of claim 1, wherein substantially all of said structures have substantially the same shape and dimensions.
- 27. The method of claim 1, wherein said three-dimensional structures are located on a polishing element, said article further comprising:a) a resilient element; and b) a rigid element disposed between said polishing element and said resilient element.
- 28. The method of claim 27, wherein said rigid element is bonded to said polishing element and said resilient element.
- 29. The method of claim 1, wherein said method comprises planarizing a metal surface of a wafer suited for fabrication of semiconductor devices.
- 30. The method of claim 29, wherein said metal comprises copper.
- 31. The method of claim 1, wherein said method comprises planarizing a dielectric surface of a wafer suited for fabrication of semiconductor devices.
- 32. The method of claim 1, wherein said method is substantially free of audible vibration.
- 33. The method of claim 1, wherein said method is conducted in the absence of inorganic abrasive particles.
- 34. The method of claim 1, wherein said polishing composition comprises abrasive particles.
- 35. The method of claim 1, wherein said polishing composition is essentially free of abrasive particles.
- 36. The method of claim 1, wherein said three-dimensional structures comprise elongated prismatic structures.
- 37. The method of claim 1, wherein said three-dimensional structures comprise elongated ridges.
- 38. The method of claim 1, further comprising removing at least about 500 Angstroms of material/minute from the surface of a plurality of wafers for a period of at least about 200 minutes.
- 39. The method of claim 1, further comprising removing at least about 500 Angstroms of material/minute from at least one wafer and providing wafers having no greater than about 10% wafer non-uniformity.
- 40. A method of chemically modifying a wafer suited for fabrication of semiconductor devices, said method comprising:a) contacting a surface of the wafer with an article comprising a plurality of unit cells repeating across the surface of said article, the individual unit cells comprising at least a portion of a three-dimensional structure, said three-dimensional structure being essentially free of inorganic abrasive particles, said unit cell being characterized by a unit cell parameter as follows: [[V1−Vs]/Aas]/Auc>1 where V1 is the volume defined by the area of said unit cell and the height of said structure of said unit cell, Vs is the volume of said structure of said unit cell, Aas is the apparent contact area of said structure, and Auc is the area of said unit cell; and b) moving at least one of the wafer and said article relative to each other in the presence of a polishing composition, said polishing composition being chemically reactive with the surface of the wafer and being capable of either enhancing or inhibiting the rate of removal of at least a portion of the surface of the wafer.
- 41. The method of claim 40, wherein [[V1−Vs]/Aas]/Auc≧5.
- 42. The method of claim 40, wherein [[V1−Vs]/Aas]/Auc≧10.
CROSS REFERENCE TO RELATED APPLICATIONS
This application is a divisional of U.S. Ser. No. 09/756,376, filed Jan. 8, 2001, now U.S. Pat. No. 6,612,815 the disclosure of which is herein incorporated by reference.
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Non-Patent Literature Citations (2)
Entry |
Trice et al., “3M Slurry-Free Copper CMP Polishing System”, Presentation given at CAMP 4th Annual International Symposium on Chemical-Mechanical Polishing, Aug. 8-11, 1999. |
Trice et al., “3M Slurry-Free Copper CMP Polishing System”, Presentation given at CAMP 4th Annual International Symposium on Chemical-Mechanical Polishing, Aug. 9-11, 1999. |