Patent Grant
8337282
This application is the U.S. National Phase under 35 U.S.C. §371 of International Application No. PCT/JP2007/066980, filed on Aug. 31, 2007, which in turn claims the benefit of Japanese Application No. 2006-241265, filed on Sep. 6, 2006, the disclosures of which Applications are incorporated by reference herein.
The present invention relates to a polishing pad which is used for polishing an object to be polished, such as a silicon wafer, in a manufacturing process of a semiconductor device or the like.
As a process for flattening a semiconductor wafer such as a silicon wafer is conventionally adopted a chemical mechanical polishing (CMP) process (for example, see the Patent Document 1).
According to the CMP process, a polishing pad is retained on a machine platen and an object to be polished, such as a silicon wafer, is retained on a polishing head, and the polishing pad and the object to be polished, which are being pressurized, are slid over each other while slurry is continuously supplied thereto so that the object is polished.
As a semiconductor device is increasingly highly integrated, demand for a higher level of flattening of an object to be polished increasingly grows. Therefore, various approaches have been so far made to satisfy such demand. For example, grooves are formed on the surface of a polishing pad so that slurry can be homogeneously supplied into between the polishing pad and the object to be polished or an average surface roughness Ra of the surface of a polishing pad is improved. These approaches, however, are not as effective as expected. When a large wafer is polished, in particular, it is not easy to achieve a higher level of flatness overall.
Further, when a polishing pad is used, it is conventionally necessary, as a means of improving poshing performance, to roughen the surface of the polishing pad in a dressing process using a disk containing diamond abrasive grains, such process being called break-in (startup) in general, in an initial stage in which the polishing pad is attached to a polishing device and the polishing device is then activated. In order to improve the productivity of semiconductor wafers, it is desirable to reduce an amount of time required for break-in.
Therefore, a main object of the present invention is to improve qualities of an object to be polished by improving the flatness of the object, and to reduce break-in time.
The inventors of the present invention tackled various challenges in order to achieve the foregoing object, and found out that the improvement of waviness on a surface of a polishing pad effectively led to the improvement of the flatness of an object to be polished and completed the present invention.
The waviness denotes unevenness whose dimension is in the range of 20 mm-200 mm and whose amplitude is in the range of 10 μm-200 μm.
A polishing pad according to the present invention is a polishing pad used for polishing an object to be polished, comprising a polishing surface pressed onto the object to be polished, wherein waviness on the polishing surface has a dimension in the range of 5 mm-200 mm and a largest amplitude of 40 μm or less.
According to the present invention, since the waviness on the polishing surface pressed onto the object to be polished is reduced, influences of the waviness on the polishing surface exerted on the object to be polished is lessened. As a result, the flatness of the object to be polished can be improved.
A polishing pad according to the present invention is a polishing pad used for polishing an object to be polished, comprising a polishing surface pressed onto the object to be polished, wherein a zeta potential of the polishing surface measured with a use of a neutral solution is equal to or above −50 mV and less than 0 mV.
According to the present invention, the minus zeta potential of the polishing surface of the polishing pad is equal to or above −50 mV and less than 0 mV, which is closer to zero than a zeta potential of a polishing surface of a conventional polishing pad. Therefore, repulsion against abrasive particles of slurry is controlled, and a fit between the slurry and the polishing surface of the polishing pad becomes better. As a result, the break-in time can be reduced, and the productivity can be improved.
In a preferred embodiment of the present invention, an average surface roughness Ra of the polishing surface may be equal to or above 1 μm and equal to or below 5 μm.
In another preferred embodiment of the present invention, an underground layer may be provided below a polishing layer comprising the polishing surface so that suitable cushioning characteristics can be provided by the underground layer.
According to the present invention, since the waviness on the polishing surface to be pressed onto the object to be polished is reduced, the flatness of the object to be polished can be improved.
Further, the minus zeta potential of the polishing surface of the polishing pad is closer to zero comparing to the zeta potential of the polishing surface of the conventional polishing pad. Accordingly, the repulsion against the minus abrasive particles of the slurry is controlled, and a fit between the slurry and the polishing surface of the polishing pad becomes better. As a result, the break-in time can be reduced, and the productivity can be improved.
Hereinafter, preferred embodiments of the present invention are described in detail referring to the drawings.
A polishing pad 1 according to the present preferred embodiment can be obtained when foamable resin, such as polyurethane, is foamed and then cured. The polishing pad may not necessarily have foamable structure and may have a non-foamable structure. Further, a non-woven fabric pad may also be used.
In the present preferred embodiment, in order to improve the flatness of an object to be polished such as a silicon wafer, the entire area of a polishing surface 1a to be pressed onto the object to be polished is buffed so that waviness on the polishing surface 1a is lessened.
When the polishing surface 1a is thus buffed, a largest amplitude of the waviness in a dimension of 5 mm-200 mm on the polishing surface 1a is reduced to be 40 μm or less. The largest amplitude is preferably as small as possible.
The method of reducing the waviness on the polishing surface is not limited to a buffing process and the polishing surface may be milled or pressed.
Hereinafter, preferred embodiments of the present invention are described.
In a embodiment 1 of the present invention and a conventional example, an MH-type polishing pad manufactured by Nitta Haas Incorporated, which is a foamable urethane pad having relatively large foaming diameters suitable for polishing silicon, was used.
In the drawing, a horizontal axis denotes positions on the polishing surface of the polishing pad, and Line L1 denotes the embodiment 1 and Line L2 denotes the conventional example 1. The waviness on the polishing surface was measured by a measurement device HSS-1700 manufactured by Hitachi Zosen Corporation.
In the case of the polishing pad according to the conventional example 1, the surface of which was not buffed, a sharp rise is shown as illustrated in Line 2, the polishing surface has a lot of waviness, and the largest amplitude thereof exceeds 40 μm. In contrast, the polishing pad according to the embodiment 1 shows a modest rise as illustrated in Line 1, and it is learnt that the polishing surface has less waviness, and the largest amplitude is reduced to be 40 μm or less.
Each of the polishing pads according to the embodiment 1 and the conventional example 1 was used to polish both surfaces of a silicon wafer of 300 mm under the following conditions, and the flatness of the silicon wafer and a polishing rate were evaluated.
The number of rotations of an upper machine platen was 20 rpm, the number of rotations of a lower machine platen was 15 rpm, an applied pressure was 100/cm2, silica slurry at 25° C. was used, and a volumetric flow of the slurry was 2.5 L/min.
Table 1 shows the GBIR (Global Back Ideal Range), SFQR (Site Front Least Squares Range), roll off and polishing rate of the polished silicon wafer. In the table, respective average values obtained in a polishing test for five silicon wafers are shown.
As shown in Table 1, the flatness represented by the GBIR and SFQR of the silicon wafers polished by the polishing pad according to the embodiment 1 was improved in comparison to that achieved by the polishing pad according to the conventional example 1, and the roll off and the polishing rate were also improved.
The silicon wafers were measured by a laser measuring device, which was NANOMETRO 200TT manufactured by KURODA Precision Industries Ltd.
It can be confirmed that a central portion, rather than a peripheral portion, of the silicon wafer was polished by the polishing pad according to the conventional example 1 as illustrated in
As described, when the polishing pad according to the embodiment 1 capable of reducing the waviness on the polishing surface is used, the flatness of the silicon wafer can be improved, and the roll off and the polishing rate can also be improved.
The polishing rate of the polishing pad according to the embodiment 1 was kept high with stability from the first round of the polishing process, while the polishing rate of the polishing pad according to the conventional example 1 was stable from the second round of the polishing process.
As is learnt from
It is necessary for the frictional force to be constant in order to obtain a constant polishing rate. It takes 60 seconds for the constant frictional force to be obtained in the polishing pad according to the embodiment 1, while 150 seconds are necessary in the polishing pad according to the conventional example 1. It can be learnt therefore that the startup time of the polishing process in the polishing pad according to the embodiment 1 is shorter than that in the polishing pad according to the conventional example 1.
Table 2 is measurement results showing values of an average surface roughness Ra of the polishing surfaces of the polishing pads according to the embodiment 1 and the conventional example 1 measured by a real-time scan laser microscope 1LM21D manufactured by Lazertec Co., Ltd. Table 2 shows measurement results obtained from five points in the region of 45 μm×45 μm, and respective average values thereof.
As illustrated in Table 2, the average surface roughness Ra of the polishing surface according to the embodiment 1 which was buffed is larger than that of the conventional example 1. Therefore, the break-in time necessary for the polishing rate to be increased and then leveled off can be reduced in comparison to the conventional example 1 as described earlier.
An MH-type polishing pad was used in the embodiment 1 and the conventional example 1. In a embodiment 2 (2-1 and 2-2) and a conventional example 2, an IC-type polishing pad, which is a foamable urethane pad having relatively small foaming diameters manufactured by Nitta Haas Incorporated, was used.
For the embodiment 2, a embodiment 2=1 in which a polishing surface of the IC-type polishing pad was buffed by sand paper of count #100 and a embodiment 2-2 in which the polishing surface was buffed by sand paper of count #240 finer than #100 were prepared, and they are compared to the conventional example 2 in which the polishing surface was not buffed.
In a manner similar to the foregoing embodiment, it was confirmed that the waviness on the polishing surfaces of the polishing pads according to the embodiments 2-1 and 2-2 was less, and the largest amplitudes were also reduced to be 40 μm or less in comparison to the polishing pad according to the conventional example 2, according to measurement results obtained by the measurement device HSS-1700 manufactured by Hitachi Zosen Corporation.
Then, values of the average surface roughness Ra of the polishing surfaces of the polishing pads according to the embodiments 2-1 and 2-2 and the conventional example 2 were measured by the real-time scan laser microscope 1LM21D manufactured by Lazertec Co., Ltd.
Table 3 shows results of the measurement. In Table 3, the measurement results obtained from five points in the region of 18 μm×18 μm and respective average values thereof are shown.
As illustrated in Table 3, the average surface roughness Ra is larger on the polishing surfaces, which were buffed, according to the embodiments 2-1 and 2-2 in comparison to the polishing surface according to the conventional example 2. Therefore, the reduction of the break-in time necessary for the polishing rate to be increased and then leveled off can be expected.
In order to reduce the break-in time, the average surface roughness Ra of the polishing surface is preferably equal to or above 1 μm, and more preferably 1 μm-5 μm. The average surface roughness more than 5 μm, which may result in the generation of scratches, is not suitable.
Next, zeta potentials of the polishing surfaces of the polishing pads according to the embodiments 2-1 and 2-2 and the conventional example 2, and the zeta potential of the polishing surface of the polishing pad according to the conventional example 2 subjected to break-in were measured by a zeta potential/particle diameter measuring system ELS-Z2 manufactured by OTSUKA ELECTRONICS CO., LTD. according to the laser Doppler method (dynamic/cataphoretic light diffusion method) in which 10 mM of a neutral NaCl solution was used.
Table 4 shows results of the measurement.
As shown in Table 4, average values of the zeta potentials of the polishing surfaces of the polishing pads according to the embodiments 2-1 and 2-2 were −9.18 mV, and −12.38 mV, respectively, while an average value of the zeta potentials of the polishing surface of the polishing pad according to the conventional example 2 was −133.16 mV. Thus, the values obtained from the embodiments 2-1 and 2-2 were closer to 0 mV comparing to the conventional example 2.
As described, the minus zeta potentials of the polishing surfaces of the polishing pads according to the embodiments 2-1 and 2-2 were closer to 0 mV in comparison to the zeta potential of the polishing surface in the conventional example 2. Therefore, the repulsion against the minus abrasive particles of the slurry is controlled, and a fit between the slurry and the polishing surface of the polishing pad becomes better. As a result, the reduction in the break-in time can be expected.
The values obtained from the embodiments 2-1 and 2-2 were closer to zero than −32.89 mV which was the zeta potential average value of the polishing surface of the polishing pad according to the conventional example 2 subjected to break-in. This demonstrates that it is unnecessary in the embodiments 2-1 and 2-2 to perform such break-in as is required in the conventional technology.
In order to reduce the break-in time, the zeta potential of the polishing surface of the polishing pad is preferably equal to or above −50 mV and less than 0 mV.
Next, a silicon wafer with an 8-inch TEOS film attached thereto was polished by the polishing pads according to the embodiment 2-1 and the conventional example 2 and the polishing pad according to the conventional example 2 subjected to break-in under the following conditions, and the polishing rates thereby obtained were evaluated.
The number of rotations of the upper machine platen was 60 rpm, the number of rotations of the lower machine platen was 41 rpm, the applied pressure was 48 kPa, slurry ILD3225 manufactured by Nitta Haas Incorporated was used, and the volumetric flow of the slurry was 100 mL/min. The silicon wafer was polished for 60 seconds, and the 60-second polishing was repeatedly implemented with a 30-second dressing process interposed therebetween.
s shows a result of the polishing process.
In the polishing pad according to the embodiment 2-1 shown by ▴, the polishing rate is higher and leveled off sooner in comparison to the polishing pad according to the conventional example 2 shown by ●. Further, the polishing pad according to the embodiment 2-1 was substantially the same as the polishing pad according to the conventional example 2 subjected to break-in shown by □ in terms of a polishing rate and stability.
In other words, the embodiment 2-1 in which break-in was omitted demonstrates the characteristics similar to those of the conventional example 2 subjected to break-in. Therefore, it can be learnt that such break-in as is required in the conventional example 2 is unnecessary for the polishing pad according to the embodiment 2-1.
The flatness of the silicon wafers which were polished by the polishing pads according to the embodiments 2-1 and 2-2 and the conventional example 2 was evaluated in a manner similar to the embodiment 1. As a result, the silicon wafers polished by the polishing pads according to the embodiments 2-1 and 2-2 with no break-in showed the GBIR and SFQR representing the flatness which were equal to or better than those of the silicon wafer polished by the polishing pad according to the conventional example 2 subjected to break-in.
In the preferred embodiments described so far, the polishing pad has a single-layer structure; however, may have a multilayer structure comprising a ground layer 2, which is made up of a non-woven cloth impregnated with urethane or soft foam, as a lower layer as illustrated in
The present invention is useful when a semiconductor wafer, such as a silicon wafer, is polished.
| Number | Date | Country | Kind |
|---|---|---|---|
| P2006-241265 | Sep 2006 | JP | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP2007/066980 | 8/31/2007 | WO | 00 | 6/17/2009 |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2008/029725 | 3/13/2008 | WO | A |
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