Patent Application
20070111403
The present invention relates generally to semiconductor devices and, more particularly, to an electrically programmable polycide fuse having improved reliability and programming speed.
Data storage devices and memories may be classified into two types: volatile and non-volatile. Whereas power must be provided to a volatile memory to maintain its stored information, a non-volatile memory may be powered down yet still retain the stored information. Examples of non-volatile memory include Electrically Erasable Programmable Read Only Memory (EEPROM) and flash. Although these non-volatile memories have proven to be very popular because they retain data without requiring power, they are generally incompatible with conventional Complementary Metal Oxide Semiconductor (CMOS) processing techniques.
This incompatibility introduces a problem in that CMOS is a dominant technology used in the manufacture of a vast number of integrated circuits. Should an integrated circuit require non-volatile storage, additional process steps besides the CMOS process steps already implemented to manufacture the remaining components will be necessary. Such additional process steps introduce substantial cost. To avoid this cost, polycide fuses compatible with CMOS technology have been developed to implement a non-volatile memory. In contrast to EEPROM and flash, a polycide fuse memory is a one time programmable (OTP) memory in that once a fuse is programmed, it cannot be re-programmed. Each polycide fuse is manufactured in a non-programmed state. To program a polycide fuse, current is passed through the fuse until at least the silicide layer in the polycide fuse becomes open circuited (producing a “blown” fuse). To read a polycide fuse memory, the resistance of each fuse is compared to a threshold resistance. If the fuse has a resistance above the threshold resistance (which may have a value of, for example, 10K Ω), the fuse is judged to be programmed. On the other hand, if the fuse has a resistance below the threshold resistance, the fuse is judged to be not programmed.
As circuit dimensions continue to shrink for CMOS technology, the available power supply voltage levels also decrease to avoid damaging circuit components. For example, it is conventional to have CMOS circuitry that cannot tolerate voltages greater than 3.3 V. Indeed, CMOS circuitry has been developed that cannot tolerate voltages greater than 2.5 V. Such relatively-low voltage levels in turn reduce the available current than can be forced through a polycide fuse so that it can be programmed. It is thus conventional to require as much as 200 μs to program a polycide fuse, thereby leading to undesirable delays in programming substantial numbers of such fuses.
Another problem with conventional polycide fuses is reliability. A polycide fuse needs to be reliable in both the programmed and non-programmed states. To be reliable in the non-programmed state, a polycide fuse should consistently have a resistance below the threshold resistance. Conversely, a reliable programmed fuse should consistently have a resistance above the threshold resistance. However, the shrinking dimensions of modern CMOS processes have affected polycide fuse reliability in both the non-programmed and programmed states. In particular, it has been found that commonly-used deposition techniques for making polycide fuses produce a silicon nitride layer having a relatively high hydrogen concentration. It is known that hydrogen contained within deposited silicon nitride may diffuse into adjacent structures and compromise device reliability. For example, plasma-enhanced-chemical-vapor-deposition (PECVD) is widely known to produce silicon nitride having such relatively high hydrogen concentrations. Although increasing PECVD deposition temperature reduces the hydrogen concentration, operation of PECVD above 480° C. is problematic. Another commonly-performed silicon nitride deposition technique, low-pressure-chemical-vapor-deposition (LPCVD), can be performed at much higher temperatures such as 800° C., thereby largely removing free hydrogen from the deposited silicon nitride. However, the use of LPCVD places relatively large stresses on the deposited silicon nitride and underlying structures in the polycide fuse. As a result, it is conventional to produce polycide fuses with silicon nitride layers having relatively high concentrations of hydrogen.
Accordingly, there is need in the art for a polycide fuse having improved reliability and reduced programming time.
In accordance with an embodiment of the invention, a polycide fuse includes: a polysilicon layer; a silicide layer formed on the polysilicon layer; and a silicon nitride layer formed on the silicide layer, the silicon nitride layer having a relatively low hydrogen concentration and a relatively low mechanical stress.
In accordance with another embodiment of the invention, a method of manufacturing a polycide fuse includes the acts of: forming a polysilicon layer; forming a silicide layer on the polysilicon layer; and forming a silicon nitride layer on the silicide layer using RTCVD.
In accordance with another embodiment of the invention, a polycide fuse includes: a polysilicon layer; a silicide layer formed on the polysilicon layer; and a silicon nitride layer formed on the silicide layer by RTCVD, the silicon nitride layer thereby having a relatively low hydrogen concentration and a relatively low mechanical stress, wherein the polycide fuse includes a cathode, an anode, and a fuse neck joining the cathode and the anode, the fuse neck having a length of at least one micron.
The scope of the invention is defined by the claims, which are incorporated into this section by reference. A more complete understanding of embodiments of the present invention will be afforded to those skilled in the art, as well as a realization of additional advantages thereof, by a consideration of the following detailed description of one or more embodiments. Reference will be made to the appended sheets of drawings that will first be described briefly.
Embodiments of the present invention and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.
Reference will now be made in detail to one or more embodiments of the invention. While the invention will be described with respect to these embodiments, it should be understood that the invention is not limited to any particular embodiment. On the contrary, the invention includes alternatives, modifications, and equivalents as may come within the spirit and scope of the appended claims. Furthermore, in the following description, numerous specific details are set forth to provide a thorough understanding of the invention. The invention may be practiced without some or all of these specific details. In other instances, well-known structures and principles of operation have not been described in detail to avoid obscuring the invention.
Turning now to the drawings,
A cross-sectional view of polycide fuse 100 is illustrated in
Referring back to
The programming process may be better understood with reference to
Turning now to
Programming speed may be significantly increased (and programming time thus reduced) by adapting polycide fuse 100 such that the transient programming current is largely confined to silicide layer 210 (
It will be appreciated that the manufacture of polycide fuse 100 is entirely compatible with conventional CMOS processing techniques such as the CS100 A process such that no additional processing steps are necessary besides those already being performed to manufacture the remaining components. However, as discussed above, conventional silicon nitride deposition techniques produce silicon nitride layers having relatively high concentrations of hydrogen that adversely affect polycide fuse reliability. In embodiments of the present invention, silicon nitride layer 215 (
In one embodiment, the RTCVD process deposits silicon nitride layer 215 at a temperature of about 500° C. to about 650° C. Those skilled in the art will appreciate that the deposition of silicon nitride in an RTCVD system can be carried out in a single-wafer deposition process in a relatively short period of time. Since the RTCVD process is carried out on a single wafer, the temperature to which the substrate is subjected can be controlled to minimize hydrogen incorporation into the silicon nitride material. Further, the precise temperature control also permits silicon nitride layer 215 to be deposited with a relatively low film stress. The relatively low deposition temperature avoids undesirable diffusion of impurities previously introduced into the underlying layers within polycide fuse 100. Further, previously formed alloys, such as silicide layer 210 are not degraded during the RTCVD process. Additional details of suitable RTCVD processes are disclosed in U.S. patent application Ser. No. 11/013,240, filed Dec. 14, 2004, the contents of which are incorporated by reference in their entirety.
Advantageously, embodiments of polycide fuse 100 may be incorporated into other devices such as, for example, programmable logic devices to form OTP memories. Turning now to
Embodiments described above illustrate but do not limit the invention. For example, although various features have been described with reference to particular materials and doping, it will be appreciated that other implementations are also contemplated by the present disclosure. It should also be understood that numerous modifications and variations are possible in accordance with the principles of the present invention. Moreover, no limitations from the specification are intended to be read into any claims unless those limitations are expressly included in the claims. Accordingly, the scope of the invention is defined by the following claims.
