Claims
- 1. A method for reducing the size of microsteps on an epitaxial layer deposited on a polished semiconductor wafer substrate, the method comprising:providing a semiconductor wafer; depositing an epitaxial layer on a surface of said semiconductor wafer, wherein during the deposition of the epitaxial layer, microsteps are formed on an exposed surface of said epitaxial layer; forming a boundary interface within said deposited epitaxial layer by thermal oxidizing at least a portion of the epitaxial layer of said semiconductor wafer including at least a portion of said exposed surface defining said microsteps, wherein said boundary interface being defined as an interface between said oxidized portion of said epitaxial layer and a portion of said epitaxial layer not oxidized, said boundary interface being relatively smoother than said exposed surface of said deposited epitaxial layer; and removing said microsteps by substantially removing the oxidized top portion of said epitaxial layer, wherein said relatively smoother boundary interface is exposed as a surface of said epitaxial layer.
CROSS REFERENCES TO RELATED APPLICATIONS
The present application is a divisional and claims priority from non-provisional U.S. patent application entitled, “POST-EPITAXIAL THERMAL OXIDATION,” having application Ser. No. 09/233,253, and filed on Jan. 19, 1999, now U.S. Pat. No. 6,372,521 is assigned to the present invention.
This application relies on U.S. Provisional Patent Application No. 60/072,046, entitled “Post Expitaxial Thermal Oxidation,” filed Jan. 21, 1998.
US Referenced Citations (1)
Number |
Name |
Date |
Kind |
4615762 |
Jastrzebski et al. |
Oct 1986 |
A |
Provisional Applications (1)
|
Number |
Date |
Country |
|
60/072046 |
Jan 1998 |
US |