Claims
- 1. A method for reducing the size of microsteps on an epitaxial layer deposited on a polished semiconductor wafer substrate, the method comprising:providing a semiconductor wafer; depositing an epitaxial layer on a surface of said semiconductor wafer, wherein during the deposition of the epitaxial layer microsteps are formed on an exposed surface of said epitaxial layer; oxidizing at least a portion of the epitaxial layer of said semiconductor to a subsurface depth below said microsteps on said exposed surface of said epitaxial layer; and removing said microsteps by substantially removing the oxidized portion of said epitaxial layer to the subsurface depth below said microsetps on said exposed surface of said epitaxial layer.
CROSS REFERENCES TO RELATED APPLICATIONS
The present application is a continuation of and claims priority from non-provisional application Ser. No. 10/114,899 filed Apr. 2, 2002 now U.S. Pat. No. 6,482,659 issued Nov. 19, 2002 which is a divisional of application Ser. No. 09/233,253 filed Jan. 19, 1999 now U.S. Pat. No. 6,372,521 issued Apr. 16, 2002 which claims benefit of provisional U.S. Patent Application No. 60/072,046 filed on Jan. 21, 1998.
US Referenced Citations (3)
Number |
Name |
Date |
Kind |
4615762 |
Jastrzebski et al. |
Oct 1986 |
A |
6240933 |
Bergman |
Jun 2001 |
B1 |
6312968 |
Shimabukuro et al. |
Nov 2001 |
B1 |
Provisional Applications (1)
|
Number |
Date |
Country |
|
60/072046 |
Jan 1998 |
US |
Continuations (1)
|
Number |
Date |
Country |
Parent |
10/114899 |
Apr 2002 |
US |
Child |
10/222112 |
|
US |