Patent Application
20150035580
The present description relates to a switching output stage with improved efficiency and electromagnetic radiation characteristics.
As it is known, power stages operating in switching mode are quickly replacing the so-called “linear” systems by virtue of their higher efficiency. The most common cases of electronic devices operating based on “switching” techniques are voltage adjusters and audio power amplifiers.
The need is increasingly felt by users, to have switching devices having reduced dimensions with regards to the dissipating devices and the output inductances. This involves the manufacturers producing devices that reduce the dissipated power and increase the switching frequency.
For the characteristics of the switching devices, these requirements are conflicting, since, as the switching frequency increases, the losses due to the switching also increase, thus the efficiency of the same device is reduced.
Another point to be considered relates to the electromagnetic radiation of the device, which generally increases as the switching speed increases, i.e., as the switching frequency increases.
Particularly, also with reference to
It is further noticed that the second conduction terminal MHs of the first electronic switch MH is connected to the first conduction terminal MLd of the second electronic switch ML, and both are connected to an output terminal Vout.
Such switches MH, MI are turned on and off alternately by the corresponding drivers DRV1, DRV2 connecting the output Vout to the supply terminal Vdd or the ground terminal GND.
Particularly, in the example of
The typical waveforms of such output stages are illustrated in
As it is noticed, the power dissipation, for each type of current Iout, occurs both by conduction (zones A, B, and C) and by switching (zones D and E).
It is worth pointing out that the conduction losses (zones A, B, and C) are due to the voltage drop at the ends of the two power MOS transistors multiplied by the current Iout.
On the other hand, the switching losses (zones D and E) are given by the product of the voltage at the ends of the power MOS transistors for the current flowing therein during the transition into an output voltage from GND to Vdd.
While neglecting the “dead zones”, where both power MOS transistors are turned off, although there are losses due to the current flowing in the intrinsic diode that there is between the drain terminal and the source terminal, the conduction losses (zones A, B, and C) are independent from the switching frequency, since they only depend on the Rds(on) of the power MOS transistors.
Instead, the switching losses (zones D and E) are directly proportional to the switching frequency, and decrease as the rising and descending time of the output waveform decreases.
The parasitic elements that are associated with the package may be one of the main obstacles to reaching high efficiencies at high frequencies. For example, in the traditional packages, an example of which is illustrated in
These values are such that both the conduction losses (caused by the total series resistance Rds(on) of the half bridge illustrated in
The presence of the inductance L1, L2 forces not particularly high variations of the current in the switches of the half bridge with respect to time (i.e., in the formula di/dt).
This depends on the fact that the voltage at the ends of the bonding inductance is related to the variation upon time of the current by the formula: VL=L*di/dt, where L is the value of the parasitic bonding inductance and VL is the voltage at the ends of the same bonding inductance caused by the current variation, the voltage that would be developed at the ends of the parasitic inductances, thus at the ends of the power transistors acting as switches of the half bridge. Such voltage at the ends of the bonding inductance VL may exceed the specifications for the component in the case of a high (di/dt).
Furthermore, these peaks may also cause malfunctions of other parts of the device.
The consequences of the structures that serve to decrease the factor di/dt are rise and descent times of the output waveform such that the switching losses at frequencies above some hundred kHz become the prevailing ones.
In order to minimize the power dissipated by switching, the so-called “resonating”, “almost resonating” or “soft switching” switching systems exist, in which, by a further resonating LC cell besides the one that is generally present in the output filter, the transistors MH and ML of the half bridges are turned on only when the voltage at the ends thereof or the current flowing therein is null.
Generally, the circuits are more complex than those of a simple bridge, since they require additional inductances and, sometimes, converters. Furthermore, with the switching circuits of a resonating type, it is complex to have good fidelity of the PWM command in a power output.
Recently, various packages were proposed, that minimize the parasitic elements of the traditional packages. Particularly, for power devices, the so-called packages having a low parasitic inductance are indicated, particularly as regards the leads or bonding wires, such as, for example, a WLP package, which is the acronym for Wafer-Level package, or a CSP package, which is the acronym for Chip-Scale package.
Particularly, the WLP package, also with reference to
This scheme, besides reducing the parasitic resistance to values below one milliohm, reduces the parasitic inductance by a factor of about 100, from 5 nH to less than 50 pH.
The drawback of this WLP package is related to the difficulty or impossibility of dissipating the power through a true dissipater, at least in low cost systems.
In this case the heatsink is the printed circuit board on which the chip is attached. It is estimated that a WLP with 200 balls on a 2s2p circuit with standard dimensions jdec have a Rthj-a of about 20 degrees/W.
However, it has to be pointed out that, in devices with supply voltage and output currents exceeding a preset value, also considering a complete zeroing of the parasitics, the power dissipated by switching and the current peaks in standard devices of the half-bridge type, although they are driven so as to have very fast switching fronts, do not allow dissipating the power only by exploiting the printed board. Furthermore, they may make it very difficult to limit the electromagnetic emissions.
For example, consider the circuit of
In this configuration, the switching losses are due to only the load of the transistor ML.
The current output by the supply generator Vdd as a function of the output current, from 0.1 A to 6.1 A is illustrated in
In this step, the output current flows in the recirculation diode dMH of transistor MH. In order to make it so that the Vout returns to zero, the transistor ML first discharges the charge built up in this recirculation diode dMH, which then, throughout this period, is similar to a short at the supply voltage Vdd. Again in this period, on the transistor ML the supply voltage Vdd falls, plus the direct voltage of the diode dMH. Since the current levels reached in this step may reach values of about 70 A (
An object is to reduce or minimize this pulse, thus improving both the efficiency and the electromagnetic radiation performance.
Furthermore, another object is to increase the efficiency by reducing the switching losses, while reducing the electromagnetic radiation by virtue of the significant reduction of the current peaks involved.
Other objects, features and advantages are provided by a power electronic device including first and second electronic switches, each integrated on a package having a low parasitic inductance, a supply terminal and a ground terminal. The first conduction terminal of the first switch may be coupled with the supply terminal, and the second conduction terminal of the second electronic switch may be coupled with the ground terminal. The corresponding control terminals of the switches may be coupled to corresponding pilot drivers. The package may include first and second electric terminals, wherein the second conduction terminal of the first switch is coupled to the first electric terminal, and the first conduction terminal of the second switch is coupled to the second electric terminal. A first inductance may be interposed between the first electric terminal and the output terminal and/or a second inductance interposed between the second electric terminal and the output terminal.
The characteristics and advantages of the present disclosure will be apparent from the following detailed description of a possible practical embodiment, which is illustrated by way of non-limiting example in the set of drawings, in which:
Although it is not explicitly pointed out, the single characteristics described with reference to the specific embodiments shall be meant as accessory and/or interchangeable with other characteristics, described with reference to other implementation examples.
In the following, for the sake of description simplicity, elements already described with reference to the prior art will be indicated with the same reference number.
The present description will be explained by considering the current Iout as an incoming current in the power electronic device even if the same objects may be achieved with currents Iout exiting the power electronic devices.
Referring now to
The WLP or CSP type package is known; therefore, it will not be further described. To the aims of the present description, it is worth noticing that the WLP or CSP type package has a supply terminal Vdd (for example, equal to 10V) and a ground terminal GND.
Particularly, the first and the second electronic switches MH, ML each have a first and a second conduction terminals MHd, MLd and MHs, MLs and a command or control terminal MHg, MLg.
As it is noticed from
Particularly, the WLP or CSP type package comprises first and second electric terminals T1, T2, in which the second conduction terminal MHs of the first electronic switch MH is connected to the first electric terminal T1 and the first conduction terminal MLd of the second electronic switch ML is connected to the second electric terminal T2.
It is worth noticing that the first and the second electric terminals T1, T2 are mutually connected to an output terminal Vout.
Advantageously, the electronic device 1′ comprises a first inductance L1′ interposed between the first electric terminal T1 and the output terminal Vout.
According to a feature of the electronic device 1′, it comprises a second inductance L2′ interposed between the second electric terminal T2 and the output terminal Vout.
Preferably, the electronic device 1′ comprises both the first inductance L1′, interposed between the first electric terminal T1 and the output terminal Vout, and the second inductance L2′ interposed between the second electric terminal T2 and the output terminal Vout.
Preferably, the value of the first inductance L1′ is equal to the value of the second inductance L2′.
Advantageously, the inductances L1′, L2′ are much higher than the parasitic inductances present in series at the Vdd and GND terminals.
Particularly, such inductances L1′, L2′ are implemented in values equal for example to 5 nH.
It is worth noticing that the first and the second inductances L1′, L2′ may be present or arranged externally or internally to the WLP type package.
In other terms, the first and the second inductances L1′, L2′ may be integrated in the power device 1′, or implemented externally to the package on which the same power device is implemented.
In an embodiment, the first electronic switch MH and the second electronic switch ML are both implemented in an N-channel power transistor.
Therefore, the power electronic device 1′ represents a switching output power stage.
Such N-channel power transistors MH and ML are connected in accordance with the half-bridge scheme, where the first electronic switch MH represents the high side of the output stage, and the second electronic switch ML represents the low side of the output stage.
Particularly, the first conduction terminal MHd, MLd of the two transistors is implemented in the drain terminal of the transistor, the second conduction terminal MHs, MLs is implemented in the source terminal of the two transistors, and the command terminal MHg, MLg is implemented in the gate terminal of the two transistors.
In
In the following description, reference will be made only to the embodiment in which both the first inductance L1′ and the second inductance L2′ are implemented, always considering that the behavior of the electronic device 1 in the case that only one inductance L1′ or L2′ is implemented are similar.
The addition of these inductances L1′ and L2′ makes it so that, when the transistor ML is activated, the Vds thereof drops to potentials that are near to zero before the drain current starts rising, since all the supply voltage will drop at the inductance ends.
This allows avoiding the peak of dissipated power on ML, and avoiding the very steep current peak, which will rise by following a preset slope given by di/dt=V/L, where i is the current in the inductance L1′ and L2′, L represents the value of such inductances, and V is the voltage at the ends of the above-mentioned inductances L1′ and L2′.
With reference to
In such
From the simulation of
Therefore, by virtue of the insertion of at least one inductance L1′ or L2′, preferably both, a reduction of the amplitude and the slope of the current pulse due to the recirculation diode dMH of the MOS transistor of the high side, i.e., of the switch MH is achieved.
The maintenance of the current peak at 35 A in the embodiment of the electronic power device 1′ illustrated with reference to
In order to limit such a voltage spike, and with reference to
Such at least one resistive member R1′, R2′ turns out to be connected between the second conduction terminal MHd of the first electronic switch MH and the first conduction terminal MLd of the second electronic switch ML.
Preferably, two resistive members R1′ and R2′ are implemented, which are arranged mutually in series, and connected between the second conduction terminal MHd of the first electronic switch MH and the first conduction terminal MLd of the second electronic switch ML.
Such resistive members R1′ and R2′ act as damping resistances.
Particularly, the resistive members R1′ and R2′ are preferably arranged inside the WLP or CSP package, i.e., integrated in the electronic device 1″, so as to have negligible parasitic inductances.
In an alternative embodiment, the common point of the resistive members R1′ and R2′ may be connected to the common point of the two inductances L1′, L2′. However, the latter approach is generally more complex, since it requires, in the case that L1′ and L2′ are outside the package, a further connection between the inside and the outside of the chip itself.
For example, the values of R1′ and R2′ may be of the order of a few Ohms.
The presence of the resistances R1′ and R2′ involves an efficiency reduction for the device, which is consistent with that of the prior art circuit as illustrated in
However, it is known from U.S. Pat. No. 7,332,943, by the name of the same Applicant of the present application, and incorporated in its entirety herein by reference, that the addition of a non-null voltage Vgs at the high side MH of the half-bridge switching output stage, in the devices 1′ and 1″ of
Such operation is described with reference to
The drawback in inserting the voltage generator V(off) is the output resistance of the pilot generator Rd of the gate-source voltage that, to avoid restarting operations of MH, caused by the high dv/dt of the output voltage and the parasitic capacitance Cgd, has to be very small, for example, below 1 Ohm.
This also depends on the fact that the capacitance Cgd, during the descent transient of the output voltage of the transistor MH from the supply voltage value Vdd to zero, is charged with the current that is provided essentially by the driving circuit, i.e., the driver V(off).
The voltage drop on the output resistance Rd of this circuit may increase the voltage Voff at the output terminal to values higher than the threshold values Vth of the transistor, causing the cross-conduction pulses between MH and MI.
In
Furthermore, it is worth noticing that, also with such value of Rd equal to 0.1 ohm, a certain contribution to the voltage spike due to spurious re-starting is present as shown in
In fact, in
Independently from the embodiments of the power electronic device illustrated in
Particularly, such compensation circuit 2 comprises: capacitive means or capacitor 3 dimensioned as a function of a parasitic capacitance existing between the command terminal MHg and the first conduction terminal MHd of the first electronic switch MH, i.e., the parasitic capacitance Cgd set forth above. The circuit 2 may also include an electronic switch MR having a command terminal MCg and a first and second conduction terminals MRd, MRs.
In particular, the capacitive means or capacitor 3 is connected with the command terminal MCg of the electronic switch MR in order to activate it, so that the current circulating in electronic switch MR compensates the current circulating in the parasitic capacitance Cgd during the descent transient of the output voltage Vout, present at the output terminal, from the value of the voltage present at the supply terminal Vdd to the value of the voltage at the ground terminal GND.
It is worth noticing that between the command terminal MRg of the electronic switch MR and the second conduction terminal MRs of such electronic switch MR, a resistance Rr is present. Such resistance Rr acts as an anti-leakage device, i.e., it avoids “floating” of the command terminal MRg of the MOS MR. This scenario is to be avoided, because the MOS MR could turn on also under undesired conditions. The resistance Rr imposes the minimum current in Cgd(ref) so that the MOS MR turns on, equal to Vgs(thresholdMr)/Rr.
Particularly, according to a preferred embodiment, the capacitive means or capacitor 3 are proportional to the parasitic capacitance Cgd of the first switch MH and are implemented in a capacitance Cgd(ref) or in a N-type channel MOS transistor, as exemplified in
Particularly, according to a preferred embodiment, the electronic switch MC is implemented in an N-type channel power transistor.
It is worth noticing that the capacitance Cgd(ref) is proportional to the parasitic capacitance Cgd of the high side of the output stage (transistor MH) and it is dimensioned so it is able to turn the N-type channel power transistor on with which the electronic switch MR is implemented.
By operating in such a manner, it is possible to compensate the gate current, since, if the drain current MR actuated by the current circulating in the capacitance Cgd(ref) is higher than or equal to the current circulating in the parasitic capacity Cgd, then the voltage Vgs of the transistor MH remains constant or decreases, avoiding the cross-conduction current pulse.
The result of inserting the compensation circuit 2 is illustrated in the simulation of
As it is noticed, the compensation caused by such compensation circuit 2 is noticeable, since the peak current is below 10 A; however, a time offset exists before such compensation circuit 2 actually intervenes. Such offset may be assessed on the order of ten nanoseconds, and in the specific case of
Referring now to
Advantageously, according to a characteristic aspect of the present description, to the power device 1″ described with reference to
Such power device 1″″ allows obtaining that on the capacitive means Cgd(ref) also the voltage present at the ends of the inductances L1′ and L2′ falls, therefore obtaining an anticipation of the intervention of the drain current of MR so as to practically nullify the cross-conduction pulse, by making it almost independent from the value of the resistance Rd.
The result of introducing the compensation circuit 2 in the electronic device 1″ is illustrated in the simulations of
Referring now to
Referring now to the
As it is noticed, the reduction of the amplitudes of the harmonics with respect to the standard case 1 is apparent. In the critical zone around 100 MHz (which is the frequency modulation transmission band) is about a minimum of 5 dB for the case of the device 1″ and it is higher than 10 dB for the case of the device 1″″.
Instead, referring now to
Particularly, the comparison was performed with respect to the dissipation due only to the Rds(on) of the transistor ML and a device described with respect to
Referring now to
In general, the compensation circuit 2 will be able to be implemented only on the high side of the output stage of the electronic device 1″″ (i.e., transistor MH), only on the low side of the output stage of the electronic device 1″″ (i.e., transistor ML), or on both the power transistors according to the fact that the output current Iout can be only incoming, only exiting, or it can take both polarities.
Furthermore, it is worth noticing that both the electronic device 1″″ described with reference to
Typically, the P-type channel power MOS transistor is used for implementing the switch MH because it has the advantage of not requiring a driving of the gate that has to exceed the supply voltage Vdd, as it has instead to be done in the case that the switch MH is implemented with an N-type channel power MOS transistor.
In the latter case, also with reference to
It is worth noticing that the electronic device 1″″ described with reference to
It shall apparent that those of ordinary skill in the art, in order to meet contingent, specific needs, will be able to make a number of modifications and variations described above, all of which anyhow falling within the protection scope as defined by the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| MI2013A001283 | Jul 2013 | IT | national |
