Patent Application
20080234953
In various semiconductor applications, it is becoming advantageous to be able to monitor the amount of power that a chip (or portion of a chip) is consuming. For example, in some applications, maximum power consumption requirements may be imposed but at the same time, it may be desirable to operate as close as possible to such maximum requirements in order to achieve improved performance. Existing power consumption monitoring (and/or estimation) approaches involve measuring voltages and/or currents and then calculating power consumption, but unfortunately, such approaches can be relatively costly, e.g., in terms of circuit or manufacturing resources to implement them. Accordingly, a novel approach for monitoring power consumption is desired.
Embodiments of the invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements.
As taught herein, the basic idea of this disclosure is that integrated circuit junction temperature (Tj) can be used to estimate the chip's power dissipation. It is generally known that:
T
j(hot)=Ψj−c·P+Tcase.
Tj(hot) is the temperature (in ° C.) of a hot portion (e.g., hottest or reasonably approaching the hottest) portion in an operating semiconductor device; Ψj−c is the thermal resistance, from junction-to-case, for the semiconductor device; P is the consumed power of the device; and Tcase is the temperature of the semiconductor case. (As used herein, the case corresponds to the exterior of the semiconductor chip, typically, one or more surfaces used to conduct heat away from the chip. For example, it could correspond to the temperature of a heat spreader thermally mounted to a chip.)
It has been observed, especially for relatively large chips such as multi-core processor chips, that the case temperature (Tcase) is typically reasonably proximal to “cool” areas within an operating chip. Thus, with the equation above, Tj(cool) can be substituted for Tcase. Thus, with this substitution, P can be derived as:
P≈(Tj(hot)−Tj(cool))/Ψj−c.
With reference to
The semiconductor chip 102 has a temperature sensor circuit 106 for determining a relatively cool temperature of the chip and a temperature sensor circuit 108 for determining a relatively hot temperature of the chip. It also has logic (not shown) to receive signals from the sensors to calculate an estimated power, consumed by the chip, using the above approximation. (Note that in some embodiments, it may not be necessary to actually divide by a thermal resistance. that is, the thermal resistance is a constant, so the hot/cool temperature difference could be used, e.g., to control or limit power consumption, without having to calculate an actual power value.)
Any suitable temperature sensing circuit may be used to implement sensors 106 or 108. There are varieties of different types of temperature sensing circuits known to persons of skill in the art. For example, suitable temperature sensing circuits and schemes are shown in U.S. Pat. App. Publ. No. 20060265174 to Doyle et al., entitled “THERMAL SENSING FOR INTEGRATED CIRCUITS” and incorporated by reference herein.
Logic (not shown) for processing temperature sensor signals and determining a power estimate using the above formula may be implemented with any suitable circuitry within the chip. For example, it could be performed with firmware instructions in an on-board controller, or it could be performed with dedicated circuitry such as circuit components to implement a finite state machine.
The sensors 106, 108 may be located in any areas of the chip sufficient for achieving acceptably accurate power consumption estimations. For example, as shown in the figure, the hot sensor 108 is located relatively centrally, e.g., within a processor's core, where operating temperature may be the highest. In contrast, the cool sensor is located in an outer area of the chip, which may be the coolest part of the chip and reasonably close to the temperature of the heat spreader 104. It should be appreciated, however, that the hottest or coolest locations are not required for estimating power, but in some embodiments, they may yield the most accurate results.
(Along these lines, it should be appreciated that as used herein, the terms “hot” and “cool” are relative terms and should not be limited to any specific range of temperatures. They are used to indicate a relationship between temperatures, e.g., a hot temperature is higher than a cool temperature and vice versa. For example, a reading of 100° C. could be “cool” in comparison with other higher temperatures. by the same token, 20° C. could be “hot” in comparison with other cooler temperatures.)
In some embodiments, junction-to-case thermal resistance (Ψj−c) may be used for the power estimation. This may be convenient in that it may already be available. Alternatively, a different thermal resistance value, particularly corresponding to the thermal gradient between the hot and cool temperature sensors, could be used. It could be determined through characterization using a sufficient number of chips with actual power consumption being measured so that a Ψh−c for the chip type can be obtained.
Depending on the type of chip, its application, and complexity, the estimated power may be used for a variety of purposes. In some embodiments, it may be accurate enough to actually control how hard a chip is driven in order to operate it at (or close to) its maximum rated power. In other applications, it may be used as a secondary power monitoring scheme, e.g., as a failsafe, in addition to another more accurate scheme. In other applications, it could, for example, be used in cooperation with a power conservation mode in a mobile device.
The cores are relatively centrally located with the cache 304 located in outer areas of the chip. As seen in the figure, the cool sensors 306 are located near the outer corners, away from the cores and closer to the cache, which typically have the cooler portions of the chip. Conversely, the hot sensors 308 are located in the cores, which typically have the hotter areas of the chip.
The utilized Ψ could be a single thermal resistance for the chip (e.g., a junction-to-case Ψ or a different, specifically characterized point-to-point Ψ within the chip). Alternatively, it could be selected from a group of thermal resistance values Ψ characterized for each hot sensor to cool sensor gradient combination.
It should be noted that the depicted system could be implemented in different forms. That is, it could be implemented in a single chip module, a circuit board, or a chassis having multiple circuit boards. Similarly, it could constitute one or more complete computers or alternatively, it could constitute a component useful within a computing system.
The invention is not limited to the embodiments described, but can be practiced with modification and alteration within the spirit and scope of the appended claims. For example, it should be appreciated that the present invention is applicable for use with all types of semiconductor integrated circuit (“IC”) chips. Examples of these IC chips include but are not limited to processors, controllers, chip set components, programmable logic arrays (PLA), memory chips, network chips, and the like.
Moreover, it should be appreciated that example sizes/models/values/ranges may have been given, although the present invention is not limited to the same. As manufacturing techniques (e.g., photolithography) mature over time, it is expected that devices of smaller size could be manufactured. In addition, well known power/ground connections to IC chips and other components may or may not be shown within the figures for simplicity of illustration and discussion, and so as not to obscure the invention. Further, arrangements may be shown in block diagram form in order to avoid obscuring the invention, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present invention is to be implemented, i.e., such specifics should be well within purview of one skilled in the art. Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the invention, it should be apparent to one skilled in the art that the invention can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.
