Patent Application
20100103759
This application claims priority to Chinese Patent Application No. 200810201786.8, filed Oct. 24, 2008, commonly assigned, incorporated by reference herein for all purposes.
The present invention is directed to integrated circuits and their processing for the manufacture of semiconductor devices. More particularly, the invention provides a method and device for selectively lowering power supply voltage to an SRAM memory array. Merely by way of example, the invention has been applied to SRAM devices for providing low power consumption while maintaining high memory speed. But it would be recognized that the invention has a much broader range of applicability. For example, the invention can be applied to other embedded or stand-alone integrated circuits memories, such as DRAM and non-volatile memories.
Integrated circuits or “ICs” have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Current ICs provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of ICs. Semiconductor devices are now being fabricated with features less than a quarter of a micron across.
Increasing circuit density has not only improved the complexity and performance of ICs but has also provided lower cost parts to the consumer. An IC fabrication facility can cost hundreds of millions, or even billions, of dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of ICs on it. Therefore, by making the individual devices of an IC smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Making devices smaller is very challenging, as each process used in IC fabrication has a limit. That is to say, a given process typically only works down to a certain feature size, and then either the process or the device layout needs to be changed. An example of such a limit is that memory cell standby current has become an major contributor to overall integrated circuits power consumption.
Fabrication of custom integrated circuits using chip foundry services has evolved over the years. Fabless chip companies often design the custom integrated circuits. Such custom integrated circuits require a set of custom masks commonly called “reticles” to be manufactured. A chip foundry company called Semiconductor International Manufacturing Company (SMIC) of Shanghai, China is an example of a chip company that performs foundry services. Although fabless chip companies and foundry services have increased through the years, many limitations still exist. For example, as logic devices are scaled and designed to operate under lower voltages, memory device leakage current makes it difficult to reduce overall device power consumption. Memory devices such as static random access memory (SRAM) consume substantial power in many integrated circuits applications. For example, the increasing demand for portable applications has made power consumption one of the most important design parameters. Many of these portable applications require a power efficient SRAM. These and other limitations will be discussed further below.
From the above, it is seen that an improved technique for designing semiconductor devices is desired.
According to the present invention, techniques directed to integrated circuits and their processing are provided for the manufacture of semiconductor devices. More particularly, the invention provides a method and device for selectively lowering power supply voltage to an SRAM memory array. Merely by way of example, the invention has been applied to SRAM devices for providing low power consumption while maintaining high memory speed. But it would be recognized that the invention has a much broader range of applicability. For example, the invention can be applied to other embedded or stand-alone integrated circuits memories, such as DRAM and non-volatile memories.
According to an embodiment of the invention, a method for providing a voltage supply in an integrated circuit memory device includes providing an integrated circuit memory device which includes a first plurality of memory cells. Each of the first plurality of memory cells includes a power terminal and a ground terminal. The method includes providing a first power voltage which is associated with a power supply. The method also provides a second power voltage which is lower than the first power voltage in magnitude. The method includes selecting a second plurality of memory cells from the first plurality of memory cells. The first plurality of memory cells includes the second plurality of memory cells and a third plurality of memory cells. The third plurality of memory cells are unselected. The method provides the first power voltage to the power terminal of each of the second plurality of memory cells. The method provides the second power voltage, which is lower than the first power voltage in magnitude, to the power terminal of each of the third plurality of memory cells. The method then performs at least a read operation and/or a write operation to at least one of the second plurality of memory cells.
In a specific embodiment of the invention, the method includes providing a first ground voltage and a second ground voltage. The second ground voltage is higher than the first ground voltage. The method then supplies the first ground voltage to the ground terminal of each of the selected memory cells, and supplies the second ground voltage to the ground terminal of each of the unselected memory cells. In an embodiment, each of the memory cells is an SRAM memory cell. In a specific embodiment, each of the memory cells includes a first and second cross-coupled branches. Each branch further includes a load device and a drive transistor connected in series. In an embodiment, the power terminal of each memory cell is electrically connected to the load device and the ground terminal is electrically connected to the drive transistor. In a specific embodiment, the load device is a PMOS transistor and the drive transistor is an NMOS transistor. In another embodiment, the load device is an NMOS transistor and the drive transistor is an NMOS transistor. In yet another embodiment, the load device is a resistor and the drive transistor is an NMOS transistor. In a specific embodiment, the first power voltage is about 1.2 volts. In an embodiment, the second power voltage is about 0.9 volts. In certain embodiments, the first ground voltage is about 0 volts. In some embodiments, the second ground voltage is about 0.3 volts. In a specific embodiment, providing the second power voltage further includes providing a level-shifting transistor and lowering the first power voltage by approximately a threshold voltage of the level-shifting transistor. In some embodiments, providing the second power voltage further includes providing a source follower circuit. In an embodiment, selecting the second plurality of memory cells further includes providing a word line in the memory device, and selecting the memory cells coupled to the word line. In an embodiment, selecting the second plurality of memory cells further includes providing a plurality of word line in the memory device, each word line being coupled to at least a memory cell, and providing a word line pre-decoder for selecting a second plurality of word lines. The method then selects the memory cells coupled to the second plurality of word lines. In a specific embodiment, the second plurality of word lines includes four word lines.
According to another embodiment of the invention, a method for providing voltage supply in a memory device includes providing an integrated circuit memory device comprising a first plurality of memory cells. Each memory cell includes a power terminal and a ground terminal. The method provides a first ground voltage and a second ground voltage which higher than the first ground voltage in magnitude. The method selects a second plurality of memory cells from the first plurality of memory cells. The first plurality of memory cells includes the second plurality of memory cells and a third plurality of memory cells which are unselected. The method provides the first ground voltage to the ground terminal of each of the second plurality of memory cells and the second ground voltage to the ground terminal of each of the third plurality of memory cells. The second ground voltage being higher than the first ground voltage in magnitude. The method then performs at least a read operation and/or a write operation to at least one of the second plurality of memory cells.
In an alternative embodiment of the invention, an integrated circuit memory device is provided. The memory device includes a first plurality of memory cells. Each memory cell includes a power terminal. The memory device includes a decoding circuit for at least selecting a second plurality of memory cells from the first plurality of memory cells and providing an output signal. The first plurality of memory cells includes the second plurality of memory cells and a third plurality of memory cells. The third plurality of memory cells are not selected by the decoding circuit. The memory device includes a switch circuit for supplying a first power voltage to the power terminal of each of the second plurality of memory cells and supplying a second power voltage to the power terminal of each of the third plurality of memory cells in response to the output signal of the decoding circuit. The first power voltage is provided by a first power supply. The second power voltage is provided by a second power supply. The second power voltage is lower than the first power voltage in magnitude.
In a specific embodiment, each of the first plurality of memory cells further includes a ground terminal, and he memory device also includes a second switch circuit for supplying a first ground voltage to the ground terminal of each of the second plurality of memory cells and supplying a second ground voltage to the ground terminal of each of the third plurality of memory cells in response to the output signal of the decoding circuit. The first ground voltage is provided by a third power supply. The second ground voltage is provided by a fourth power supply. The second ground voltage is higher than the first ground voltage in magnitude. In an embodiment, each of the memory cells is an SRAM memory cell. In some embodiments, each of the memory cells comprises a first and second cross-coupled branches. Each branch further includes a load device and a drive transistor connected in series. In certain embodiments, the power terminal of each memory cell is electrically connected to the load devices and the ground terminal is electrically connected to the drive transistors. In a specific embodiment, the load device is a PMOS transistor and the drive transistor is an NMOS transistor. In another embodiment, the load device is an NMOS transistor and the drive transistor is an NMOS transistor. In yet another embodiment, the load device is a resistor and the drive transistor is an NMOS transistor. In a specific embodiment, the first power voltage is about 1.2 volts. In an embodiment, the second power voltage is about 0.9 volts. In certain embodiments, the first ground voltage is about 0 volts. In some embodiments, the second ground voltage is about 0.3 volts. In a specific embodiment, the second power supply further includes a level-shifting transistor for lowering the first power voltage by about a threshold voltage of the level-shifting transistor. In some embodiments, the second power supply further includes a source follower circuit. In a specific embodiment, the memory device also includes a first plurality of word lines, each of the word lines being coupled to at least a memory cell. The device includes an input circuit for receiving an address signal. The decoding circuit selects a second plurality of word lines from the first plurality of word lines in response to the address signal. In an embodiment, the second plurality of word lines includes one word line. In another embodiment, the second plurality of word lines includes four word lines.
Numerous benefits are achieved using one or more features of the present invention. In a specific embodiment, the present invention can provide an SRAM array having reduced standby current by lowering the power supply voltage of inactive cells. In certain embodiments, the invention can provide full power supply to active memory cells to maintain operating speed of the memory array. Certain embodiments of the invention achieve simple design and low cost implementation by, for example, using existing decoding signals for selective power line supply. Depending upon the specific embodiment, the invention also provides a method that is implemented using conventional circuit design methodology and process technology. Depending upon the embodiments, one or more of these benefits may be achieved. These and other benefits are described throughout the present specification and more particularly below.
According to the present invention, techniques directed to integrated circuits and their processing are provided for the manufacture of semiconductor devices. More particularly, the invention provides a method and device for selectively lowering power supply voltage to an SRAM memory array. Merely by way of example, the invention has been applied to SRAM devices for providing low power consumption while maintaining high memory speed. But it would be recognized that the invention has a much broader range of applicability. For example, the invention can be applied to other embedded or stand-alone integrated circuits memories, such as DRAM and non-volatile memories.
Depending upon the embodiment, the present invention includes various features, which may be used. These features include the following:
1. Reduce SRAM array standby current by lowering the power supply voltage of inactive cells;
2. Supply full power supply to active memory cells to maintain operating speed of the memory array; and
3. Achieve simple design and low cost implementation by, for example, using existing address decoding signals for selecting power supply lines.
As shown, the above features may be in one or more of the embodiments to follow. These features are merely examples, which should not unduly limit the scope of the claims herein. One of ordinary skill in the art would recognize many variations, modifications, and alternatives. For example, certain embodiments discussed below refer to an SRAM memory array. However, one of ordinary skill in the art would recognize that the invention can be applied to other integrated circuit memory devices, such as DRAM, non-volatile memory devices, and read-only memory (ROM) devices, etc.
In a specific embodiment, SRAM devices with an array size of 4 mega bits have been designed using a 0.13 um process. Merely as an example, an SRAM device is configured as 8 banks, with each bank having 512K bits. In a particular embodiment, a bank is internally organized in 1024 rows and 512 columns. In an embodiment, a single memory cell can have a standby current of 10 pA when the cell VDD voltage is 1.2V. A whole array containing 4M cells can consume a total standby current of about 40 mA. If the VDD is reduced to 0.9 volts, the cell current for a single memory cell can be reduced to about 0.01 pA. The standby current for the whole array can be reduced to about 40 uA. In this particular example, the power consumption using the lower power supply can be reduced to about 0.1% of the power consumption at the higher voltage supply. However, according to an embodiment, if the power supply to an entire SRAM memory array is reduced, the speed of the memory device can be degraded. According to an embodiment of the present invention, techniques are provided for selectively reducing power supply to inactive memory cells to reduce power consumption, while continuing full power supply in selected memory cells to maintain memory speed performance. Of course, one of ordinary skill in the art would recognize other variations, modifications, and alternatives.
In a specific embodiment, a memory device is designed with a power supply of 1.2 volts. The memory device can include a transistor having a threshold voltage Vt of, for example, 0.3 volts. In an embodiment, a lower power supply voltage of 0.9 volts can be obtained, for example, by using a voltage shifting circuit that produces an output voltage of 0.9 volts from an input voltage of 1.2 volts. In a specific embodiment, the voltage shifting circuit can be a source follower circuit including an NMOS transistor having a threshold voltage of 0.3 volts. With 1.2 volts applied at its gate terminal, a source terminal of the NMOS transistor is about 0.9 volts, approximately a Vt drop below the gate voltage. In alternative embodiment, other voltage shifting circuit can be used to generate a lower output voltage from a higher input voltage. Of course, one of ordinary skill in the art would recognize other variations, modifications, and alternatives.
In a specific embodiment, SRAM cell 400 is a CMOS SRAM cell including PMOS load devices 401 and 402 and NMOS drive devices 403 and 404. In some embodiments, the load devices can be NMOS transistors. In other embodiment, the load devices can be resistors. In alternative embodiments, the drive devices 402 and 404 can be PMOS transistors. Dependent upon the embodiments, memory cell 400 can be a DRAM cell, a non-volatile memory cell, or a read-only memory (ROM) cell. Memory cell 400 can be a memory cell in a stand alone integrated circuit memory or an embedded memory. Of course, there can be other variations, modifications, and alternatives.
In a particular example, the ground terminals 803 and 804 of memory cell 800 are connected to a ground voltage supply VSS1=VSS+Vt, when memory cell 800 is unselected. A ground voltage supply voltage of VSS is applied to the ground terminals 803 and 804, when memory cell 800 is selected. As shown, the power terminals 801 and 802 of memory cell 800 are connected to a power voltage supply VDD1=VDD−Vt, when memory cell 800 is unselected. A power voltage supply voltage of VDD is applied to the ground terminals 801 and 802, when memory cell 800 is selected. The standby current of memory cell 800 is reduced. Of course, there can be other variations, modifications, and alternatives.
In a specific embodiment, decode circuit 900 combines predecoded signals F, PXA,
PXB, and PXC to select one word line WL associated with one of 1024 rows. As shown in
Referring to
1. (Step 1110) Provide an integrated circuit memory device. The integrated circuit memory device includes a first plurality of memory cells. Preferably, each of the first plurality of memory cells include a power terminal and a ground terminal;
2. (Step 1120) Provide first power voltage supply. The first power voltage is associated with a power supply;
3. (Step 1130) Provide a second supply voltage lower than the first supply voltage;
4. (Step 1140) Apply the second supply voltage to the memory array;
5. (Step 1150) Select a second plurality of memory cells from the first plurality of memory cells. Preferably, the second plurality of memory cells includes a smaller number of memory cells than the first plurality of memory cells;
6. (Step 1160) Apply the first supply voltage to the power terminal of each of the selected memory cells to maintain an operating speed of the selected memory cells;
7. (Step 1170) Perform an memory operation to the selected memory cells; and
8. (Step 1180) Apply the second power voltage to the power terminal of each of the unselected memory cells, whereby power consumption in the unselected memory cells is reduced.
The above sequence of steps provides a method for providing voltage supply to an integrated circuit memory device according to an embodiment of the present invention. As shown, the method uses a combination of steps including a way of selectively lowering power supply voltage to unselected cells in a memory array while maintaining full power supply to the selected memory cells. Merely by way of example, the invention has been applied to SRAM devices for providing low power consumption while maintaining high memory speed. Other alternatives can also be provided where steps are added, one or more steps are removed, or one or more steps are provided in a different sequence without departing from the scope of the claims herein.
It is also understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application and scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 200810201786.8 | Oct 2008 | CN | national |
