Patent Application
20230299137
The present disclosure relates to a power semiconductor device. More particularly, but not exclusively, the present disclosure relates to a trench-gate power semiconductor device with an insulation trench.
Power semiconductor devices (such as, insulated-gate bipolar transistors (IGBTs)) have been widely used as power switches in a variety of power applications. Important operating parameters of IGBTs typically include the on-state voltage drop between the collector and the emitter (VCE,sat), the switching loss (Esw), and the safe operating area (SOA). VCE,sat and Esw indicate the efficiency of an IGBT while SOA indicates the reliability of an IGBT.
Generally speaking, there are two common types of IGBT structures. One type is called a planar-gate IGBT in which a gate electrode is provided on a surface of a wafer. The other type is called a trench-gate IGBT in which a trench structure is formed in a wafer and a gate electrode is buried in the trench structure. The trench-gate IGBT has a MOS channel which is vertical to the wafer surface, and the vertical MOS channel effectively eliminates a JFET effect in the planar gate structure. Concurrently, as the MOS channel density is not limited by the chip surface area, the channel density can be improved greatly. In this way, as compared to the planar-gate IGBT, the trench-gate IGBT can provide an increased channel density and accordingly a reduced on-state voltage drop VCE,sat. However, the trench-gate IGBT has a worse short-circuit current capability or a poorer short-circuit SOA (SCSOA) due to its high saturation collector current density. Therefore, in the latest trench gate technology, dummy regions have been adopted to optimize the trade-off performance between VCE,sat and SCSOA without sacrificing the reverse blocking voltage.
The dummy regions (which include dummy trenches as well as dummy wells between the dummy trenches) introduce additional parasitic capacitance and more space to store free electron-hole carriers which need to be removed or flood in when the device is turned off or turned on. It has been reported that the dummy trenches could be electrically connected to the active gate electrodes of the trench-gate IGBT, but this type of connections would result in large switching loss due to increased gate-collector capacitance (CGC). It is also known that the dummy trenches may be electrically connected to the emitter electrode of the IGBT, but this type of connections would increase the turn-on switching speed (represented by the rate of change of the collector current, di/dt) and may result in uncontrollable di/dt through changing a gate resistor Rg,on.
Therefore, it is often required to trade off one operating parameter of an IGBT for the improvement of another operating parameter of the IGBT. Similar problems exist for other types of power semiconductor devices.
It is generally desirable to provide a power semiconductor device which has an improved device efficiency as well as an improved reliability.
It is an object of the present disclosure, among others, to provide an improved power semiconductor device which solves the problems associated with known structures, whether identified herein or otherwise.
According to a first aspect of the present disclosure, there is provided a power semiconductor device, comprising:
As compared to prior designs of power semiconductor devices (e.g., IGBTs) which provide a dummy semiconductor region to neighbour an active cell, using the insulation trench of the first aspect to replace at least a part of the dummy semiconductor region is advantageous for improving the SOA and the switching controllability, and reducing the switching loss and the EMI noise of the power semiconductor device, while providing a similar level of current density. The length L1 of the active cell and the length L2 of the insulation trench follow the design rule of 0.5 ≤ L2/L1 ≤ 2, which is useful for keeping uniform electric field distribution on the chip front side (thereby improving the reliability of the device) and for maintaining process uniformity and controllability. L2/L1 refers to a ratio of the second length L2 and the first length L1.
Preferably, the first and second lengths L1 and L2 may further satisfy the relationship of L2/L1 ≤ 1.7. More preferably, the first and second lengths L1 and L2 may further satisfy the relationship of L2/L1 ≤ 1.5. By making L2/L1 not greater than 2, preferably not greater than 1.7, and most preferably not greater than 1.5, the electric field under the insulation trench may be prevented from reaching an excessive level when the device is reversely biased, thereby protecting the device from breaking down.
Preferably, the first and second lengths L1 and L2 may further satisfy the relationship of L2/L1 ≥ 1. By making L2/L1 not lower than 0.5, more preferably not lower than 1, the risk of the device suffering from a high short circuit current is reduced, thereby allowing the device to have an acceptance SCSOA performance.
The emitter region may be selectively provided at the first side of the semiconductor substrate.
The active cell may further comprise a first implant zone provided between the active base region and the drift layer, wherein the first implant zone is of the second conductivity type and has a higher doping concentration than the drift layer.
Advantageously, the first implant zone improves the conductivity modulation in the power semiconductor device by enhancing the carrier profile in the drift layer during the on state, thereby reducing VCE,sat of the power semiconductor device.
The active gate trench may be configured to extend through the base layer and the first implant zone into the drift layer.
The insulation trench may be filled exclusively with the dielectric material.
In other words, the insulation trench is not filled with any semiconducting or electrically conducting material. The dielectric material may comprise more than one type of dielectric material.
The insulation trench may be configured to extend from the surface of the semiconductor substrate at the first side into the drift layer.
The insulation trench and the active gate trench may have substantially the same depth along the first direction.
The power semiconductor device may further comprise an emitter electrode which is electrically connected to the emitter region of the active cell and a collector electrode which is electrically connected to collector layer.
The active cell may further comprise a second implant zone between the active gate trench and the drift layer, the second implant zone having the first conductivity type.
Advantageously, the second implant zone shields the bottom of the active gate trench from the bombing holes injected by the collector layer during an on state of the power semiconductor device, and accordingly, protects the active gate trench from trapping holes bombing from the collector layer. As a result, the second implant zone improves the reliability of the power semiconductor device. Further, the second implant zone provides better blocking capability for the power semiconductor device.
The second implant zone between the active gate trench and the drift layer may be of a floating potential, i.e., not electrically connected to any electrode of the power semiconductor device.
The second implant zone may also be provided between the insulation trench and the drift layer.
Advantageously, the second implant zone between the insulation trench and the drift layer provides better blocking capability for the power semiconductor device.
The second implant zone between the insulation trench and the drift layer may be electrically connected to the emitter electrode.
The second direction may be parallel to the surface of the semiconductor substrate. The active cell may be configured to provide at least one current channel during an on-state of the power semiconductor device. It would be appreciated that the active cell refers to a minimum repeating unit that is able to conduct current in a whole power semiconductor device.
The active cell may further comprise a dummy base region which is a part of the base layer, and wherein the active base region and the dummy base region are provided at opposite sides of the active gate trench, such that the active cell provides a single current channel during the on-state of the power semiconductor device.
It would be appreciated that the single current channel is provided by the active base region during the on-state of the power semiconductor device, and that the dummy base region does not have any emitter region therein.
The first implant zone may also be provided between the dummy base region and the drift layer.
The dummy base region of the active cell may be of a floating potential or may be electrically connected to the emitter electrode.
The active cell may be configured to provide two current channels located at opposite sides of the active gate trench during the on-state of the power semiconductor device. The active gate trench may be provided in the middle of the active cell along the second direction.
The power semiconductor device may comprise a plurality of the active cells and a plurality of the insulation trenches.
The active cells and the insulation trenches may be arranged along the second direction. Each active cell may be provided immediately between two of the insulation trenches along the second direction
A single one of the insulation trenches may be provided immediately between neighbouring ones of the active cells.
The expression “immediately between” means that there is no other structure between neighbouring ones of the active cells. In other words, the distance between the neighbouring ones of the active cells along the second direction is the second length L2 of the insulation trench.
The power semiconductor device may further comprise a dummy cell. The dummy cell may comprise a dummy base region which is a part of the base layer.
It would be appreciated that the dummy cell does not provide any current channel during an on-state of the power semiconductor device.
The dummy cell may further comprise a dummy gate trench which comprises a gate insulator and a dummy gate electrode disposed therein.
The dummy gate electrode and the dummy base region of the dummy cell may be electrically connected to the emitter electrode. Alternatively, the dummy gate electrode may be electrically connected to the active gate electrode.
The active gate electrode and the dummy gate electrode may be made of polysilicon. A length of the dummy cell along the second direction may be equal to the first length L1.
The dummy gate trench may have the same dimension as the active gate trench.
The dummy gate trench may be provided in the middle of the dummy cell along the second direction.
The first implant zone may also be provided within the dummy cell between the dummy base region and the drift layer.
The second implant zone may also be provided within the dummy cell between the dummy gate trench and the drift layer.
The power semiconductor device may comprise a plurality of the dummy cells. At least one of the dummy cells and at least two of the insulation trenches may be provided between neighbouring ones of the active cells along the second direction. The insulation trenches may be provided between a dummy cell and an active cell, or between two dummy cells, along the second direction.
The power semiconductor device may further comprise a buffer layer having the second conductivity type, wherein the buffer layer is provided between the drift layer and the collector layer, and has a higher doping concentration than the drift layer. Advantageously, the buffer layer is useful for reducing the on-state voltage drop VCE,sat of the power semiconductor device.
The power semiconductor device may comprise an insulated-gate bipolar transistor (IGBT).
According to a second aspect of the present disclosure, there is provided a method of manufacturing a power semiconductor device, the method comprising:
Where appropriate any of the optional features described above in relation to the first aspect of the present disclosure may be applied to the second aspect of the disclosure. It would be appreciated that the various ranges of L2/L1 described above allow for a degree of variability, for example, ±10%, in the stated values of the end points of the ranges. For instance, a stated limit of 2 may be any number between 2∗(1-10%), and 2∗(1+10%). Further, values expressed in a range format should be interpreted in a flexible manner to include not only the numerical values explicitly recited as the end points of the range, but also to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited.
In order that the disclosure may be more fully understood, a number of embodiments of the present disclosure will now be described, by way of example, with reference to the accompanying drawings, in which:
In the figures, like parts are denoted by like reference numerals.
It will be appreciated that the drawings are for illustration purposes only and are not drawn to scale.
Hereafter, referring to the attached drawings, a detailed description will be given of preferred embodiments of a power semiconductor device according to the disclosure. A layer or region being prefixed by N or P in the description and attached drawings means that electrons or holes respectively are majority carriers. Also, ‘+’ or ‘-’ added to N or P indicates a higher impurity concentration or lower impurity concentration respectively than in a layer or region to which ‘+’ or ‘-’ is not added. Doping regions of the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different ‘N’ doping regions may have the same or different absolute doping concentrations. In the following descriptions and attached drawings, the same reference signs are given to the same configurations, and redundant descriptions are omitted.
A plurality of active cells 15 and a plurality of insulation trenches 17 are formed within the semiconductor substrate 2. As shown in
The active cells 15 are designed to have identical dimensions and configurations. With the expression “active cell”, it is meant that the cell would provide at least one current channel during an on-state of the IGBT 1. Each active cell 15 comprises an active gate trench 9. Each active gate trench 9 comprises a gate insulator 11 which for example may be a thin layer of oxide film, and an active gate electrode 10 which for example may be made of polysilicon. The expressions “active gate electrode” and “active gate trench” mean that the gate electrode within the gate trench is a control electrode, which controls the on/off of the current channel(s) of the active cell 15.
Each active gate trench 9 is in a stripe form extending from the first surface 16 through the P type base layer 5 into the N- drift layer 4. The extending direction of the active gate trenches 9 is along a Y axis. The Y axis is generally perpendicular to the X axis. The active gate trenches 9 of the plurality of active cells 15 are aligned in the X axis. The Y axis may also be referred to as the “first direction” or the depth direction of the substrate 2, and the X axis may also be referred to as the “second direction” or the lateral direction of the substrate 2.
The base layer 5 is divided by the insulation trenches 17 and the active gate trenches 9 into a plurality of P type active base regions 5-i. Each active cell 15 further comprises two of the P type active base regions 5-i which are located at opposite sides of the respective active gate trench 9. The P type active base regions 5-i may also be referred to as active P wells.
As further shown in
Each active cell 15 further comprises an N+ type emitter region 7 which is selectively provided within a respective active base region 5-i adjacent to the first surface 16 of the substrate 2. In the example of
Each of the insulation trenches 17 is filled with a dielectric material. The dielectric material may also be referred to as an electrically insulating material. An example of the dielectric material is silicon dioxide. Preferably, each of the insulation trenches 17 is filled exclusively with a dielectric material, i.e., not filled with any semiconducting or electrically conducting material. The dielectric material within each insulation trench 17 may comprise more than one type of dielectric material. The insulation trenches 17 also extend from the first surface 16 through the P type base layer 5 into the N- drift layer 4. The extending direction of the insulation trenches 17 is along a Y axis. The insulation trenches 17 have substantially the same depth as the active gate trenches 9 along the Y axis.
The IGBT 1 further comprises a collector electrode 19 which is electrically connected to the P+ type collector layer 3, an emitter electrode 21 which is electrically connected to each emitter region 7. The emitter electrode 21 may include a barrier layer made of titanium nitride, tantalum nitride, titanium or tantalum by way of example. A main layer of the emitter electrode 21 may be made of, for example, tungsten or tungsten-based metals, aluminium, copper, or alloys of aluminium and copper. The collector electrode 19 may comprise aluminium, copper, alloys of aluminium or copper, or multiple layers of metals, e.g. Al/Ti/Ni/Ag or Al/Ni/Ag, etc. Although the electrical connections among the active gate electrodes 10 are not explicitly shown in the cross-sectional perspective provided by
An interlay dielectric 23 covers an upper portion of the active cells 15. Therefore, the interlay dielectric 23 electrically isolates the active gate electrodes 10 from the emitter electrode 21. The emitter electrode 21 includes vertical connectors 22 which extend through the interlay dielectric 23 to form an electrical connection with the emitter regions 7 and the P type active base regions 5-i. A heavily doped P+ type region 8 is further provided at the interface between each vertical connector 22 and the corresponding P type active base region 5-i, so as to reduce the contact resistance between the connector 22 and the active base region 5-i. The reduced contact resistance is useful in that it allows excess holes injected from the P+ type collector layer 3 into the N- drift layer 4 during an on-state of the IGBT 1 to easily flow towards the emitter electrode 21.
As shown in
The particular design rules between L1 and L2 are advantageous for keeping uniform electric field distribution on the chip front side, and accordingly improve the reliability of the IGBT 1. The chip front side refers to the top surface of a wafer on which the IGBT 1 is manufactured. If L2 is too long with respect to L1, the bottom of the insulation trenches 17 could suffer from higher electric field when the IGBT 1 is reversed biased (i.e., when VGE=0 and VCE is of a positive potential) thereby lowering the breakdown voltage of the IGBT 1. On the other hand, if L2 is too short with respect to L1, the IGBT 1 may suffer from higher short circuit current, thereby worsening the SCSOA performance of the IGBT 1.
Further, the particular design rules are useful for maintaining process uniformity and controllability. As described below in more detail, a semiconductor substrate may be etched to provide the insulation trenches 17 and the active gate trenches 9 simultaneously in a single dry etching step. With L2 being no longer than two times of L1, the lengths L1 and L2 are of comparable scales. As such, the etching depths of the semiconductor substrate may be maintained uniformly across the chip area. This means that the insulation trenches 17 and the active gate trenches 9 would have substantially the same depth along the Y axis. In addition, if L2 is too long with respect to L1, it may be difficult to control the process of filling the insulation trenches 17 with the dielectric material.
As described in more detail below, the insulation trenches 17 were formed by selectively etching the P type base layer 5 and the N- drift layer 4. The sidewalls of the insulation trenches 17 are parallel to the vertical Y axis as shown in
By adjusting the second length L2 of the insulation trenches 17, it is possible to adjust the current density of the IGBT 1, so as to meet a predefined performance requirement. For example, an IGBT may be required to deliver 200A current within a chip area of 1 cm*1cm. The required current density may be achieved by adjusting the ratio between the second length L2 and the first length L1.
In prior designs of IGBT, dummy semiconductor regions (also referred to as dummy regions) are commonly provided between adjacent active cells. The known dummy regions typically include a P type dummy base region (which is similar to a part of the P type base layer 5 of the IGBT 1, and may also be referred to as a dummy P well). The dummy base region is usually kept floating, meaning that it is not electronically connected to any electrode and thus has a floating potential. An example of the dummy region is for example shown as the P region 13 in
As compared to the known dummy regions, the use of the insulation trenches 17 between adjacent active cells 15 are advantageous for improving the SOA of the IGBT 1. This is explained in more detail below.
During an on state of the IGBT 1, the P+ type collector layer 3 injects a large amount of excess holes into the N- drift layer 4. Consequently, the carrier concentration in the highly-resistive N- drift layer 4 increases, causing its resistivity to decrease. This temporary increase in conductivity (i.e., a reduction in resistivity) during a conduction period is called conductivity modulation. When the IGBT 1 is switched from an on state to an off state, the excess holes in the N- drift layer 4 either flow into the emitter electrode 21, or are annihilated with excess electrons due to recombination. However, for the prior designs of IGBT which provides a dummy base region between adjacent active cells, the excess holes tend to accumulate within the dummy base region, causing the potential of the dummy base region to rise. The rising potential in the dummy base region may cause dynamic avalanche in the IGBT and thus limit the SOA of the IGBT. By using the insulation trenches 17 to replace the dummy base regions, the IGBT 1 of the present disclosure significantly reduces the accumulation of the excess holes within the substrate 2 when the IGBT 1 is switched from an on state to an off state. Accordingly, the IGBT 1 has a reduced risk of dynamic avalanche and an improved SOA.
The use of the insulation trenches 17 between adjacent active cells 15 are also advantageous for improving the switching controllability and reducing switching loss and the EMI noise of the IGBT 1. This is explained in more detail below.
The gate capacitance of an IGBT affects the switching loss and the switching controllability of an IGBT. The gate capacitance includes the gate-emitter capacitance (CGE) and the miller capacitance (CGC).
By providing the insulation trenches 17 between neighbouring ones of the active cells 15, the gate-emitter capacitance (CGE) of the IGBT 1 is significantly reduced by an amount which is equal to the gate-emitter capacitance (CGE) of a trench gate structure (either an active trench gate or a dummy trench gate) which otherwise could be provided at the locations of the insulation trenches 17.
The Miller capacitance CGC exists due to the internal structure of an IGBT, and can be considered as including two individual capacitances arranged in series. The first capacitance results from to the oxide layer (e.g., the gate insulator 11) of the gate and has a constant value. The second capacitance represents the capacitive coupling between the collector and the emitter. Being a thick dielectric layer, the insulation trenches 17 significantly reduce the capacitive coupling between the emitter electrode 21 and the collector electrode 19. Therefore, the use of the insulation trenches 17 is also beneficial for reducing the miller capacitance of the IGBT.
Since the use of the insulation trenches 17 reduce both the gate-emitter capacitance (CGE) and the miller capacitance (CGC), the gate capacitance of the IGBT 1 can be charged and discharged at a faster speed than the prior designs, thereby achieving a reduced switching loss and an improved switching controllability.
Further, in the prior IGBT designs, there are significant parasitic capacitances associated with the dummy base regions and the dummy gate trenches, and the parasitic capacitances cause oscillations and create unpleasant noises during the on/off switching of the IGBT 1. By using the insulation trenches 17 to replace the dummy base regions and the dummy gate trenches, the parasitic capacitances within the device are reduced, and accordingly the EMI noise generated by the IGBT 1 is reduced.
Therefore, as compared to the prior IGBT designs which provide dummy semiconductor regions between neighbouring active cells, the use of the insulation trenches 17 to replace such dummy regions improves the SOA and the switching controllability, and reduces switching loss and the EMI noise of the IGBT 1, while providing a similar level of current density. The length L2 of the insulation trenches 17 along the X axis follows the design rule of 0.5 ≤ L2/L1 ≤ 2 to keep uniform electric field distribution on the chip front side (thereby improving the reliability of the IGBT 1) and to maintain process uniformity and controllability.
In addition, the N type first implant zones 13 are useful for improving the conductivity modulation in the IGBT 1 by enhancing the carrier profile in the N- type drift layer 4 in an on state, thereby advantageously reducing VCE,sat of the IGBT 1. Therefore, the IGBT 1 presents an improved trade-off performance amongst the on-state voltage drop VCE,sat, the switching loss Esw and the safe operation area SOA. The IGBT 1 provides an improved efficiency as well as an improved reliability as compared to prior designs of IGBTs.
Further, the first implant zones 13 together with the insulation trenches 17 advantageously enable concurrent improvements in VCE,sat and SOA of the IGBT 1 as compared to prior IGBT designs in which active cells are immediately next to each other. More specifically, by providing the insulation trenches 17 between neighbouring ones of the active cells 15, the IGBT 1 has a reduced channel density relative to a typical IGBT design. The reduced channel density results in an improved SOA (in particular, SCSOA). Normally, the reduced channel density would also cause an increase of VCE,sat. However, with the first implant zone 13, it is possible to maintain VCE,sat at the same level or even to reduce VCE,sat as compared to the prior designs.
The N type buffer layer 6 may also be referred to as a field stop layer, because it terminates the electrical field within the IGBT 1. The buffer layer 6 is useful for reducing the on-state voltage drop VCE,sat of the IGBT 1, and makes the IGBT 1 a punch-through (PT) IGBT. It would be appreciated that the N type buffer layer 6 may be omitted. It would further be appreciated that the first implant zones 13 may also be omitted.
The IGBT 1A includes a plurality of active cells 15A and a plurality of insulation trenches 17. In contrast to the active cells 15 each of which provides two current channels at opposite sides of the respective active gate trench 9, each active cell 15A provides a single current channel at one side of its active gate trench 9. As shown in
The dummy base regions 5-ii may have a floating potential. Alternatively, the dummy base regions 5-ii may be electrically connected to the emitter electrode 21 (which is normally grounded for an N-channel IGBT such as the IGBT 1A).
Further, although
It would be understood that with the same lengths L1 and L2, the IGBT 1A has a lower channel density than the IGBT 1 due to the fact that there is no current flowing through the dummy base regions 5-ii during the on state of the IGBT 1A. Accordingly, the IGBT 1A generally provides a lower current density, which is approximately a half of the current density achievable by the IGBT 1. Therefore, the IGBT 1A is useful for applications requiring a lower current density.
In the IGBT 1B, a plurality of active cells 15, a plurality of insulation trenches 17 as well as a plurality of dummy cells 15B are formed within the semiconductor substrate 2. As illustrated in
It would be appreciated that more than one dummy cell 15B may be provided between two adjacent active cells 15. In that case, an insulation trench 17 would be provided between each dummy cell 15B and its neighbouring dummy or active cell so as to isolate the cells (whether active or dummy) from one another. In other words, a combination of M (M being an integer ≥ 2) dummy cell 15B and M+1 insulation trenches 17 may be provided immediately between two adjacent active cells 15 along the X axis.
As described above, the expression “active cell” means that the respective cell would provide at least one conducting channel during an on-state of the IGBT. Conversely, the expression “dummy cell” means that the respective cell would not be able to provide any conducting current channel during the on state of the IGBT. Each dummy cell 15B comprises a dummy gate trench 9B. Each dummy gate trench 9B comprises a gate insulator 11B which for example may be a thin layer of oxide film, and a dummy gate electrode 10B which for example may be made of polysilicon. The expressions “dummy gate electrode” and “dummy gate trench” mean that the respective gate electrode within the corresponding gate trench is not a control electrode, and cannot be used to control the on/off switching of any current channel of the IGBT 1B.
As shown in
There is no emitter region within any of the dummy base regions 5-ii. Therefore, there is no current channel flowing through any of the dummy cells 15B during the on state of the IGBT 1B. However, each active cell 15 is able to provide two current channels along the two sidewalls of the active gate trench 9.
As shown in
The lengths L1 and L2 in the IGBT 1B still satisfy the design rule of 0.5 ≤ L2/L1 ≤ 2. More preferably, the lengths L1 and L2 satisfy the design rule of L2/L1 ≤ 1.7, or most preferably L2/L1 ≤ 1.5, and/or L2/L1 ≥ 1. Since the dummy cells 15B and the active cells 15 are both semiconductor regions formed in the substrate 2 and are designed to have very similar structures and configurations, the particular design rules between L1 and L2 remains useful for keeping uniform electric field distribution on the chip front side, and for maintaining process uniformity and controllability.
It would be understood that with the same lengths L1 and L2, the IGBT 1B has a lower channel density than the IGBT 1 due to the fact that the dummy cells 15B do not provide any conducting channel during the on state of the IGBT 1B. Accordingly, the IGBT 1B generally provides a lower current density, which is approximately a half of the current density achievable by the IGBT 1. Therefore, the IGBT 1B is useful for applications requiring a lower current density.
As described above, the IGBT 1 uses its insulation trenches 17 to replace the entirety of the dummy semiconductor regions used in prior designs. Turning to
The dummy base regions 5-ii and the dummy gate electrodes 10B of the IGBT 1B may be electrically connected to the emitter electrode 21 which is normally grounded, or may be floating. Alternatively, dummy gate electrodes 10B may be electrically connected to the active gate electrode.
It would be appreciated that the dummy gate trench 9B (including the gate insulator 11B and the dummy gate electrode 10B) may be omitted such that each dummy cell 15B only includes the dummy base region 5-ii and the first implant zone 13. In that case, each of the dummy base region 5-ii and the first implant zone 13 would have a length equal to L1 along the X axis.
The structure of the IGBT 1C is similar to that of the IGBT 1B. However, the dummy cells 15C of the IGBT 1C do not have any of the first implant zones 13.
As compared to the IGBT 1C, the IGBT 1D has additional second implant zones 25. The second implant zones 25 are P type, and are formed by implantation. Therefore, all of the second implant zones 25 may be formed in the substrate 2 simultaneously. As shown in
The second implant zones 25 under the gate trenches 9, 9B are useful in that they shield the bottom of the gate trenches 9, 9B from the bombing holes injected by the P+ collector layer 3 during an on state of the IGBT 1D. Accordingly, the gate trenches 9, 9B are protected by the second implant zones 25 from trapping holes bombing from the collector layer 3. As a result, the second implant zones 25 under the gate trenches 9, 9B (in particular, the active gate trenches 9) improve the reliability of the IGBT 1D. Further, the second implant zones 25 under the gate trenches 9, 9B provide better blocking capability. Being P type, the second implant zones 25 under the gate trenches 9, 9B are useful for depleting the N- drift layer 4 in the blocking state, thereby supporting a high breakdown voltage for the IGBT 1D.
The second implant zones 25 under the gate trenches 9, 9B may be floating, i.e., not electrically connected to any electrodes of the IGBT 1D.
As further shown in
The second implant zones 25 under the insulation trenches 17 may be electrically connected to the emitter electrode 21 which is normally grounded.
It would be appreciated that the second implant zones 25 may be provided within each of the IGBTs 1, 1A, 1B and 1C described above. It would also be appreciated that the second implant zones 25 between the insulation trenches 17 and the N- drift layer 4 may be omitted, such that the second implant zones 25 are only formed under the gate trenches 9 and 9B. It would further be understood that the second implant zones 25 under the dummy gate trenches 9B may also be omitted, such that the second implant zones 25 are only formed under the active gate trenches 9.
The IGBTs described above are all N-channel IGBTs. It would be appreciated that the doping types of each region/layer may be changed to the opposite doping types so as to provide P-channel IGBTs.
At the first step as illustrated by
At the second step as illustrated by
After the gate oxide layer 11, 11B is formed, another implantation step (not shown in
At the third step as illustrated by
At the fourth step as illustrated by
At the sixth step as illustrated by
Further, N type dopants (e.g., Phosphorous) are selectively implanted into the substrate 2 with a high ion energy (e.g., >2.0 MeV) to form the first implant zones 13 within the active cells 15. Thermal annealing follows to activate the implanted N type dopants. High ion energy is required because of the depth of the first implant zones 13 within the substrate 2.
At the seventh step as illustrated by
At the eighth step as illustrated by
At the ninth step as illustrated by
While the above paragraphs only describe the methods for manufacturing the IGBTs 1C and 1D, it would be understood that the described methods may be easily adapted (by for example modifying the masks used during the implantation and etching steps) in order to manufacture the IGBTs of other embodiments.
While the embodiments described above refer to IGBTs only, it would be appreciated that the present disclosure may be applied to other types of power semiconductor devices.
The skilled person will understand that in the preceding description and appended claims, positional terms such as ‘top’, ‘bottom’, ‘under’, ‘lateral’, ‘vertical’, etc. are made with reference to conceptual illustrations of a power semiconductor device, such as those showing standard cross sectional views and those shown in the appended drawings. These terms are used for ease of reference but are not intended to be of limiting nature. These terms are therefore to be understood as referring to a semiconductor structure when in an orientation as shown in the accompanying drawings.
Although the disclosure has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the disclosure, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2021/084443 | 3/31/2021 | WO |
